2 * arch/arm/mach-tegra/pm.c
4 * CPU complex suspend & resume functions for Tegra SoCs
6 * Copyright (c) 2009-2011, NVIDIA Corporation.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
23 #include <linux/kernel.h>
24 #include <linux/ctype.h>
25 #include <linux/init.h>
27 #include <linux/sched.h>
28 #include <linux/smp.h>
29 #include <linux/irq.h>
30 #include <linux/interrupt.h>
31 #include <linux/clk.h>
32 #include <linux/err.h>
33 #include <linux/debugfs.h>
34 #include <linux/delay.h>
35 #include <linux/suspend.h>
36 #include <linux/slab.h>
37 #include <linux/serial_reg.h>
38 #include <linux/seq_file.h>
39 #include <linux/uaccess.h>
40 #include <linux/syscore_ops.h>
42 #include <asm/cacheflush.h>
43 #include <asm/cpu_pm.h>
44 #include <asm/hardware/cache-l2x0.h>
45 #include <asm/hardware/gic.h>
46 #include <asm/localtimer.h>
47 #include <asm/pgalloc.h>
48 #include <asm/tlbflush.h>
51 #include <mach/iomap.h>
52 #include <mach/irqs.h>
53 #include <mach/powergate.h>
63 struct suspend_context {
65 * The next 7 values are referenced by offset in __restart_plls
66 * in headsmp-t2.S, and should not be moved
84 #ifdef CONFIG_PM_SLEEP
85 static DEFINE_SPINLOCK(tegra_lp2_lock);
86 static cpumask_t tegra_in_lp2;
88 static unsigned long iram_save_size;
89 static void __iomem *iram_code = IO_ADDRESS(TEGRA_IRAM_CODE_AREA);
90 static void __iomem *clk_rst = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
91 static void __iomem *evp_reset =
92 IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100;
93 static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
96 struct suspend_context tegra_sctx;
98 #define TEGRA_POWER_PWRREQ_POLARITY (1 << 8) /* core power request polarity */
99 #define TEGRA_POWER_PWRREQ_OE (1 << 9) /* core power request enable */
100 #define TEGRA_POWER_SYSCLK_POLARITY (1 << 10) /* sys clk polarity */
101 #define TEGRA_POWER_SYSCLK_OE (1 << 11) /* system clock enable */
102 #define TEGRA_POWER_PWRGATE_DIS (1 << 12) /* power gate disabled */
103 #define TEGRA_POWER_EFFECT_LP0 (1 << 14) /* enter LP0 when CPU pwr gated */
104 #define TEGRA_POWER_CPU_PWRREQ_POLARITY (1 << 15) /* CPU power request polarity */
105 #define TEGRA_POWER_CPU_PWRREQ_OE (1 << 16) /* CPU power request enable */
108 #define PMC_CTRL_LATCH_WAKEUPS (1 << 5)
109 #define PMC_WAKE_MASK 0xc
110 #define PMC_WAKE_LEVEL 0x10
111 #define PMC_DPAD_ORIDE 0x1C
112 #define PMC_WAKE_DELAY 0xe0
113 #define PMC_DPD_SAMPLE 0x20
115 #define PMC_WAKE_STATUS 0x14
116 #define PMC_SW_WAKE_STATUS 0x18
117 #define PMC_COREPWRGOOD_TIMER 0x3c
118 #define PMC_SCRATCH0 0x50
119 #define PMC_SCRATCH1 0x54
120 #define PMC_CPUPWRGOOD_TIMER 0xc8
121 #define PMC_CPUPWROFF_TIMER 0xcc
122 #define PMC_COREPWROFF_TIMER PMC_WAKE_DELAY
124 #define CLK_RESET_CCLK_BURST 0x20
125 #define CLK_RESET_CCLK_DIVIDER 0x24
126 #define CLK_RESET_PLLC_BASE 0x80
127 #define CLK_RESET_PLLM_BASE 0x90
128 #define CLK_RESET_PLLX_BASE 0xe0
129 #define CLK_RESET_PLLX_MISC 0xe4
130 #define CLK_RESET_PLLP_BASE 0xa0
131 #define CLK_RESET_PLLP_OUTA 0xa4
132 #define CLK_RESET_PLLP_OUTB 0xa8
133 #define CLK_RESET_PLLP_MISC 0xac
135 #define CLK_RESET_SOURCE_CSITE 0x1d4
137 #define CLK_RESET_CCLK_BURST_POLICY_SHIFT 28
138 #define CLK_RESET_CCLK_BURST_POLICY_PLLM 3
139 #define CLK_RESET_CCLK_BURST_POLICY_PLLX 8
141 #define EMC_MRW_0 0x0e8
142 #define EMC_MRW_DEV_SELECTN 30
143 #define EMC_MRW_DEV_NONE (3 << EMC_MRW_DEV_SELECTN)
145 #define MC_SECURITY_START 0x6c
146 #define MC_SECURITY_SIZE 0x70
147 #define MC_SECURITY_CFG2 0x7c
149 phys_addr_t tegra_pgd_phys; /* pgd used by hotplug & LP2 bootup */
150 static pgd_t *tegra_pgd;
152 #ifdef CONFIG_PM_SLEEP
153 static int tegra_last_pclk;
155 static struct clk *tegra_pclk;
156 static const struct tegra_suspend_platform_data *pdata;
157 static enum tegra_suspend_mode current_suspend_mode = TEGRA_SUSPEND_NONE;
159 static const char *tegra_suspend_name[TEGRA_MAX_SUSPEND_MODE] = {
160 [TEGRA_SUSPEND_NONE] = "none",
161 [TEGRA_SUSPEND_LP2] = "lp2",
162 [TEGRA_SUSPEND_LP1] = "lp1",
163 [TEGRA_SUSPEND_LP0] = "lp0",
166 #if defined(CONFIG_PM_SLEEP) && INSTRUMENT_CLUSTER_SWITCH
167 enum tegra_cluster_switch_time_id {
168 tegra_cluster_switch_time_id_start = 0,
169 tegra_cluster_switch_time_id_prolog,
170 tegra_cluster_switch_time_id_switch,
171 tegra_cluster_switch_time_id_epilog,
172 tegra_cluster_switch_time_id_max
176 tegra_cluster_switch_times[tegra_cluster_switch_time_id_max];
177 #define tegra_cluster_switch_time(flags, id) \
180 if (flags & TEGRA_POWER_CLUSTER_MASK) { \
181 void __iomem *timer_us = \
182 IO_ADDRESS(TEGRA_TMRUS_BASE); \
183 if (id < tegra_cluster_switch_time_id_max) \
184 tegra_cluster_switch_times[id] = \
191 #define tegra_cluster_switch_time(flags, id) do {} while(0)
194 unsigned long tegra_cpu_power_good_time(void)
196 if (WARN_ON_ONCE(!pdata))
199 return pdata->cpu_timer;
202 unsigned long tegra_cpu_power_off_time(void)
204 if (WARN_ON_ONCE(!pdata))
207 return pdata->cpu_off_timer;
210 unsigned long tegra_cpu_lp2_min_residency(void)
212 if (WARN_ON_ONCE(!pdata))
215 return pdata->cpu_lp2_min_residency;
219 * create_suspend_pgtable
221 * Creates a page table with identity mappings of physical memory and IRAM
222 * for use when the MMU is off, in addition to all the regular kernel mappings.
224 static int create_suspend_pgtable(void)
226 tegra_pgd = pgd_alloc(&init_mm);
230 identity_mapping_add(tegra_pgd, PLAT_PHYS_OFFSET, IO_IRAM_PHYS);
231 identity_mapping_add(tegra_pgd, IO_IRAM_PHYS,
232 IO_IRAM_PHYS + SECTION_SIZE);
234 tegra_pgd_phys = virt_to_phys(tegra_pgd);
239 #ifdef CONFIG_PM_SLEEP
240 /* ensures that sufficient time is passed for a register write to
241 * serialize into the 32KHz domain */
242 static void pmc_32kwritel(u32 val, unsigned long offs)
244 writel(val, pmc + offs);
248 static void set_power_timers(unsigned long us_on, unsigned long us_off,
251 unsigned long long ticks;
252 unsigned long long pclk;
254 if (WARN_ON_ONCE(rate <= 0))
259 if (rate != tegra_last_pclk) {
260 ticks = (us_on * pclk) + 999999ull;
261 do_div(ticks, 1000000);
262 writel((unsigned long)ticks, pmc + PMC_CPUPWRGOOD_TIMER);
264 ticks = (us_off * pclk) + 999999ull;
265 do_div(ticks, 1000000);
266 writel((unsigned long)ticks, pmc + PMC_CPUPWROFF_TIMER);
269 tegra_last_pclk = pclk;
273 * restore_cpu_complex
275 * restores cpu clock setting, clears flow controller
277 * always called on cpu 0, even when suspend_cpu_complex was called on cpu 1
280 static void restore_cpu_complex(void)
285 /* restore original burst policy setting */
287 writel(tegra_sctx.pllx_misc, clk_rst + CLK_RESET_PLLX_MISC);
288 writel(tegra_sctx.pllx_base, clk_rst + CLK_RESET_PLLX_BASE);
289 writel(tegra_sctx.pllp_misc, clk_rst + CLK_RESET_PLLP_MISC);
290 writel(tegra_sctx.pllp_base, clk_rst + CLK_RESET_PLLP_BASE);
291 writel(tegra_sctx.pllp_outa, clk_rst + CLK_RESET_PLLP_OUTA);
292 writel(tegra_sctx.pllp_outb, clk_rst + CLK_RESET_PLLP_OUTB);
294 /* Is CPU complex already running on PLLX? */
295 reg = readl(clk_rst + CLK_RESET_CCLK_BURST);
298 /* restore original burst policy setting; PLLX state restored
299 * by CPU boot-up code - wait for PLL stabilization if PLLX
302 BUG_ON(readl(clk_rst + CLK_RESET_PLLX_BASE) !=
303 tegra_sctx.pllx_base);
305 if (tegra_sctx.pllx_base & (1<<30)) {
306 #if USE_PLL_LOCK_BITS
307 /* Enable lock detector */
308 reg = readl(clk_rst + CLK_RESET_PLLX_MISC);
310 writel(reg, clk_rst + CLK_RESET_PLLX_MISC);
311 while (!(readl(clk_rst + CLK_RESET_PLLX_BASE) &&
318 writel(tegra_sctx.cclk_divider, clk_rst +
319 CLK_RESET_CCLK_DIVIDER);
320 writel(tegra_sctx.cpu_burst, clk_rst +
321 CLK_RESET_CCLK_BURST);
324 writel(tegra_sctx.clk_csite_src, clk_rst + CLK_RESET_SOURCE_CSITE);
326 /* do not power-gate the CPU when flow controlled */
327 for (i = 0; i < num_possible_cpus(); i++) {
328 reg = readl(FLOW_CTRL_CPU_CSR(i));
329 reg &= ~FLOW_CTRL_CSR_WFE_BITMAP; /* clear wfe bitmap */
330 reg &= ~FLOW_CTRL_CSR_WFI_BITMAP; /* clear wfi bitmap */
331 reg &= ~FLOW_CTRL_CSR_ENABLE; /* clear enable */
332 reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr */
333 reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event */
334 flowctrl_writel(reg, FLOW_CTRL_CPU_CSR(i));
339 * suspend_cpu_complex
341 * saves pll state for use by restart_plls, prepares flow controller for
342 * transition to suspend state
344 * in suspend, always called on cpu 0
345 * in idle, called on the last cpu to request lp2
347 static void suspend_cpu_complex(void)
351 int cpu = smp_processor_id();
353 /* switch coresite to clk_m, save off original source */
354 tegra_sctx.clk_csite_src = readl(clk_rst + CLK_RESET_SOURCE_CSITE);
355 writel(3<<30, clk_rst + CLK_RESET_SOURCE_CSITE);
357 tegra_sctx.cpu_burst = readl(clk_rst + CLK_RESET_CCLK_BURST);
358 tegra_sctx.pllx_base = readl(clk_rst + CLK_RESET_PLLX_BASE);
359 tegra_sctx.pllx_misc = readl(clk_rst + CLK_RESET_PLLX_MISC);
360 tegra_sctx.pllp_base = readl(clk_rst + CLK_RESET_PLLP_BASE);
361 tegra_sctx.pllp_outa = readl(clk_rst + CLK_RESET_PLLP_OUTA);
362 tegra_sctx.pllp_outb = readl(clk_rst + CLK_RESET_PLLP_OUTB);
363 tegra_sctx.pllp_misc = readl(clk_rst + CLK_RESET_PLLP_MISC);
364 tegra_sctx.cclk_divider = readl(clk_rst + CLK_RESET_CCLK_DIVIDER);
366 reg = readl(FLOW_CTRL_CPU_CSR(cpu));
367 reg &= ~FLOW_CTRL_CSR_WFE_BITMAP; /* clear wfe bitmap */
368 reg &= ~FLOW_CTRL_CSR_WFI_BITMAP; /* clear wfi bitmap */
369 reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event flag */
370 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
371 reg |= FLOW_CTRL_CSR_WFE_CPU0 << cpu; /* enable power gating on wfe */
373 reg |= FLOW_CTRL_CSR_WFI_CPU0 << cpu; /* enable power gating on wfi */
375 reg |= FLOW_CTRL_CSR_ENABLE; /* enable power gating */
376 flowctrl_writel(reg, FLOW_CTRL_CPU_CSR(cpu));
378 for (i = 0; i < num_possible_cpus(); i++) {
381 reg = readl(FLOW_CTRL_CPU_CSR(i));
382 reg |= FLOW_CTRL_CSR_EVENT_FLAG;
383 reg |= FLOW_CTRL_CSR_INTR_FLAG;
384 flowctrl_writel(reg, FLOW_CTRL_CPU_CSR(i));
385 flowctrl_writel(0, FLOW_CTRL_HALT_CPU(i));
389 void tegra_clear_cpu_in_lp2(int cpu)
391 spin_lock(&tegra_lp2_lock);
392 cpumask_clear_cpu(cpu, &tegra_in_lp2);
393 spin_unlock(&tegra_lp2_lock);
396 bool tegra_set_cpu_in_lp2(int cpu)
398 bool last_cpu = false;
400 spin_lock(&tegra_lp2_lock);
402 cpumask_set_cpu(cpu, &tegra_in_lp2);
403 if (cpumask_equal(&tegra_in_lp2, cpu_online_mask))
405 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
407 tegra2_cpu_set_resettable_soon();
410 spin_unlock(&tegra_lp2_lock);
414 unsigned int tegra_idle_lp2_last(unsigned int sleep_time, unsigned int flags)
419 /* Only the last cpu down does the final suspend steps */
420 reg = readl(pmc + PMC_CTRL);
421 reg |= TEGRA_POWER_CPU_PWRREQ_OE;
422 reg |= TEGRA_POWER_PWRREQ_OE;
424 reg &= ~TEGRA_POWER_EFFECT_LP0;
425 pmc_32kwritel(reg, PMC_CTRL);
427 tegra_cluster_switch_time(flags, tegra_cluster_switch_time_id_start);
429 writel(virt_to_phys(tegra_resume), evp_reset);
432 * We can use clk_get_rate_all_locked() here, because all other cpus
433 * are in LP2 state and irqs are disabled
435 set_power_timers(pdata->cpu_timer, pdata->cpu_off_timer,
436 clk_get_rate_all_locked(tegra_pclk));
438 if (flags & TEGRA_POWER_CLUSTER_MASK)
439 tegra_cluster_switch_prolog(reg);
442 tegra_lp2_set_trigger(sleep_time);
444 cpu_complex_pm_enter();
446 suspend_cpu_complex();
447 tegra_cluster_switch_time(flags, tegra_cluster_switch_time_id_prolog);
452 tegra_sleep_cpu(PLAT_PHYS_OFFSET - PAGE_OFFSET);
454 #ifdef CONFIG_CACHE_L2X0
457 tegra_cluster_switch_time(flags, tegra_cluster_switch_time_id_switch);
458 restore_cpu_complex();
459 cpu_complex_pm_exit();
461 remain = tegra_lp2_timer_remain();
463 tegra_lp2_set_trigger(0);
465 if (flags & TEGRA_POWER_CLUSTER_MASK)
466 tegra_cluster_switch_epilog(reg);
468 tegra_cluster_switch_time(flags, tegra_cluster_switch_time_id_epilog);
470 #if INSTRUMENT_CLUSTER_SWITCH
471 if (flags & TEGRA_POWER_CLUSTER_MASK) {
472 pr_err("%s: prolog %lu us, switch %lu us, epilog %lu us, total %lu us\n",
473 is_lp_cluster() ? "G=>LP" : "LP=>G",
474 tegra_cluster_switch_times[tegra_cluster_switch_time_id_prolog] -
475 tegra_cluster_switch_times[tegra_cluster_switch_time_id_start],
476 tegra_cluster_switch_times[tegra_cluster_switch_time_id_switch] -
477 tegra_cluster_switch_times[tegra_cluster_switch_time_id_prolog],
478 tegra_cluster_switch_times[tegra_cluster_switch_time_id_epilog] -
479 tegra_cluster_switch_times[tegra_cluster_switch_time_id_switch],
480 tegra_cluster_switch_times[tegra_cluster_switch_time_id_epilog] -
481 tegra_cluster_switch_times[tegra_cluster_switch_time_id_start]);
487 static int tegra_common_suspend(void)
489 void __iomem *mc = IO_ADDRESS(TEGRA_MC_BASE);
491 tegra_sctx.mc[0] = readl(mc + MC_SECURITY_START);
492 tegra_sctx.mc[1] = readl(mc + MC_SECURITY_SIZE);
493 tegra_sctx.mc[2] = readl(mc + MC_SECURITY_CFG2);
495 /* copy the reset vector and SDRAM shutdown code into IRAM */
496 memcpy(iram_save, iram_code, iram_save_size);
497 memcpy(iram_code, tegra_iram_start(), iram_save_size);
502 static void tegra_common_resume(void)
504 void __iomem *mc = IO_ADDRESS(TEGRA_MC_BASE);
505 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
506 void __iomem *emc = IO_ADDRESS(TEGRA_EMC_BASE);
509 /* Clear DPD sample */
510 writel(0x0, pmc + PMC_DPD_SAMPLE);
512 writel(tegra_sctx.mc[0], mc + MC_SECURITY_START);
513 writel(tegra_sctx.mc[1], mc + MC_SECURITY_SIZE);
514 writel(tegra_sctx.mc[2], mc + MC_SECURITY_CFG2);
515 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
516 /* trigger emc mode write */
517 writel(EMC_MRW_DEV_NONE, emc + EMC_MRW_0);
519 /* clear scratch registers shared by suspend and the reset pen */
520 writel(0x0, pmc + PMC_SCRATCH39);
521 writel(0x0, pmc + PMC_SCRATCH41);
524 memcpy(iram_code, iram_save, iram_save_size);
527 static int tegra_suspend_prepare_late(void)
529 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
530 disable_irq(INT_SYS_STATS_MON);
535 static void tegra_suspend_wake(void)
537 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
538 enable_irq(INT_SYS_STATS_MON);
542 static void tegra_pm_set(enum tegra_suspend_mode mode)
545 unsigned long rate = 32768;
547 reg = readl(pmc + PMC_CTRL);
548 reg |= TEGRA_POWER_CPU_PWRREQ_OE;
549 reg |= TEGRA_POWER_PWRREQ_OE;
550 reg &= ~TEGRA_POWER_EFFECT_LP0;
553 case TEGRA_SUSPEND_LP0:
555 * lp0 boots through the AVP, which then resumes the AVP to
556 * the address in scratch 39, and the cpu to the address in
557 * scratch 41 to tegra_resume
559 writel(0x0, pmc + PMC_SCRATCH39);
560 __raw_writel(virt_to_phys(tegra_resume), pmc + PMC_SCRATCH41);
561 reg |= TEGRA_POWER_EFFECT_LP0;
563 /* Enable DPD sample to trigger sampling pads data and direction
564 * in which pad will be driven during lp0 mode*/
565 writel(0x1, pmc + PMC_DPD_SAMPLE);
567 case TEGRA_SUSPEND_LP1:
569 * lp1 boots through the normal cpu reset vector pointing to
570 * tegra_lp1_reset in IRAM, which resumes the CPU to
571 * the address in scratch 41 to tegra_resume
573 writel(tegra_lp1_reset() - tegra_iram_start() +
574 TEGRA_IRAM_CODE_AREA, evp_reset);
575 __raw_writel(virt_to_phys(tegra_resume), pmc + PMC_SCRATCH41);
577 case TEGRA_SUSPEND_LP2:
579 * lp2 boots through the normal cpu reset vector directly to
582 writel(virt_to_phys(tegra_resume), evp_reset);
583 rate = clk_get_rate(tegra_pclk);
589 set_power_timers(pdata->cpu_timer, pdata->cpu_off_timer, rate);
591 pmc_32kwritel(reg, PMC_CTRL);
593 /* Set warmboot flag */
594 reg = readl(pmc + PMC_SCRATCH0);
595 pmc_32kwritel(reg | 1, PMC_SCRATCH0);
597 pmc_32kwritel(tegra_lp0_vec_start, PMC_SCRATCH1);
600 static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = {
601 [TEGRA_SUSPEND_NONE] = "none",
602 [TEGRA_SUSPEND_LP2] = "LP2",
603 [TEGRA_SUSPEND_LP1] = "LP1",
604 [TEGRA_SUSPEND_LP0] = "LP0",
607 static int tegra_suspend_enter(suspend_state_t state)
609 return tegra_suspend_dram(current_suspend_mode);
612 static void tegra_suspend_check_pwr_stats(void)
614 /* cpus and l2 are powered off later */
615 unsigned long pwrgate_partid_mask =
616 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
617 (1 << TEGRA_POWERGATE_HEG) |
618 (1 << TEGRA_POWERGATE_SATA) |
619 (1 << TEGRA_POWERGATE_3D1) |
621 (1 << TEGRA_POWERGATE_3D) |
622 (1 << TEGRA_POWERGATE_VENC) |
623 (1 << TEGRA_POWERGATE_PCIE) |
624 (1 << TEGRA_POWERGATE_VDEC) |
625 (1 << TEGRA_POWERGATE_MPE);
629 for (partid = 0; partid < TEGRA_NUM_POWERGATE; partid++)
630 if ((1 << partid) & pwrgate_partid_mask)
631 if (tegra_powergate_is_powered(partid))
632 pr_warning("partition %s is left on before suspend\n",
633 tegra_powergate_get_name(partid));
638 int tegra_suspend_dram(enum tegra_suspend_mode mode)
640 BUG_ON(mode < 0 || mode >= TEGRA_MAX_SUSPEND_MODE);
642 if ((mode == TEGRA_SUSPEND_LP0) && !tegra_pm_irq_lp0_allowed()) {
643 pr_info("LP0 not used due to unsupported wakeup events\n");
644 mode = TEGRA_SUSPEND_LP1;
647 if ((mode == TEGRA_SUSPEND_LP0) || (mode == TEGRA_SUSPEND_LP1))
648 tegra_suspend_check_pwr_stats();
650 tegra_common_suspend();
652 pr_info("Entering suspend state %s\n", lp_state[mode]);
659 cpu_complex_pm_enter();
661 if (mode == TEGRA_SUSPEND_LP0)
662 tegra_lp0_suspend_mc();
664 suspend_cpu_complex();
669 if (mode == TEGRA_SUSPEND_LP2)
670 tegra_sleep_cpu(PLAT_PHYS_OFFSET - PAGE_OFFSET);
672 tegra_sleep_core(PLAT_PHYS_OFFSET - PAGE_OFFSET);
676 if (mode == TEGRA_SUSPEND_LP0)
677 tegra_lp0_resume_mc();
679 restore_cpu_complex();
681 cpu_complex_pm_exit();
686 tegra_common_resume();
692 * Function pointers to optional board specific function
694 void (*tegra_deep_sleep)(int);
695 EXPORT_SYMBOL(tegra_deep_sleep);
697 static int tegra_suspend_prepare(void)
699 if ((current_suspend_mode == TEGRA_SUSPEND_LP0) && tegra_deep_sleep)
704 static void tegra_suspend_finish(void)
706 if ((current_suspend_mode == TEGRA_SUSPEND_LP0) && tegra_deep_sleep)
710 static const struct platform_suspend_ops tegra_suspend_ops = {
711 .valid = suspend_valid_only_mem,
712 .prepare = tegra_suspend_prepare,
713 .finish = tegra_suspend_finish,
714 .prepare_late = tegra_suspend_prepare_late,
715 .wake = tegra_suspend_wake,
716 .enter = tegra_suspend_enter,
719 static ssize_t suspend_mode_show(struct kobject *kobj,
720 struct kobj_attribute *attr, char *buf)
723 char *end = buf + PAGE_SIZE;
725 start += scnprintf(start, end - start, "%s ", \
726 tegra_suspend_name[current_suspend_mode]);
727 start += scnprintf(start, end - start, "\n");
732 static ssize_t suspend_mode_store(struct kobject *kobj,
733 struct kobj_attribute *attr,
734 const char *buf, size_t n)
737 const char *name_ptr;
738 enum tegra_suspend_mode new_mode;
741 while (*name_ptr && !isspace(*name_ptr))
743 len = name_ptr - buf;
747 for (new_mode = TEGRA_SUSPEND_NONE; \
748 new_mode < TEGRA_MAX_SUSPEND_MODE; ++new_mode) {
749 if (!strncmp(buf, tegra_suspend_name[new_mode], len)) {
750 current_suspend_mode = new_mode;
759 static struct kobj_attribute suspend_mode_attribute =
760 __ATTR(mode, 0666, suspend_mode_show, suspend_mode_store);
762 static struct kobject *suspend_kobj;
765 void __init tegra_init_suspend(struct tegra_suspend_platform_data *plat)
770 tegra_pclk = clk_get_sys(NULL, "pclk");
771 BUG_ON(IS_ERR(tegra_pclk));
776 preset_lpj = loops_per_jiffy;
778 create_suspend_pgtable();
780 #ifdef CONFIG_PM_SLEEP
782 if ((tegra_get_chipid() == TEGRA_CHIPID_TEGRA3) &&
783 (tegra_get_revision() == TEGRA_REVISION_A01) &&
784 (plat->suspend_mode == TEGRA_SUSPEND_LP0)) {
785 /* Tegra 3 A01 supports only LP1 */
786 pr_warning("%s: Suspend mode LP0 is not supported on A01 "
787 "-- disabling LP0\n", __func__);
788 plat->suspend_mode = TEGRA_SUSPEND_LP1;
791 if (plat->suspend_mode == TEGRA_SUSPEND_LP0 && !tegra_lp0_vec_size) {
792 pr_warning("%s: Suspend mode LP0 requested, no lp0_vec "
793 "provided by bootlader -- disabling LP0\n",
795 plat->suspend_mode = TEGRA_SUSPEND_LP1;
798 iram_save_size = tegra_iram_end() - tegra_iram_start();
800 iram_save = kmalloc(iram_save_size, GFP_KERNEL);
802 pr_err("%s: unable to allocate memory for SDRAM self-refresh "
803 "-- LP0/LP1 unavailable\n", __func__);
804 plat->suspend_mode = TEGRA_SUSPEND_LP2;
807 /* !!!FIXME!!! THIS IS TEGRA2 ONLY */
808 /* Initialize scratch registers used for CPU LP2 synchronization */
809 writel(0, pmc + PMC_SCRATCH37);
810 writel(0, pmc + PMC_SCRATCH38);
811 writel(0, pmc + PMC_SCRATCH39);
812 writel(0, pmc + PMC_SCRATCH41);
814 /* Always enable CPU power request; just normal polarity is supported */
815 reg = readl(pmc + PMC_CTRL);
816 BUG_ON(reg & TEGRA_POWER_CPU_PWRREQ_POLARITY);
817 reg |= TEGRA_POWER_CPU_PWRREQ_OE;
818 pmc_32kwritel(reg, PMC_CTRL);
820 /* Configure core power request and system clock control if LP0
822 __raw_writel(pdata->core_timer, pmc + PMC_COREPWRGOOD_TIMER);
823 __raw_writel(pdata->core_off_timer, pmc + PMC_COREPWROFF_TIMER);
825 reg = readl(pmc + PMC_CTRL);
827 if (!pdata->sysclkreq_high)
828 reg |= TEGRA_POWER_SYSCLK_POLARITY;
830 reg &= ~TEGRA_POWER_SYSCLK_POLARITY;
832 if (!pdata->corereq_high)
833 reg |= TEGRA_POWER_PWRREQ_POLARITY;
835 reg &= ~TEGRA_POWER_PWRREQ_POLARITY;
837 /* configure output inverters while the request is tristated */
838 pmc_32kwritel(reg, PMC_CTRL);
840 /* now enable requests */
841 reg |= TEGRA_POWER_SYSCLK_OE;
842 reg |= TEGRA_POWER_PWRREQ_OE;
843 pmc_32kwritel(reg, PMC_CTRL);
845 if (pdata->suspend_mode == TEGRA_SUSPEND_LP0)
846 tegra_lp0_suspend_init();
848 suspend_set_ops(&tegra_suspend_ops);
850 /* Create /sys/power/suspend/type */
851 suspend_kobj = kobject_create_and_add("suspend", power_kobj);
853 if (sysfs_create_file(suspend_kobj, \
854 &suspend_mode_attribute.attr))
855 pr_err("%s: sysfs_create_file suspend type failed!\n",
859 #ifdef CONFIG_CPU_IDLE
860 if (plat->suspend_mode == TEGRA_SUSPEND_NONE)
861 tegra_lp2_in_idle(false);
864 if (plat->suspend_mode != TEGRA_SUSPEND_NONE) {
865 pr_warning("%s: Suspend requires CONFIG_PM_SLEEP -- "
866 "disabling suspend\n", __func__);
867 plat->suspend_mode = TEGRA_SUSPEND_NONE;
871 current_suspend_mode = plat->suspend_mode;
874 static int tegra_debug_uart_suspend(void)
879 if (TEGRA_DEBUG_UART_BASE == 0)
882 uart = IO_ADDRESS(TEGRA_DEBUG_UART_BASE);
884 lcr = readb(uart + UART_LCR * 4);
886 tegra_sctx.uart[0] = lcr;
887 tegra_sctx.uart[1] = readb(uart + UART_MCR * 4);
890 writeb(lcr & ~UART_LCR_DLAB, uart + UART_LCR * 4);
892 tegra_sctx.uart[2] = readb(uart + UART_IER * 4);
895 writeb(lcr | UART_LCR_DLAB, uart + UART_LCR * 4);
897 tegra_sctx.uart[3] = readb(uart + UART_DLL * 4);
898 tegra_sctx.uart[4] = readb(uart + UART_DLM * 4);
900 writeb(lcr, uart + UART_LCR * 4);
905 static void tegra_debug_uart_resume(void)
910 if (TEGRA_DEBUG_UART_BASE == 0)
913 uart = IO_ADDRESS(TEGRA_DEBUG_UART_BASE);
915 lcr = tegra_sctx.uart[0];
917 writeb(tegra_sctx.uart[1], uart + UART_MCR * 4);
920 writeb(lcr & ~UART_LCR_DLAB, uart + UART_LCR * 4);
922 writeb(tegra_sctx.uart[2], uart + UART_IER * 4);
925 writeb(lcr | UART_LCR_DLAB, uart + UART_LCR * 4);
927 writeb(tegra_sctx.uart[3], uart + UART_DLL * 4);
928 writeb(tegra_sctx.uart[4], uart + UART_DLM * 4);
930 writeb(lcr, uart + UART_LCR * 4);
933 static struct syscore_ops tegra_debug_uart_syscore_ops = {
934 .suspend = tegra_debug_uart_suspend,
935 .resume = tegra_debug_uart_resume,
938 static int tegra_debug_uart_syscore_init(void)
940 register_syscore_ops(&tegra_debug_uart_syscore_ops);
943 arch_initcall(tegra_debug_uart_syscore_init);
945 #ifdef CONFIG_DEBUG_FS
946 static int tegra_suspend_debug_show(struct seq_file *s, void *data)
948 seq_printf(s, "%s\n", tegra_suspend_name[*(int *)s->private]);
952 static int tegra_suspend_debug_open(struct inode *inode, struct file *file)
954 return single_open(file, tegra_suspend_debug_show, inode->i_private);
957 static int tegra_suspend_debug_write(struct file *file,
958 const char __user *user_buf, size_t count, loff_t *ppos)
963 struct seq_file *s = file->private_data;
964 enum tegra_suspend_mode *val = s->private;
966 memset(buf, 0x00, sizeof(buf));
967 buf_size = min(count, (sizeof(buf)-1));
968 if (copy_from_user(buf, user_buf, buf_size))
971 for (i = 0; i < TEGRA_MAX_SUSPEND_MODE; i++) {
972 if (!strnicmp(buf, tegra_suspend_name[i],
973 strlen(tegra_suspend_name[i]))) {
974 if (i > pdata->suspend_mode)
984 static const struct file_operations tegra_suspend_debug_fops = {
985 .open = tegra_suspend_debug_open,
986 .write = tegra_suspend_debug_write,
989 .release = single_release,
992 static int __init tegra_suspend_debug_init(void)
996 d = debugfs_create_file("suspend_mode", 0755, NULL,
997 (void *)¤t_suspend_mode, &tegra_suspend_debug_fops);
999 pr_info("Failed to create suspend_mode debug file\n");
1006 late_initcall(tegra_suspend_debug_init);