2 * linux/arch/arm/mach-tegra/platsmp.c
4 * Copyright (C) 2002 ARM Ltd.
7 * Copyright (C) 2009 Palm
10 * Copyright (C) 2010-2011 NVIDIA Corporation
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/init.h>
20 #include <linux/smp.h>
21 #include <linux/delay.h>
22 #include <linux/clk.h>
23 #include <linux/cpumask.h>
25 #include <asm/hardware/gic.h>
26 #include <asm/smp_scu.h>
28 #include <mach/iomap.h>
29 #include <mach/powergate.h>
35 #include "cpu-tegra.h"
37 bool tegra_all_cpus_booted;
39 static DECLARE_BITMAP(tegra_cpu_init_bits, CONFIG_NR_CPUS) __read_mostly;
40 const struct cpumask *const tegra_cpu_init_mask = to_cpumask(tegra_cpu_init_bits);
41 #define tegra_cpu_init_map (*(cpumask_t *)tegra_cpu_init_mask)
43 #define CLK_RST_CONTROLLER_CLK_CPU_CMPLX \
44 (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x4c)
45 #define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET \
46 (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x340)
47 #define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR \
48 (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x344)
50 #define CPU_CLOCK(cpu) (0x1<<(8+cpu))
51 #define CPU_RESET(cpu) (0x1111ul<<(cpu))
53 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
54 #define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR \
55 (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x34c)
56 #define CAR_BOND_OUT_V \
57 (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x390)
58 #define CAR_BOND_OUT_V_CPU_G (1<<0)
61 static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
63 static unsigned int available_cpus(void)
65 static unsigned int ncores;
68 ncores = scu_get_core_count(scu_base);
69 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
71 u32 fuse_sku = readl(FUSE_SKU_DIRECT_CONFIG);
72 ncores -= FUSE_SKU_NUM_DISABLED_CPUS(fuse_sku);
73 BUG_ON((int)ncores <= 0);
80 static int is_g_cluster_available(unsigned int cpu)
82 #ifdef CONFIG_TEGRA_CLUSTER_CONTROL
83 u32 fuse_sku = readl(FUSE_SKU_DIRECT_CONFIG);
84 u32 bond_out = readl(CAR_BOND_OUT_V);
86 /* Does the G CPU complex exist at all? */
87 if ((fuse_sku & FUSE_SKU_DISABLE_ALL_CPUS) ||
88 (bond_out & CAR_BOND_OUT_V_CPU_G))
91 if (cpu >= available_cpus())
94 /* FIXME: The G CPU can be unavailable for a number of reasons
95 * (e.g., low battery, over temperature, etc.). Add checks for
96 * these conditions. */
103 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
104 static bool is_cpu_powered(unsigned int cpu)
109 return tegra_powergate_is_powered(TEGRA_CPU_POWERGATE_ID(cpu));
113 static int power_up_cpu(unsigned int cpu)
117 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
118 unsigned long timeout;
120 BUG_ON(cpu == smp_processor_id());
121 BUG_ON(is_lp_cluster());
123 /* If this cpu has booted this function is entered after
124 * CPU has been already un-gated by flow controller. Wait
125 * for confirmation that cpu is powered and remove clamps.
126 * On first boot entry do not wait - go to direct ungate.
128 if (cpu_isset(cpu, tegra_cpu_init_map)) {
129 timeout = jiffies + 5;
131 if (is_cpu_powered(cpu))
134 } while (time_before(jiffies, timeout));
137 /* First boot or Flow controller did not work as expected. Try to
138 directly toggle power gates. Error if direct power on also fails. */
139 if (!is_cpu_powered(cpu)) {
140 ret = tegra_unpowergate_partition(TEGRA_CPU_POWERGATE_ID(cpu));
144 /* Wait for the power to come up. */
145 timeout = jiffies + 10*HZ;
148 if (is_cpu_powered(cpu))
151 } while (time_before(jiffies, timeout));
157 /* CPU partition is powered. Enable the CPU clock. */
158 writel(CPU_CLOCK(cpu), CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
159 reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
162 /* Remove I/O clamps. */
163 ret = tegra_powergate_remove_clamping(TEGRA_CPU_POWERGATE_ID(cpu));
167 /* Enable the CPU clock. */
168 reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
169 writel(reg & ~CPU_CLOCK(cpu), CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
171 reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
173 /* Clear flow controller CSR. */
174 flowctrl_writel(0, FLOW_CTRL_CPU_CSR(cpu));
178 void __cpuinit platform_secondary_init(unsigned int cpu)
180 gic_secondary_init(0);
182 cpumask_set_cpu(cpu, to_cpumask(tegra_cpu_init_bits));
183 if (!tegra_all_cpus_booted)
184 if (cpumask_equal(tegra_cpu_init_mask, cpu_present_mask))
185 tegra_all_cpus_booted = true;
188 int boot_secondary(unsigned int cpu, struct task_struct *idle)
192 /* Avoid timer calibration on slave cpus. Use the value calibrated
193 * on master cpu. This reduces the bringup time for each slave cpu
196 preset_lpj = loops_per_jiffy;
197 if (is_lp_cluster()) {
198 struct clk *cpu_clk, *cpu_g_clk;
200 /* The G CPU may not be available for a variety of reasons. */
201 status = is_g_cluster_available(cpu);
205 cpu_clk = tegra_get_clock_by_name("cpu");
206 cpu_g_clk = tegra_get_clock_by_name("cpu_g");
208 /* Switch to G CPU before continuing. */
209 if (!cpu_clk || !cpu_g_clk) {
210 /* Early boot, clock infrastructure is not initialized
211 - CPU mode switch is not allowed */
214 #ifdef CONFIG_CPU_FREQ
215 /* set cpu rate is within g-mode range before switch */
216 unsigned int speed = max(
217 (unsigned long)tegra_getspeed(0),
218 clk_get_min_rate(cpu_g_clk) / 1000);
219 tegra_update_cpu_speed(speed);
221 status = clk_set_parent(cpu_clk, cpu_g_clk);
230 /* Force the CPU into reset. The CPU must remain in reset when the
231 flow controller state is cleared (which will cause the flow
232 controller to stop driving reset if the CPU has been power-gated
233 via the flow controller). This will have no effect on first boot
234 of the CPU since it should already be in reset. */
235 writel(CPU_RESET(cpu), CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
238 /* Unhalt the CPU. If the flow controller was used to power-gate the
239 CPU this will cause the flow controller to stop driving reset.
240 The CPU will remain in reset because the clock and reset block
241 is now driving reset. */
242 flowctrl_writel(0, FLOW_CTRL_HALT_CPU(cpu));
244 status = power_up_cpu(cpu);
248 /* Take the CPU out of reset. */
249 writel(CPU_RESET(cpu), CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
256 * Initialise the CPU possible map early - this describes the CPUs
257 * which may be present or become present in the system.
259 void __init smp_init_cpus(void)
261 unsigned int ncores = available_cpus();
264 if (ncores > nr_cpu_ids) {
265 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
270 for (i = 0; i < ncores; i++)
271 set_cpu_possible(i, true);
273 /* If only one CPU is possible, platform_smp_prepare_cpus() will
274 never get called. We must therefore initialize the reset handler
275 here. If there is more than one CPU, we must wait until after
276 the cpu_present_mask has been updated with all present CPUs in
277 platform_smp_prepare_cpus() before initializing the reset handler. */
279 tegra_cpu_reset_handler_init();
280 tegra_all_cpus_booted = true;
283 set_smp_cross_call(gic_raise_softirq);
286 void __init platform_smp_prepare_cpus(unsigned int max_cpus)
289 /* Always mark the boot CPU as initialized. */
290 cpumask_set_cpu(0, to_cpumask(tegra_cpu_init_bits));
293 tegra_all_cpus_booted = true;
295 /* If we're here, it means that more than one CPU was found by
296 smp_init_cpus() which also means that it did not initialize the
297 reset handler. Do it now before the secondary CPUs are started. */
298 tegra_cpu_reset_handler_init();
300 #if defined(CONFIG_HAVE_ARM_SCU)
302 u32 scu_ctrl = __raw_readl(scu_base) |
303 1 << 3 | /* Enable speculative line fill*/
304 1 << 5 | /* Enable IC standby */
305 1 << 6; /* Enable SCU standby */
307 __raw_writel(scu_ctrl, scu_base);
310 scu_enable(scu_base);