Ventana: KBC: Removing the KBC usage on ventana
[linux-2.6.git] / arch / arm / mach-tegra / pinmux.c
1 /*
2  * linux/arch/arm/mach-tegra/pinmux.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Copyright (C) 2011 NVIDIA Corporation.
6  *
7  * This software is licensed under the terms of the GNU General Public
8  * License version 2, as published by the Free Software Foundation, and
9  * may be copied, distributed, and modified under those terms.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/errno.h>
22 #include <linux/spinlock.h>
23 #include <linux/io.h>
24
25 #include <mach/iomap.h>
26 #include <mach/pinmux.h>
27
28 #define HSM_EN(reg)     (((reg) >> 2) & 0x1)
29 #define SCHMT_EN(reg)   (((reg) >> 3) & 0x1)
30 #define LPMD(reg)       (((reg) >> 4) & 0x3)
31 #define DRVDN(reg)      (((reg) >> 12) & 0x1f)
32 #define DRVUP(reg)      (((reg) >> 20) & 0x1f)
33 #define SLWR(reg)       (((reg) >> 28) & 0x3)
34 #define SLWF(reg)       (((reg) >> 30) & 0x3)
35
36 static const struct tegra_pingroup_desc *const pingroups = tegra_soc_pingroups;
37 static const struct tegra_drive_pingroup_desc *const drive_pingroups = tegra_soc_drive_pingroups;
38
39 static char *tegra_mux_names[TEGRA_MAX_MUX] = {
40         [TEGRA_MUX_AHB_CLK] = "AHB_CLK",
41         [TEGRA_MUX_APB_CLK] = "APB_CLK",
42         [TEGRA_MUX_AUDIO_SYNC] = "AUDIO_SYNC",
43         [TEGRA_MUX_CRT] = "CRT",
44         [TEGRA_MUX_DAP1] = "DAP1",
45         [TEGRA_MUX_DAP2] = "DAP2",
46         [TEGRA_MUX_DAP3] = "DAP3",
47         [TEGRA_MUX_DAP4] = "DAP4",
48         [TEGRA_MUX_DAP5] = "DAP5",
49         [TEGRA_MUX_DISPLAYA] = "DISPLAYA",
50         [TEGRA_MUX_DISPLAYB] = "DISPLAYB",
51         [TEGRA_MUX_EMC_TEST0_DLL] = "EMC_TEST0_DLL",
52         [TEGRA_MUX_EMC_TEST1_DLL] = "EMC_TEST1_DLL",
53         [TEGRA_MUX_GMI] = "GMI",
54         [TEGRA_MUX_GMI_INT] = "GMI_INT",
55         [TEGRA_MUX_HDMI] = "HDMI",
56         [TEGRA_MUX_I2C] = "I2C",
57         [TEGRA_MUX_I2C2] = "I2C2",
58         [TEGRA_MUX_I2C3] = "I2C3",
59         [TEGRA_MUX_IDE] = "IDE",
60         [TEGRA_MUX_IRDA] = "IRDA",
61         [TEGRA_MUX_KBC] = "KBC",
62         [TEGRA_MUX_MIO] = "MIO",
63         [TEGRA_MUX_MIPI_HS] = "MIPI_HS",
64         [TEGRA_MUX_NAND] = "NAND",
65         [TEGRA_MUX_OSC] = "OSC",
66         [TEGRA_MUX_OWR] = "OWR",
67         [TEGRA_MUX_PCIE] = "PCIE",
68         [TEGRA_MUX_PLLA_OUT] = "PLLA_OUT",
69         [TEGRA_MUX_PLLC_OUT1] = "PLLC_OUT1",
70         [TEGRA_MUX_PLLM_OUT1] = "PLLM_OUT1",
71         [TEGRA_MUX_PLLP_OUT2] = "PLLP_OUT2",
72         [TEGRA_MUX_PLLP_OUT3] = "PLLP_OUT3",
73         [TEGRA_MUX_PLLP_OUT4] = "PLLP_OUT4",
74         [TEGRA_MUX_PWM] = "PWM",
75         [TEGRA_MUX_PWR_INTR] = "PWR_INTR",
76         [TEGRA_MUX_PWR_ON] = "PWR_ON",
77         [TEGRA_MUX_RTCK] = "RTCK",
78         [TEGRA_MUX_SDIO1] = "SDIO1",
79         [TEGRA_MUX_SDIO2] = "SDIO2",
80         [TEGRA_MUX_SDIO3] = "SDIO3",
81         [TEGRA_MUX_SDIO4] = "SDIO4",
82         [TEGRA_MUX_SFLASH] = "SFLASH",
83         [TEGRA_MUX_SPDIF] = "SPDIF",
84         [TEGRA_MUX_SPI1] = "SPI1",
85         [TEGRA_MUX_SPI2] = "SPI2",
86         [TEGRA_MUX_SPI2_ALT] = "SPI2_ALT",
87         [TEGRA_MUX_SPI3] = "SPI3",
88         [TEGRA_MUX_SPI4] = "SPI4",
89         [TEGRA_MUX_TRACE] = "TRACE",
90         [TEGRA_MUX_TWC] = "TWC",
91         [TEGRA_MUX_UARTA] = "UARTA",
92         [TEGRA_MUX_UARTB] = "UARTB",
93         [TEGRA_MUX_UARTC] = "UARTC",
94         [TEGRA_MUX_UARTD] = "UARTD",
95         [TEGRA_MUX_UARTE] = "UARTE",
96         [TEGRA_MUX_ULPI] = "ULPI",
97         [TEGRA_MUX_VI] = "VI",
98         [TEGRA_MUX_VI_SENSOR_CLK] = "VI_SENSOR_CLK",
99         [TEGRA_MUX_XIO] = "XIO",
100 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
101         [TEGRA_MUX_BLINK] = "BLINK",
102         [TEGRA_MUX_CEC] = "CEC",
103         [TEGRA_MUX_CLK12] = "CLK12",
104         [TEGRA_MUX_DAP] = "DAP",
105         [TEGRA_MUX_DAPSDMMC2] = "DAPSDMMC2",
106         [TEGRA_MUX_DDR] = "DDR",
107         [TEGRA_MUX_DEV3] = "DEV3",
108         [TEGRA_MUX_DTV] = "DTV",
109         [TEGRA_MUX_VI_ALT1] = "VI_ALT1",
110         [TEGRA_MUX_VI_ALT2] = "VI_ALT2",
111         [TEGRA_MUX_VI_ALT3] = "VI_ALT3",
112         [TEGRA_MUX_EMC_DLL] = "EMC_DLL",
113         [TEGRA_MUX_EXTPERIPH1] = "EXTPERIPH1",
114         [TEGRA_MUX_EXTPERIPH2] = "EXTPERIPH2",
115         [TEGRA_MUX_EXTPERIPH3] = "EXTPERIPH3",
116         [TEGRA_MUX_GMI_ALT] = "GMI_ALT",
117         [TEGRA_MUX_HDA] = "HDA",
118         [TEGRA_MUX_HSI] = "HSI",
119         [TEGRA_MUX_I2C4] = "I2C4",
120         [TEGRA_MUX_I2C5] = "I2C5",
121         [TEGRA_MUX_I2CPWR] = "I2CPWR",
122         [TEGRA_MUX_I2S0] = "I2S0",
123         [TEGRA_MUX_I2S1] = "I2S1",
124         [TEGRA_MUX_I2S2] = "I2S2",
125         [TEGRA_MUX_I2S3] = "I2S3",
126         [TEGRA_MUX_I2S4] = "I2S4",
127         [TEGRA_MUX_NAND_ALT] = "NAND_ALT",
128         [TEGRA_MUX_POPSDIO4] = "POPSDIO4",
129         [TEGRA_MUX_POPSDMMC4] = "POPSDMMC4",
130         [TEGRA_MUX_PWM0] = "PWM0",
131         [TEGRA_MUX_PWM1] = "PWM1",
132         [TEGRA_MUX_PWM2] = "PWM2",
133         [TEGRA_MUX_PWM3] = "PWM3",
134         [TEGRA_MUX_SATA] = "SATA",
135         [TEGRA_MUX_SPI5] = "SPI5",
136         [TEGRA_MUX_SPI6] = "SPI6",
137         [TEGRA_MUX_SYSCLK] = "SYSCLK",
138         [TEGRA_MUX_VGP1] = "VGP1",
139         [TEGRA_MUX_VGP2] = "VGP2",
140         [TEGRA_MUX_VGP3] = "VGP3",
141         [TEGRA_MUX_VGP4] = "VGP4",
142         [TEGRA_MUX_VGP5] = "VGP5",
143         [TEGRA_MUX_VGP6] = "VGP6",
144 #endif
145         [TEGRA_MUX_SAFE] = "<safe>",
146 };
147
148 static const char *tegra_drive_names[TEGRA_MAX_DRIVE] = {
149         [TEGRA_DRIVE_DIV_8] = "DIV_8",
150         [TEGRA_DRIVE_DIV_4] = "DIV_4",
151         [TEGRA_DRIVE_DIV_2] = "DIV_2",
152         [TEGRA_DRIVE_DIV_1] = "DIV_1",
153 };
154
155 static const char *tegra_slew_names[TEGRA_MAX_SLEW] = {
156         [TEGRA_SLEW_FASTEST] = "FASTEST",
157         [TEGRA_SLEW_FAST] = "FAST",
158         [TEGRA_SLEW_SLOW] = "SLOW",
159         [TEGRA_SLEW_SLOWEST] = "SLOWEST",
160 };
161
162 static DEFINE_SPINLOCK(mux_lock);
163
164 static const char *pingroup_name(enum tegra_pingroup pg)
165 {
166         if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
167                 return "<UNKNOWN>";
168
169         return pingroups[pg].name;
170 }
171
172 static const char *func_name(enum tegra_mux_func func)
173 {
174         if (func == TEGRA_MUX_RSVD1)
175                 return "RSVD1";
176
177         if (func == TEGRA_MUX_RSVD2)
178                 return "RSVD2";
179
180         if (func == TEGRA_MUX_RSVD3)
181                 return "RSVD3";
182
183         if (func == TEGRA_MUX_RSVD4)
184                 return "RSVD4";
185
186         if (func == TEGRA_MUX_NONE)
187                 return "NONE";
188
189         if (func == TEGRA_MUX_INVALID)
190                 return "INVALID";
191
192         if (func < 0 || func >=  TEGRA_MAX_MUX)
193                 return "<UNKNOWN>";
194
195         return tegra_mux_names[func];
196 }
197
198
199 static const char *tri_name(unsigned long val)
200 {
201         return val ? "TRISTATE" : "NORMAL";
202 }
203
204 static const char *pupd_name(unsigned long val)
205 {
206         switch (val) {
207         case 0:
208                 return "NORMAL";
209
210         case 1:
211                 return "PULL_DOWN";
212
213         case 2:
214                 return "PULL_UP";
215
216         default:
217                 return "RSVD";
218         }
219 }
220
221 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
222 static const char *lock_name(unsigned long val)
223 {
224         switch(val) {
225         case TEGRA_PIN_LOCK_DEFAULT:
226                 return "LOCK_DEFUALT";
227
228         case TEGRA_PIN_LOCK_DISABLE:
229                 return "LOCK_DISABLE";
230
231         case TEGRA_PIN_LOCK_ENABLE:
232                 return "LOCK_ENABLE";
233         default:
234                 return "LOCK_DEFAULT";
235         }
236 }
237
238 static const char *od_name(unsigned long val)
239 {
240         switch(val) {
241         case TEGRA_PIN_OD_DEFAULT:
242                 return "OD_DEFAULT";
243
244         case TEGRA_PIN_OD_DISABLE:
245                 return "OD_DISABLE";
246
247         case TEGRA_PIN_OD_ENABLE:
248                 return "OD_ENABLE";
249         default:
250                 return "OD_DEFAULT";
251         }
252 }
253
254 static const char *ioreset_name(unsigned long val)
255 {
256         switch(val) {
257         case TEGRA_PIN_IO_RESET_DEFAULT:
258                 return "IO_RESET_DEFAULT";
259
260         case TEGRA_PIN_IO_RESET_DISABLE:
261                 return "IO_RESET_DISABLE";
262
263         case TEGRA_PIN_IO_RESET_ENABLE:
264                 return "IO_RESET_ENABLE";
265         default:
266                 return "IO_RESET_DEFAULT";
267         }
268 }
269 #endif
270
271 #if defined(TEGRA_PINMUX_HAS_IO_DIRECTION)
272 static const char *io_name(unsigned long val)
273 {
274         switch (val) {
275         case 0:
276                 return "OUTPUT";
277
278         case 1:
279                 return "INPUT";
280
281         default:
282                 return "RSVD";
283         }
284 }
285 #endif
286
287 static inline unsigned long pg_readl(unsigned long offset)
288 {
289         return readl(IO_TO_VIRT(TEGRA_APB_MISC_BASE) + offset);
290 }
291
292 static inline void pg_writel(unsigned long value, unsigned long offset)
293 {
294         writel(value, IO_TO_VIRT(TEGRA_APB_MISC_BASE) + offset);
295 }
296
297 static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config)
298 {
299         int mux = -1;
300         int i;
301         int find = 0;
302         unsigned long reg;
303         unsigned long flags;
304         enum tegra_pingroup pg = config->pingroup;
305         enum tegra_mux_func func = config->func;
306
307         if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
308                 return -ERANGE;
309
310         if (pingroups[pg].mux_reg <= 0)
311                 return -EINVAL;
312
313         if (func == TEGRA_MUX_INVALID) {
314                 pr_err("The pingroup %s is not recommended for option %s\n",
315                                 pingroup_name(pg), func_name(func));
316                 WARN_ON(1);
317                 return -EINVAL;
318         }
319
320         if (func < 0)
321                 return -ERANGE;
322
323         if (func == TEGRA_MUX_SAFE)
324                 func = pingroups[pg].func_safe;
325
326         if (func & TEGRA_MUX_RSVD) {
327                 for (i = 0; i < 4; i++) {
328                         if (pingroups[pg].funcs[i] & TEGRA_MUX_RSVD)
329                                 mux = i;
330
331                         if (pingroups[pg].funcs[i] == func) {
332                                 mux = i;
333                                 find = 1;
334                                 break;
335                         }
336                 }
337         } else {
338                 for (i = 0; i < 4; i++) {
339                         if (pingroups[pg].funcs[i] == func) {
340                                 mux = i;
341                                 find = 1;
342                                 break;
343                         }
344                 }
345         }
346
347         if (mux < 0) {
348                 pr_err("The pingroup %s is not supported option %s\n",
349                         pingroup_name(pg), func_name(func));
350                 WARN_ON(1);
351                 return -EINVAL;
352         }
353
354         if (!find)
355                 pr_warn("The pingroup %s was configured to %s instead of %s\n",
356                         pingroup_name(pg), func_name(pingroups[pg].funcs[mux]),
357                         func_name(func));
358
359         spin_lock_irqsave(&mux_lock, flags);
360
361         reg = pg_readl(pingroups[pg].mux_reg);
362         reg &= ~(0x3 << pingroups[pg].mux_bit);
363         reg |= mux << pingroups[pg].mux_bit;
364 #if defined(TEGRA_PINMUX_HAS_IO_DIRECTION)
365         reg &= ~(0x1 << 5);
366         reg |= ((config->io & 0x1) << 5);
367 #endif
368         pg_writel(reg, pingroups[pg].mux_reg);
369
370         spin_unlock_irqrestore(&mux_lock, flags);
371
372         return 0;
373 }
374
375 int tegra_pinmux_get_func(enum tegra_pingroup pg)
376 {
377         int mux = -1;
378         unsigned long reg;
379         unsigned long flags;
380
381         if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
382                 return -ERANGE;
383
384         if (pingroups[pg].mux_reg <= 0)
385                 return -EINVAL;
386
387         spin_lock_irqsave(&mux_lock, flags);
388
389         reg = pg_readl(pingroups[pg].mux_reg);
390         mux = (reg >> pingroups[pg].mux_bit) & 0x3;
391
392         spin_unlock_irqrestore(&mux_lock, flags);
393
394         return mux;
395 }
396
397 int tegra_pinmux_set_tristate(enum tegra_pingroup pg,
398         enum tegra_tristate tristate)
399 {
400         unsigned long reg;
401         unsigned long flags;
402
403         if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
404                 return -ERANGE;
405
406         if (pingroups[pg].tri_reg <= 0)
407                 return -EINVAL;
408
409         spin_lock_irqsave(&mux_lock, flags);
410
411         reg = pg_readl(pingroups[pg].tri_reg);
412         reg &= ~(0x1 << pingroups[pg].tri_bit);
413         if (tristate)
414                 reg |= 1 << pingroups[pg].tri_bit;
415         pg_writel(reg, pingroups[pg].tri_reg);
416
417         spin_unlock_irqrestore(&mux_lock, flags);
418
419         return 0;
420 }
421
422 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
423 static int tegra_pinmux_set_lock(enum tegra_pingroup pg,
424         enum tegra_pin_lock lock)
425 {
426         unsigned long reg;
427         unsigned long flags;
428
429         if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
430                 return -ERANGE;
431
432         if (pingroups[pg].mux_reg <= 0)
433                 return -EINVAL;
434
435         if ((lock == TEGRA_PIN_LOCK_DEFAULT) || (pingroups[pg].lock_bit < 0))
436                 return 0;
437
438         spin_lock_irqsave(&mux_lock, flags);
439
440         reg = pg_readl(pingroups[pg].mux_reg);
441         reg &= ~(0x1 << pingroups[pg].lock_bit);
442         if (lock == TEGRA_PIN_LOCK_ENABLE)
443                 reg |= (0x1 << pingroups[pg].lock_bit);
444
445         pg_writel(reg, pingroups[pg].mux_reg);
446
447         spin_unlock_irqrestore(&mux_lock, flags);
448         return 0;
449 }
450
451 static int tegra_pinmux_set_od(enum tegra_pingroup pg,
452         enum tegra_pin_od od)
453 {
454         unsigned long reg;
455         unsigned long flags;
456
457         if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
458                 return -ERANGE;
459
460         if (pingroups[pg].mux_reg <= 0)
461                 return -EINVAL;
462
463         if ((od == TEGRA_PIN_OD_DEFAULT) || (pingroups[pg].od_bit < 0))
464                 return 0;
465
466         spin_lock_irqsave(&mux_lock, flags);
467
468         reg = pg_readl(pingroups[pg].mux_reg);
469         reg &= ~(0x1 << pingroups[pg].od_bit);
470         if (od == TEGRA_PIN_OD_ENABLE)
471                 reg |= 1 << pingroups[pg].od_bit;
472
473         pg_writel(reg, pingroups[pg].mux_reg);
474
475         spin_unlock_irqrestore(&mux_lock, flags);
476
477         return 0;
478 }
479
480 static int tegra_pinmux_set_ioreset(enum tegra_pingroup pg,
481         enum tegra_pin_ioreset ioreset)
482 {
483         unsigned long reg;
484         unsigned long flags;
485
486         if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
487                 return -ERANGE;
488
489         if (pingroups[pg].mux_reg <= 0)
490                 return -EINVAL;
491
492         if ((ioreset == TEGRA_PIN_IO_RESET_DEFAULT) || (pingroups[pg].ioreset_bit < 0))
493                 return 0;
494
495         spin_lock_irqsave(&mux_lock, flags);
496
497         reg = pg_readl(pingroups[pg].mux_reg);
498         reg &= ~(0x1 << pingroups[pg].ioreset_bit);
499         if (ioreset == TEGRA_PIN_IO_RESET_ENABLE)
500                 reg |= 1 << pingroups[pg].ioreset_bit;
501
502         pg_writel(reg, pingroups[pg].mux_reg);
503
504         spin_unlock_irqrestore(&mux_lock, flags);
505
506         return 0;
507 }
508 #endif
509
510 int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg,
511         enum tegra_pullupdown pupd)
512 {
513         unsigned long reg;
514         unsigned long flags;
515
516         if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
517                 return -ERANGE;
518
519         if (pingroups[pg].pupd_reg <= 0)
520                 return -EINVAL;
521
522         if (pupd != TEGRA_PUPD_NORMAL &&
523             pupd != TEGRA_PUPD_PULL_DOWN &&
524             pupd != TEGRA_PUPD_PULL_UP)
525                 return -EINVAL;
526
527
528         spin_lock_irqsave(&mux_lock, flags);
529
530         reg = pg_readl(pingroups[pg].pupd_reg);
531         reg &= ~(0x3 << pingroups[pg].pupd_bit);
532         reg |= pupd << pingroups[pg].pupd_bit;
533         pg_writel(reg, pingroups[pg].pupd_reg);
534
535         spin_unlock_irqrestore(&mux_lock, flags);
536
537         return 0;
538 }
539
540 static void tegra_pinmux_config_pingroup(const struct tegra_pingroup_config *config)
541 {
542         enum tegra_pingroup pingroup = config->pingroup;
543         enum tegra_mux_func func     = config->func;
544         enum tegra_pullupdown pupd   = config->pupd;
545         enum tegra_tristate tristate = config->tristate;
546 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
547         enum tegra_pin_lock lock     = config->lock;
548         enum tegra_pin_od od         = config->od;
549         enum tegra_pin_ioreset ioreset = config->ioreset;
550 #endif
551         int err;
552
553         if (pingroups[pingroup].mux_reg > 0) {
554                 err = tegra_pinmux_set_func(config);
555                 if (err < 0)
556                         pr_err("pinmux: can't set pingroup %s func to %s: %d\n",
557                                pingroup_name(pingroup), func_name(func), err);
558         }
559
560         if (pingroups[pingroup].pupd_reg > 0) {
561                 err = tegra_pinmux_set_pullupdown(pingroup, pupd);
562                 if (err < 0)
563                         pr_err("pinmux: can't set pingroup %s pullupdown to %s: %d\n",
564                                pingroup_name(pingroup), pupd_name(pupd), err);
565         }
566
567         if (pingroups[pingroup].tri_reg > 0) {
568                 err = tegra_pinmux_set_tristate(pingroup, tristate);
569                 if (err < 0)
570                         pr_err("pinmux: can't set pingroup %s tristate to %s: %d\n",
571                                pingroup_name(pingroup), tri_name(func), err);
572         }
573
574 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
575         if (pingroups[pingroup].mux_reg > 0) {
576                 err = tegra_pinmux_set_lock(pingroup, lock);
577                 if (err < 0)
578                         pr_err("pinmux: can't set pingroup %s lock to %s: %d\n",
579                                pingroup_name(pingroup), lock_name(func), err);
580         }
581
582         if (pingroups[pingroup].mux_reg > 0) {
583                 err = tegra_pinmux_set_od(pingroup, od);
584                 if (err < 0)
585                         pr_err("pinmux: can't set pingroup %s od to %s: %d\n",
586                                pingroup_name(pingroup), od_name(func), err);
587         }
588
589         if (pingroups[pingroup].mux_reg > 0) {
590                 err = tegra_pinmux_set_ioreset(pingroup, ioreset);
591                 if (err < 0)
592                         pr_err("pinmux: can't set pingroup %s ioreset to %s: %d\n",
593                                pingroup_name(pingroup), ioreset_name(func), err);
594         }
595 #endif
596 }
597
598 void tegra_pinmux_config_table(const struct tegra_pingroup_config *config, int len)
599 {
600         int i;
601
602         for (i = 0; i < len; i++)
603                 tegra_pinmux_config_pingroup(&config[i]);
604 }
605
606 static const char *drive_pinmux_name(enum tegra_drive_pingroup pg)
607 {
608         if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
609                 return "<UNKNOWN>";
610
611         return drive_pingroups[pg].name;
612 }
613
614 static const char *enable_name(unsigned long val)
615 {
616         return val ? "ENABLE" : "DISABLE";
617 }
618
619 static const char *drive_name(unsigned long val)
620 {
621         if (val >= TEGRA_MAX_DRIVE)
622                 return "<UNKNOWN>";
623
624         return tegra_drive_names[val];
625 }
626
627 static const char *slew_name(unsigned long val)
628 {
629         if (val >= TEGRA_MAX_SLEW)
630                 return "<UNKNOWN>";
631
632         return tegra_slew_names[val];
633 }
634
635 static int tegra_drive_pinmux_set_hsm(enum tegra_drive_pingroup pg,
636         enum tegra_hsm hsm)
637 {
638         unsigned long flags;
639         u32 reg;
640         if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
641                 return -ERANGE;
642
643         if (hsm != TEGRA_HSM_ENABLE && hsm != TEGRA_HSM_DISABLE)
644                 return -EINVAL;
645
646         spin_lock_irqsave(&mux_lock, flags);
647
648         reg = pg_readl(drive_pingroups[pg].reg);
649         if (hsm == TEGRA_HSM_ENABLE)
650                 reg |= (1 << 2);
651         else
652                 reg &= ~(1 << 2);
653         pg_writel(reg, drive_pingroups[pg].reg);
654
655         spin_unlock_irqrestore(&mux_lock, flags);
656
657         return 0;
658 }
659
660 static int tegra_drive_pinmux_set_schmitt(enum tegra_drive_pingroup pg,
661         enum tegra_schmitt schmitt)
662 {
663         unsigned long flags;
664         u32 reg;
665         if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
666                 return -ERANGE;
667
668         if (schmitt != TEGRA_SCHMITT_ENABLE && schmitt != TEGRA_SCHMITT_DISABLE)
669                 return -EINVAL;
670
671         spin_lock_irqsave(&mux_lock, flags);
672
673         reg = pg_readl(drive_pingroups[pg].reg);
674         if (schmitt == TEGRA_SCHMITT_ENABLE)
675                 reg |= (1 << 3);
676         else
677                 reg &= ~(1 << 3);
678         pg_writel(reg, drive_pingroups[pg].reg);
679
680         spin_unlock_irqrestore(&mux_lock, flags);
681
682         return 0;
683 }
684
685 static int tegra_drive_pinmux_set_drive(enum tegra_drive_pingroup pg,
686         enum tegra_drive drive)
687 {
688         unsigned long flags;
689         u32 reg;
690         if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
691                 return -ERANGE;
692
693         if (drive < 0 || drive >= TEGRA_MAX_DRIVE)
694                 return -EINVAL;
695
696         spin_lock_irqsave(&mux_lock, flags);
697
698         reg = pg_readl(drive_pingroups[pg].reg);
699         reg &= ~(0x3 << 4);
700         reg |= drive << 4;
701         pg_writel(reg, drive_pingroups[pg].reg);
702
703         spin_unlock_irqrestore(&mux_lock, flags);
704
705         return 0;
706 }
707
708 static int tegra_drive_pinmux_set_pull_down(enum tegra_drive_pingroup pg,
709         enum tegra_pull_strength pull_down)
710 {
711         unsigned long flags;
712         u32 reg;
713
714         if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
715                 return -ERANGE;
716
717         if (pull_down < 0 || pull_down >= TEGRA_MAX_PULL)
718                 return -EINVAL;
719
720         spin_lock_irqsave(&mux_lock, flags);
721
722         reg = pg_readl(drive_pingroups[pg].reg);
723         reg &= ~(drive_pingroups[pg].drvdown_mask <<
724                 drive_pingroups[pg].drvdown_offset);
725         reg |= pull_down << drive_pingroups[pg].drvdown_offset;
726         pg_writel(reg, drive_pingroups[pg].reg);
727
728         spin_unlock_irqrestore(&mux_lock, flags);
729
730         return 0;
731 }
732
733 static int tegra_drive_pinmux_set_pull_up(enum tegra_drive_pingroup pg,
734         enum tegra_pull_strength pull_up)
735 {
736         unsigned long flags;
737         u32 reg;
738
739         if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
740                 return -ERANGE;
741
742         if (pull_up < 0 || pull_up >= TEGRA_MAX_PULL)
743                 return -EINVAL;
744
745         spin_lock_irqsave(&mux_lock, flags);
746
747         reg = pg_readl(drive_pingroups[pg].reg);
748         reg &= ~(drive_pingroups[pg].drvup_mask <<
749                 drive_pingroups[pg].drvup_offset);
750         reg |= pull_up << drive_pingroups[pg].drvup_offset;
751         pg_writel(reg, drive_pingroups[pg].reg);
752
753         spin_unlock_irqrestore(&mux_lock, flags);
754
755         return 0;
756 }
757
758 static int tegra_drive_pinmux_set_slew_rising(enum tegra_drive_pingroup pg,
759         enum tegra_slew slew_rising)
760 {
761         unsigned long flags;
762         u32 reg;
763         if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
764                 return -ERANGE;
765
766         if (slew_rising < 0 || slew_rising >= TEGRA_MAX_SLEW)
767                 return -EINVAL;
768
769         spin_lock_irqsave(&mux_lock, flags);
770
771         reg = pg_readl(drive_pingroups[pg].reg);
772         reg &= ~(0x3 << 28);
773         reg |= slew_rising << 28;
774         pg_writel(reg, drive_pingroups[pg].reg);
775
776         spin_unlock_irqrestore(&mux_lock, flags);
777
778         return 0;
779 }
780
781 static int tegra_drive_pinmux_set_slew_falling(enum tegra_drive_pingroup pg,
782         enum tegra_slew slew_falling)
783 {
784         unsigned long flags;
785         u32 reg;
786         if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
787                 return -ERANGE;
788
789         if (slew_falling < 0 || slew_falling >= TEGRA_MAX_SLEW)
790                 return -EINVAL;
791
792         spin_lock_irqsave(&mux_lock, flags);
793
794         reg = pg_readl(drive_pingroups[pg].reg);
795         reg &= ~(0x3 << 30);
796         reg |= slew_falling << 30;
797         pg_writel(reg, drive_pingroups[pg].reg);
798
799         spin_unlock_irqrestore(&mux_lock, flags);
800
801         return 0;
802 }
803
804 static void tegra_drive_pinmux_config_pingroup(enum tegra_drive_pingroup pingroup,
805                                           enum tegra_hsm hsm,
806                                           enum tegra_schmitt schmitt,
807                                           enum tegra_drive drive,
808                                           enum tegra_pull_strength pull_down,
809                                           enum tegra_pull_strength pull_up,
810                                           enum tegra_slew slew_rising,
811                                           enum tegra_slew slew_falling)
812 {
813         int err;
814
815         err = tegra_drive_pinmux_set_hsm(pingroup, hsm);
816         if (err < 0)
817                 pr_err("pinmux: can't set pingroup %s hsm to %s: %d\n",
818                         drive_pinmux_name(pingroup),
819                         enable_name(hsm), err);
820
821         err = tegra_drive_pinmux_set_schmitt(pingroup, schmitt);
822         if (err < 0)
823                 pr_err("pinmux: can't set pingroup %s schmitt to %s: %d\n",
824                         drive_pinmux_name(pingroup),
825                         enable_name(schmitt), err);
826
827         err = tegra_drive_pinmux_set_drive(pingroup, drive);
828         if (err < 0)
829                 pr_err("pinmux: can't set pingroup %s drive to %s: %d\n",
830                         drive_pinmux_name(pingroup),
831                         drive_name(drive), err);
832
833         err = tegra_drive_pinmux_set_pull_down(pingroup, pull_down);
834         if (err < 0)
835                 pr_err("pinmux: can't set pingroup %s pull down to %d: %d\n",
836                         drive_pinmux_name(pingroup),
837                         pull_down, err);
838
839         err = tegra_drive_pinmux_set_pull_up(pingroup, pull_up);
840         if (err < 0)
841                 pr_err("pinmux: can't set pingroup %s pull up to %d: %d\n",
842                         drive_pinmux_name(pingroup),
843                         pull_up, err);
844
845         err = tegra_drive_pinmux_set_slew_rising(pingroup, slew_rising);
846         if (err < 0)
847                 pr_err("pinmux: can't set pingroup %s rising slew to %s: %d\n",
848                         drive_pinmux_name(pingroup),
849                         slew_name(slew_rising), err);
850
851         err = tegra_drive_pinmux_set_slew_falling(pingroup, slew_falling);
852         if (err < 0)
853                 pr_err("pinmux: can't set pingroup %s falling slew to %s: %d\n",
854                         drive_pinmux_name(pingroup),
855                         slew_name(slew_falling), err);
856 }
857
858 void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
859         int len)
860 {
861         int i;
862
863         for (i = 0; i < len; i++)
864                 tegra_drive_pinmux_config_pingroup(config[i].pingroup,
865                                                      config[i].hsm,
866                                                      config[i].schmitt,
867                                                      config[i].drive,
868                                                      config[i].pull_down,
869                                                      config[i].pull_up,
870                                                      config[i].slew_rising,
871                                                      config[i].slew_falling);
872 }
873
874 void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config,
875         int len)
876 {
877         int i;
878         struct tegra_pingroup_config c;
879
880         for (i = 0; i < len; i++) {
881                 int err;
882                 c = config[i];
883                 if (c.pingroup < 0 || c.pingroup >= TEGRA_MAX_PINGROUP) {
884                         WARN_ON(1);
885                         continue;
886                 }
887                 c.func = pingroups[c.pingroup].func_safe;
888                 err = tegra_pinmux_set_func(&c);
889                 if (err < 0)
890                         pr_err("%s: tegra_pinmux_set_func returned %d setting "
891                                "%s to %s\n", __func__, err,
892                                pingroup_name(c.pingroup), func_name(c.func));
893         }
894 }
895
896 void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config,
897         int len)
898 {
899         int i;
900
901         for (i = 0; i < len; i++) {
902                 int err;
903                 if (config[i].pingroup < 0 ||
904                     config[i].pingroup >= TEGRA_MAX_PINGROUP) {
905                         WARN_ON(1);
906                         continue;
907                 }
908                 err = tegra_pinmux_set_func(&config[i]);
909                 if (err < 0)
910                         pr_err("%s: tegra_pinmux_set_func returned %d setting "
911                                "%s to %s\n", __func__, err,
912                                pingroup_name(config[i].pingroup),
913                                func_name(config[i].func));
914         }
915 }
916
917 void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config,
918         int len, enum tegra_tristate tristate)
919 {
920         int i;
921         int err;
922         enum tegra_pingroup pingroup;
923
924         for (i = 0; i < len; i++) {
925                 pingroup = config[i].pingroup;
926                 if (pingroups[pingroup].tri_reg > 0) {
927                         err = tegra_pinmux_set_tristate(pingroup, tristate);
928                         if (err < 0)
929                                 pr_err("pinmux: can't set pingroup %s tristate"
930                                         " to %s: %d\n", pingroup_name(pingroup),
931                                         tri_name(tristate), err);
932                 }
933         }
934 }
935
936 void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
937         int len, enum tegra_pullupdown pupd)
938 {
939         int i;
940         int err;
941         enum tegra_pingroup pingroup;
942
943         for (i = 0; i < len; i++) {
944                 pingroup = config[i].pingroup;
945                 if (pingroups[pingroup].pupd_reg > 0) {
946                         err = tegra_pinmux_set_pullupdown(pingroup, pupd);
947                         if (err < 0)
948                                 pr_err("pinmux: can't set pingroup %s pullupdown"
949                                         " to %s: %d\n", pingroup_name(pingroup),
950                                         pupd_name(pupd), err);
951                 }
952         }
953 }
954
955 #ifdef  CONFIG_DEBUG_FS
956
957 #include <linux/debugfs.h>
958 #include <linux/seq_file.h>
959
960 static void dbg_pad_field(struct seq_file *s, int len)
961 {
962         seq_putc(s, ',');
963
964         while (len-- > -1)
965                 seq_putc(s, ' ');
966 }
967
968 static int dbg_pinmux_show(struct seq_file *s, void *unused)
969 {
970         int i;
971         int len;
972
973         for (i = 0; i < TEGRA_MAX_PINGROUP; i++) {
974                 unsigned long tri;
975                 unsigned long mux;
976                 unsigned long pupd;
977
978                 seq_printf(s, "\t{TEGRA_PINGROUP_%s", pingroups[i].name);
979                 len = strlen(pingroups[i].name);
980                 dbg_pad_field(s, 15 - len);
981
982                 if (pingroups[i].mux_reg <= 0) {
983                         seq_printf(s, "TEGRA_MUX_NONE");
984                         len = strlen("NONE");
985                 } else {
986                         mux = (pg_readl(pingroups[i].mux_reg) >>
987                                pingroups[i].mux_bit) & 0x3;
988                         BUG_ON(pingroups[i].funcs[mux] == 0);
989                         if (pingroups[i].funcs[mux] ==  TEGRA_MUX_INVALID) {
990                                 seq_printf(s, "TEGRA_MUX_INVALID");
991                                 len = 7;
992                         } else if (pingroups[i].funcs[mux] & TEGRA_MUX_RSVD) {
993                                 seq_printf(s, "TEGRA_MUX_RSVD%1lu", mux+1);
994                                 len = 5;
995                         } else {
996                                 BUG_ON(!tegra_mux_names[pingroups[i].funcs[mux]]);
997                                 seq_printf(s, "TEGRA_MUX_%s",
998                                            tegra_mux_names[pingroups[i].funcs[mux]]);
999                                 len = strlen(tegra_mux_names[pingroups[i].funcs[mux]]);
1000                         }
1001                 }
1002                 dbg_pad_field(s, 13-len);
1003
1004 #if defined(TEGRA_PINMUX_HAS_IO_DIRECTION)
1005                 {
1006                         unsigned long io;
1007                         io = (pg_readl(pingroups[i].mux_reg) >> 5) & 0x1;
1008                         seq_printf(s, "TEGRA_PIN_%s", io_name(io));
1009                         len = strlen(io_name(io));
1010                         dbg_pad_field(s, 6 - len);
1011                 }
1012 #endif
1013                 if (pingroups[i].pupd_reg <= 0) {
1014                         seq_printf(s, "TEGRA_PUPD_NORMAL");
1015                         len = strlen("NORMAL");
1016                 } else {
1017                         pupd = (pg_readl(pingroups[i].pupd_reg) >>
1018                                 pingroups[i].pupd_bit) & 0x3;
1019                         seq_printf(s, "TEGRA_PUPD_%s", pupd_name(pupd));
1020                         len = strlen(pupd_name(pupd));
1021                 }
1022                 dbg_pad_field(s, 9 - len);
1023
1024                 if (pingroups[i].tri_reg <= 0) {
1025                         seq_printf(s, "TEGRA_TRI_NORMAL");
1026                 } else {
1027                         tri = (pg_readl(pingroups[i].tri_reg) >>
1028                                pingroups[i].tri_bit) & 0x1;
1029
1030                         seq_printf(s, "TEGRA_TRI_%s", tri_name(tri));
1031                 }
1032                 seq_printf(s, "},\n");
1033         }
1034         return 0;
1035 }
1036
1037 static int dbg_pinmux_open(struct inode *inode, struct file *file)
1038 {
1039         return single_open(file, dbg_pinmux_show, &inode->i_private);
1040 }
1041
1042 static const struct file_operations debug_fops = {
1043         .open           = dbg_pinmux_open,
1044         .read           = seq_read,
1045         .llseek         = seq_lseek,
1046         .release        = single_release,
1047 };
1048
1049 static int dbg_drive_pinmux_show(struct seq_file *s, void *unused)
1050 {
1051         int i;
1052         int len;
1053
1054         for (i = 0; i < TEGRA_MAX_DRIVE_PINGROUP; i++) {
1055                 u32 reg;
1056
1057                 seq_printf(s, "\t{TEGRA_DRIVE_PINGROUP_%s",
1058                         drive_pingroups[i].name);
1059                 len = strlen(drive_pingroups[i].name);
1060                 dbg_pad_field(s, 7 - len);
1061
1062
1063                 reg = pg_readl(drive_pingroups[i].reg);
1064                 if (HSM_EN(reg)) {
1065                         seq_printf(s, "TEGRA_HSM_ENABLE");
1066                         len = 16;
1067                 } else {
1068                         seq_printf(s, "TEGRA_HSM_DISABLE");
1069                         len = 17;
1070                 }
1071                 dbg_pad_field(s, 17 - len);
1072
1073                 if (SCHMT_EN(reg)) {
1074                         seq_printf(s, "TEGRA_SCHMITT_ENABLE");
1075                         len = 21;
1076                 } else {
1077                         seq_printf(s, "TEGRA_SCHMITT_DISABLE");
1078                         len = 22;
1079                 }
1080                 dbg_pad_field(s, 22 - len);
1081
1082                 seq_printf(s, "TEGRA_DRIVE_%s", drive_name(LPMD(reg)));
1083                 len = strlen(drive_name(LPMD(reg)));
1084                 dbg_pad_field(s, 5 - len);
1085
1086                 seq_printf(s, "TEGRA_PULL_%d", DRVDN(reg));
1087                 len = DRVDN(reg) < 10 ? 1 : 2;
1088                 dbg_pad_field(s, 2 - len);
1089
1090                 seq_printf(s, "TEGRA_PULL_%d", DRVUP(reg));
1091                 len = DRVUP(reg) < 10 ? 1 : 2;
1092                 dbg_pad_field(s, 2 - len);
1093
1094                 seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWR(reg)));
1095                 len = strlen(slew_name(SLWR(reg)));
1096                 dbg_pad_field(s, 7 - len);
1097
1098                 seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWF(reg)));
1099
1100                 seq_printf(s, "},\n");
1101         }
1102         return 0;
1103 }
1104
1105 static int dbg_drive_pinmux_open(struct inode *inode, struct file *file)
1106 {
1107         return single_open(file, dbg_drive_pinmux_show, &inode->i_private);
1108 }
1109
1110 static const struct file_operations debug_drive_fops = {
1111         .open           = dbg_drive_pinmux_open,
1112         .read           = seq_read,
1113         .llseek         = seq_lseek,
1114         .release        = single_release,
1115 };
1116
1117 static int __init tegra_pinmux_debuginit(void)
1118 {
1119         (void) debugfs_create_file("tegra_pinmux", S_IRUGO,
1120                                         NULL, NULL, &debug_fops);
1121         (void) debugfs_create_file("tegra_pinmux_drive", S_IRUGO,
1122                                         NULL, NULL, &debug_drive_fops);
1123         return 0;
1124 }
1125 late_initcall(tegra_pinmux_debuginit);
1126 #endif