a49c20d6cd9dbe06b8f86a01f5433c3d25609c0c
[linux-2.6.git] / arch / arm / mach-tegra / pinmux.c
1 /*
2  * linux/arch/arm/mach-tegra/pinmux.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/spinlock.h>
22 #include <linux/io.h>
23
24 #include <mach/iomap.h>
25 #include <mach/pinmux.h>
26
27 #define HSM_EN(reg)     (((reg) >> 2) & 0x1)
28 #define SCHMT_EN(reg)   (((reg) >> 3) & 0x1)
29 #define LPMD(reg)       (((reg) >> 4) & 0x3)
30 #define DRVDN(reg)      (((reg) >> 12) & 0x1f)
31 #define DRVUP(reg)      (((reg) >> 20) & 0x1f)
32 #define SLWR(reg)       (((reg) >> 28) & 0x3)
33 #define SLWF(reg)       (((reg) >> 30) & 0x3)
34
35 static const struct tegra_pingroup_desc *const pingroups = tegra_soc_pingroups;
36 static const struct tegra_drive_pingroup_desc *const drive_pingroups = tegra_soc_drive_pingroups;
37
38 static char *tegra_mux_names[TEGRA_MAX_MUX] = {
39         [TEGRA_MUX_AHB_CLK] = "AHB_CLK",
40         [TEGRA_MUX_APB_CLK] = "APB_CLK",
41         [TEGRA_MUX_AUDIO_SYNC] = "AUDIO_SYNC",
42         [TEGRA_MUX_CRT] = "CRT",
43         [TEGRA_MUX_DAP1] = "DAP1",
44         [TEGRA_MUX_DAP2] = "DAP2",
45         [TEGRA_MUX_DAP3] = "DAP3",
46         [TEGRA_MUX_DAP4] = "DAP4",
47         [TEGRA_MUX_DAP5] = "DAP5",
48         [TEGRA_MUX_DISPLAYA] = "DISPLAYA",
49         [TEGRA_MUX_DISPLAYB] = "DISPLAYB",
50         [TEGRA_MUX_EMC_TEST0_DLL] = "EMC_TEST0_DLL",
51         [TEGRA_MUX_EMC_TEST1_DLL] = "EMC_TEST1_DLL",
52         [TEGRA_MUX_GMI] = "GMI",
53         [TEGRA_MUX_GMI_INT] = "GMI_INT",
54         [TEGRA_MUX_HDMI] = "HDMI",
55         [TEGRA_MUX_I2C] = "I2C",
56         [TEGRA_MUX_I2C2] = "I2C2",
57         [TEGRA_MUX_I2C3] = "I2C3",
58         [TEGRA_MUX_IDE] = "IDE",
59         [TEGRA_MUX_IRDA] = "IRDA",
60         [TEGRA_MUX_KBC] = "KBC",
61         [TEGRA_MUX_MIO] = "MIO",
62         [TEGRA_MUX_MIPI_HS] = "MIPI_HS",
63         [TEGRA_MUX_NAND] = "NAND",
64         [TEGRA_MUX_OSC] = "OSC",
65         [TEGRA_MUX_OWR] = "OWR",
66         [TEGRA_MUX_PCIE] = "PCIE",
67         [TEGRA_MUX_PLLA_OUT] = "PLLA_OUT",
68         [TEGRA_MUX_PLLC_OUT1] = "PLLC_OUT1",
69         [TEGRA_MUX_PLLM_OUT1] = "PLLM_OUT1",
70         [TEGRA_MUX_PLLP_OUT2] = "PLLP_OUT2",
71         [TEGRA_MUX_PLLP_OUT3] = "PLLP_OUT3",
72         [TEGRA_MUX_PLLP_OUT4] = "PLLP_OUT4",
73         [TEGRA_MUX_PWM] = "PWM",
74         [TEGRA_MUX_PWR_INTR] = "PWR_INTR",
75         [TEGRA_MUX_PWR_ON] = "PWR_ON",
76         [TEGRA_MUX_RTCK] = "RTCK",
77         [TEGRA_MUX_SDIO1] = "SDIO1",
78         [TEGRA_MUX_SDIO2] = "SDIO2",
79         [TEGRA_MUX_SDIO3] = "SDIO3",
80         [TEGRA_MUX_SDIO4] = "SDIO4",
81         [TEGRA_MUX_SFLASH] = "SFLASH",
82         [TEGRA_MUX_SPDIF] = "SPDIF",
83         [TEGRA_MUX_SPI1] = "SPI1",
84         [TEGRA_MUX_SPI2] = "SPI2",
85         [TEGRA_MUX_SPI2_ALT] = "SPI2_ALT",
86         [TEGRA_MUX_SPI3] = "SPI3",
87         [TEGRA_MUX_SPI4] = "SPI4",
88         [TEGRA_MUX_TRACE] = "TRACE",
89         [TEGRA_MUX_TWC] = "TWC",
90         [TEGRA_MUX_UARTA] = "UARTA",
91         [TEGRA_MUX_UARTB] = "UARTB",
92         [TEGRA_MUX_UARTC] = "UARTC",
93         [TEGRA_MUX_UARTD] = "UARTD",
94         [TEGRA_MUX_UARTE] = "UARTE",
95         [TEGRA_MUX_ULPI] = "ULPI",
96         [TEGRA_MUX_VI] = "VI",
97         [TEGRA_MUX_VI_SENSOR_CLK] = "VI_SENSOR_CLK",
98         [TEGRA_MUX_XIO] = "XIO",
99         [TEGRA_MUX_SAFE] = "<safe>",
100 };
101
102 static const char *tegra_drive_names[TEGRA_MAX_DRIVE] = {
103         [TEGRA_DRIVE_DIV_8] = "DIV_8",
104         [TEGRA_DRIVE_DIV_4] = "DIV_4",
105         [TEGRA_DRIVE_DIV_2] = "DIV_2",
106         [TEGRA_DRIVE_DIV_1] = "DIV_1",
107 };
108
109 static const char *tegra_slew_names[TEGRA_MAX_SLEW] = {
110         [TEGRA_SLEW_FASTEST] = "FASTEST",
111         [TEGRA_SLEW_FAST] = "FAST",
112         [TEGRA_SLEW_SLOW] = "SLOW",
113         [TEGRA_SLEW_SLOWEST] = "SLOWEST",
114 };
115
116 static DEFINE_SPINLOCK(mux_lock);
117
118 static const char *pingroup_name(enum tegra_pingroup pg)
119 {
120         if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
121                 return "<UNKNOWN>";
122
123         return pingroups[pg].name;
124 }
125
126 static const char *func_name(enum tegra_mux_func func)
127 {
128         if (func == TEGRA_MUX_RSVD1)
129                 return "RSVD1";
130
131         if (func == TEGRA_MUX_RSVD2)
132                 return "RSVD2";
133
134         if (func == TEGRA_MUX_RSVD3)
135                 return "RSVD3";
136
137         if (func == TEGRA_MUX_RSVD4)
138                 return "RSVD4";
139
140         if (func == TEGRA_MUX_NONE)
141                 return "NONE";
142
143         if (func < 0 || func >=  TEGRA_MAX_MUX)
144                 return "<UNKNOWN>";
145
146         return tegra_mux_names[func];
147 }
148
149
150 static const char *tri_name(unsigned long val)
151 {
152         return val ? "TRISTATE" : "NORMAL";
153 }
154
155 static const char *pupd_name(unsigned long val)
156 {
157         switch (val) {
158         case 0:
159                 return "NORMAL";
160
161         case 1:
162                 return "PULL_DOWN";
163
164         case 2:
165                 return "PULL_UP";
166
167         default:
168                 return "RSVD";
169         }
170 }
171
172
173 static inline unsigned long pg_readl(unsigned long offset)
174 {
175         return readl(IO_TO_VIRT(TEGRA_APB_MISC_BASE) + offset);
176 }
177
178 static inline void pg_writel(unsigned long value, unsigned long offset)
179 {
180         writel(value, IO_TO_VIRT(TEGRA_APB_MISC_BASE) + offset);
181 }
182
183 static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config)
184 {
185         int mux = -1;
186         int i;
187         unsigned long reg;
188         unsigned long flags;
189         enum tegra_pingroup pg = config->pingroup;
190         enum tegra_mux_func func = config->func;
191
192         if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
193                 return -ERANGE;
194
195         if (pingroups[pg].mux_reg < 0)
196                 return -EINVAL;
197
198         if (func < 0)
199                 return -ERANGE;
200
201         if (func == TEGRA_MUX_SAFE)
202                 func = pingroups[pg].func_safe;
203
204         if (func & TEGRA_MUX_RSVD) {
205                 mux = func & 0x3;
206         } else {
207                 for (i = 0; i < 4; i++) {
208                         if (pingroups[pg].funcs[i] == func) {
209                                 mux = i;
210                                 break;
211                         }
212                 }
213         }
214
215         if (mux < 0)
216                 return -EINVAL;
217
218         spin_lock_irqsave(&mux_lock, flags);
219
220         reg = pg_readl(pingroups[pg].mux_reg);
221         reg &= ~(0x3 << pingroups[pg].mux_bit);
222         reg |= mux << pingroups[pg].mux_bit;
223         pg_writel(reg, pingroups[pg].mux_reg);
224
225         spin_unlock_irqrestore(&mux_lock, flags);
226
227         return 0;
228 }
229
230 int tegra_pinmux_get_func(enum tegra_pingroup pg)
231 {
232         int mux = -1;
233         unsigned long reg;
234         unsigned long flags;
235
236         if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
237                 return -ERANGE;
238
239         if (pingroups[pg].mux_reg < 0)
240                 return -EINVAL;
241
242         spin_lock_irqsave(&mux_lock, flags);
243
244         reg = pg_readl(pingroups[pg].mux_reg);
245         mux = (reg >> pingroups[pg].mux_bit) & 0x3;
246
247         spin_unlock_irqrestore(&mux_lock, flags);
248
249         return mux;
250 }
251
252 int tegra_pinmux_set_tristate(enum tegra_pingroup pg,
253         enum tegra_tristate tristate)
254 {
255         unsigned long reg;
256         unsigned long flags;
257
258         if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
259                 return -ERANGE;
260
261         if (pingroups[pg].tri_reg < 0)
262                 return -EINVAL;
263
264         spin_lock_irqsave(&mux_lock, flags);
265
266         reg = pg_readl(pingroups[pg].tri_reg);
267         reg &= ~(0x1 << pingroups[pg].tri_bit);
268         if (tristate)
269                 reg |= 1 << pingroups[pg].tri_bit;
270         pg_writel(reg, pingroups[pg].tri_reg);
271
272         spin_unlock_irqrestore(&mux_lock, flags);
273
274         return 0;
275 }
276
277 int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg,
278         enum tegra_pullupdown pupd)
279 {
280         unsigned long reg;
281         unsigned long flags;
282
283         if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
284                 return -ERANGE;
285
286         if (pingroups[pg].pupd_reg < 0)
287                 return -EINVAL;
288
289         if (pupd != TEGRA_PUPD_NORMAL &&
290             pupd != TEGRA_PUPD_PULL_DOWN &&
291             pupd != TEGRA_PUPD_PULL_UP)
292                 return -EINVAL;
293
294
295         spin_lock_irqsave(&mux_lock, flags);
296
297         reg = pg_readl(pingroups[pg].pupd_reg);
298         reg &= ~(0x3 << pingroups[pg].pupd_bit);
299         reg |= pupd << pingroups[pg].pupd_bit;
300         pg_writel(reg, pingroups[pg].pupd_reg);
301
302         spin_unlock_irqrestore(&mux_lock, flags);
303
304         return 0;
305 }
306
307 static void tegra_pinmux_config_pingroup(const struct tegra_pingroup_config *config)
308 {
309         enum tegra_pingroup pingroup = config->pingroup;
310         enum tegra_mux_func func     = config->func;
311         enum tegra_pullupdown pupd   = config->pupd;
312         enum tegra_tristate tristate = config->tristate;
313         int err;
314
315         if (pingroups[pingroup].mux_reg >= 0) {
316                 err = tegra_pinmux_set_func(config);
317                 if (err < 0)
318                         pr_err("pinmux: can't set pingroup %s func to %s: %d\n",
319                                pingroup_name(pingroup), func_name(func), err);
320         }
321
322         if (pingroups[pingroup].pupd_reg >= 0) {
323                 err = tegra_pinmux_set_pullupdown(pingroup, pupd);
324                 if (err < 0)
325                         pr_err("pinmux: can't set pingroup %s pullupdown to %s: %d\n",
326                                pingroup_name(pingroup), pupd_name(pupd), err);
327         }
328
329         if (pingroups[pingroup].tri_reg >= 0) {
330                 err = tegra_pinmux_set_tristate(pingroup, tristate);
331                 if (err < 0)
332                         pr_err("pinmux: can't set pingroup %s tristate to %s: %d\n",
333                                pingroup_name(pingroup), tri_name(func), err);
334         }
335 }
336
337 void tegra_pinmux_config_table(const struct tegra_pingroup_config *config, int len)
338 {
339         int i;
340
341         for (i = 0; i < len; i++)
342                 tegra_pinmux_config_pingroup(&config[i]);
343 }
344
345 static const char *drive_pinmux_name(enum tegra_drive_pingroup pg)
346 {
347         if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
348                 return "<UNKNOWN>";
349
350         return drive_pingroups[pg].name;
351 }
352
353 static const char *enable_name(unsigned long val)
354 {
355         return val ? "ENABLE" : "DISABLE";
356 }
357
358 static const char *drive_name(unsigned long val)
359 {
360         if (val >= TEGRA_MAX_DRIVE)
361                 return "<UNKNOWN>";
362
363         return tegra_drive_names[val];
364 }
365
366 static const char *slew_name(unsigned long val)
367 {
368         if (val >= TEGRA_MAX_SLEW)
369                 return "<UNKNOWN>";
370
371         return tegra_slew_names[val];
372 }
373
374 static int tegra_drive_pinmux_set_hsm(enum tegra_drive_pingroup pg,
375         enum tegra_hsm hsm)
376 {
377         unsigned long flags;
378         u32 reg;
379         if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
380                 return -ERANGE;
381
382         if (hsm != TEGRA_HSM_ENABLE && hsm != TEGRA_HSM_DISABLE)
383                 return -EINVAL;
384
385         spin_lock_irqsave(&mux_lock, flags);
386
387         reg = pg_readl(drive_pingroups[pg].reg);
388         if (hsm == TEGRA_HSM_ENABLE)
389                 reg |= (1 << 2);
390         else
391                 reg &= ~(1 << 2);
392         pg_writel(reg, drive_pingroups[pg].reg);
393
394         spin_unlock_irqrestore(&mux_lock, flags);
395
396         return 0;
397 }
398
399 static int tegra_drive_pinmux_set_schmitt(enum tegra_drive_pingroup pg,
400         enum tegra_schmitt schmitt)
401 {
402         unsigned long flags;
403         u32 reg;
404         if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
405                 return -ERANGE;
406
407         if (schmitt != TEGRA_SCHMITT_ENABLE && schmitt != TEGRA_SCHMITT_DISABLE)
408                 return -EINVAL;
409
410         spin_lock_irqsave(&mux_lock, flags);
411
412         reg = pg_readl(drive_pingroups[pg].reg);
413         if (schmitt == TEGRA_SCHMITT_ENABLE)
414                 reg |= (1 << 3);
415         else
416                 reg &= ~(1 << 3);
417         pg_writel(reg, drive_pingroups[pg].reg);
418
419         spin_unlock_irqrestore(&mux_lock, flags);
420
421         return 0;
422 }
423
424 static int tegra_drive_pinmux_set_drive(enum tegra_drive_pingroup pg,
425         enum tegra_drive drive)
426 {
427         unsigned long flags;
428         u32 reg;
429         if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
430                 return -ERANGE;
431
432         if (drive < 0 || drive >= TEGRA_MAX_DRIVE)
433                 return -EINVAL;
434
435         spin_lock_irqsave(&mux_lock, flags);
436
437         reg = pg_readl(drive_pingroups[pg].reg);
438         reg &= ~(0x3 << 4);
439         reg |= drive << 4;
440         pg_writel(reg, drive_pingroups[pg].reg);
441
442         spin_unlock_irqrestore(&mux_lock, flags);
443
444         return 0;
445 }
446
447 static int tegra_drive_pinmux_set_pull_down(enum tegra_drive_pingroup pg,
448         enum tegra_pull_strength pull_down)
449 {
450         unsigned long flags;
451         u32 reg;
452         if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
453                 return -ERANGE;
454
455         if (pull_down < 0 || pull_down >= TEGRA_MAX_PULL)
456                 return -EINVAL;
457
458         spin_lock_irqsave(&mux_lock, flags);
459
460         reg = pg_readl(drive_pingroups[pg].reg);
461         reg &= ~(0x1f << 12);
462         reg |= pull_down << 12;
463         pg_writel(reg, drive_pingroups[pg].reg);
464
465         spin_unlock_irqrestore(&mux_lock, flags);
466
467         return 0;
468 }
469
470 static int tegra_drive_pinmux_set_pull_up(enum tegra_drive_pingroup pg,
471         enum tegra_pull_strength pull_up)
472 {
473         unsigned long flags;
474         u32 reg;
475         if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
476                 return -ERANGE;
477
478         if (pull_up < 0 || pull_up >= TEGRA_MAX_PULL)
479                 return -EINVAL;
480
481         spin_lock_irqsave(&mux_lock, flags);
482
483         reg = pg_readl(drive_pingroups[pg].reg);
484         reg &= ~(0x1f << 20);
485         reg |= pull_up << 20;
486         pg_writel(reg, drive_pingroups[pg].reg);
487
488         spin_unlock_irqrestore(&mux_lock, flags);
489
490         return 0;
491 }
492
493 static int tegra_drive_pinmux_set_slew_rising(enum tegra_drive_pingroup pg,
494         enum tegra_slew slew_rising)
495 {
496         unsigned long flags;
497         u32 reg;
498         if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
499                 return -ERANGE;
500
501         if (slew_rising < 0 || slew_rising >= TEGRA_MAX_SLEW)
502                 return -EINVAL;
503
504         spin_lock_irqsave(&mux_lock, flags);
505
506         reg = pg_readl(drive_pingroups[pg].reg);
507         reg &= ~(0x3 << 28);
508         reg |= slew_rising << 28;
509         pg_writel(reg, drive_pingroups[pg].reg);
510
511         spin_unlock_irqrestore(&mux_lock, flags);
512
513         return 0;
514 }
515
516 static int tegra_drive_pinmux_set_slew_falling(enum tegra_drive_pingroup pg,
517         enum tegra_slew slew_falling)
518 {
519         unsigned long flags;
520         u32 reg;
521         if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
522                 return -ERANGE;
523
524         if (slew_falling < 0 || slew_falling >= TEGRA_MAX_SLEW)
525                 return -EINVAL;
526
527         spin_lock_irqsave(&mux_lock, flags);
528
529         reg = pg_readl(drive_pingroups[pg].reg);
530         reg &= ~(0x3 << 30);
531         reg |= slew_falling << 30;
532         pg_writel(reg, drive_pingroups[pg].reg);
533
534         spin_unlock_irqrestore(&mux_lock, flags);
535
536         return 0;
537 }
538
539 static void tegra_drive_pinmux_config_pingroup(enum tegra_drive_pingroup pingroup,
540                                           enum tegra_hsm hsm,
541                                           enum tegra_schmitt schmitt,
542                                           enum tegra_drive drive,
543                                           enum tegra_pull_strength pull_down,
544                                           enum tegra_pull_strength pull_up,
545                                           enum tegra_slew slew_rising,
546                                           enum tegra_slew slew_falling)
547 {
548         int err;
549
550         err = tegra_drive_pinmux_set_hsm(pingroup, hsm);
551         if (err < 0)
552                 pr_err("pinmux: can't set pingroup %s hsm to %s: %d\n",
553                         drive_pinmux_name(pingroup),
554                         enable_name(hsm), err);
555
556         err = tegra_drive_pinmux_set_schmitt(pingroup, schmitt);
557         if (err < 0)
558                 pr_err("pinmux: can't set pingroup %s schmitt to %s: %d\n",
559                         drive_pinmux_name(pingroup),
560                         enable_name(schmitt), err);
561
562         err = tegra_drive_pinmux_set_drive(pingroup, drive);
563         if (err < 0)
564                 pr_err("pinmux: can't set pingroup %s drive to %s: %d\n",
565                         drive_pinmux_name(pingroup),
566                         drive_name(drive), err);
567
568         err = tegra_drive_pinmux_set_pull_down(pingroup, pull_down);
569         if (err < 0)
570                 pr_err("pinmux: can't set pingroup %s pull down to %d: %d\n",
571                         drive_pinmux_name(pingroup),
572                         pull_down, err);
573
574         err = tegra_drive_pinmux_set_pull_up(pingroup, pull_up);
575         if (err < 0)
576                 pr_err("pinmux: can't set pingroup %s pull up to %d: %d\n",
577                         drive_pinmux_name(pingroup),
578                         pull_up, err);
579
580         err = tegra_drive_pinmux_set_slew_rising(pingroup, slew_rising);
581         if (err < 0)
582                 pr_err("pinmux: can't set pingroup %s rising slew to %s: %d\n",
583                         drive_pinmux_name(pingroup),
584                         slew_name(slew_rising), err);
585
586         err = tegra_drive_pinmux_set_slew_falling(pingroup, slew_falling);
587         if (err < 0)
588                 pr_err("pinmux: can't set pingroup %s falling slew to %s: %d\n",
589                         drive_pinmux_name(pingroup),
590                         slew_name(slew_falling), err);
591 }
592
593 void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
594         int len)
595 {
596         int i;
597
598         for (i = 0; i < len; i++)
599                 tegra_drive_pinmux_config_pingroup(config[i].pingroup,
600                                                      config[i].hsm,
601                                                      config[i].schmitt,
602                                                      config[i].drive,
603                                                      config[i].pull_down,
604                                                      config[i].pull_up,
605                                                      config[i].slew_rising,
606                                                      config[i].slew_falling);
607 }
608
609 void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config,
610         int len)
611 {
612         int i;
613         struct tegra_pingroup_config c;
614
615         for (i = 0; i < len; i++) {
616                 int err;
617                 c = config[i];
618                 if (c.pingroup < 0 || c.pingroup >= TEGRA_MAX_PINGROUP) {
619                         WARN_ON(1);
620                         continue;
621                 }
622                 c.func = pingroups[c.pingroup].func_safe;
623                 err = tegra_pinmux_set_func(&c);
624                 if (err < 0)
625                         pr_err("%s: tegra_pinmux_set_func returned %d setting "
626                                "%s to %s\n", __func__, err,
627                                pingroup_name(c.pingroup), func_name(c.func));
628         }
629 }
630
631 void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config,
632         int len)
633 {
634         int i;
635
636         for (i = 0; i < len; i++) {
637                 int err;
638                 if (config[i].pingroup < 0 ||
639                     config[i].pingroup >= TEGRA_MAX_PINGROUP) {
640                         WARN_ON(1);
641                         continue;
642                 }
643                 err = tegra_pinmux_set_func(&config[i]);
644                 if (err < 0)
645                         pr_err("%s: tegra_pinmux_set_func returned %d setting "
646                                "%s to %s\n", __func__, err,
647                                pingroup_name(config[i].pingroup),
648                                func_name(config[i].func));
649         }
650 }
651
652 void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config,
653         int len, enum tegra_tristate tristate)
654 {
655         int i;
656         int err;
657         enum tegra_pingroup pingroup;
658
659         for (i = 0; i < len; i++) {
660                 pingroup = config[i].pingroup;
661                 if (pingroups[pingroup].tri_reg >= 0) {
662                         err = tegra_pinmux_set_tristate(pingroup, tristate);
663                         if (err < 0)
664                                 pr_err("pinmux: can't set pingroup %s tristate"
665                                         " to %s: %d\n", pingroup_name(pingroup),
666                                         tri_name(tristate), err);
667                 }
668         }
669 }
670
671 void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
672         int len, enum tegra_pullupdown pupd)
673 {
674         int i;
675         int err;
676         enum tegra_pingroup pingroup;
677
678         for (i = 0; i < len; i++) {
679                 pingroup = config[i].pingroup;
680                 if (pingroups[pingroup].pupd_reg >= 0) {
681                         err = tegra_pinmux_set_pullupdown(pingroup, pupd);
682                         if (err < 0)
683                                 pr_err("pinmux: can't set pingroup %s pullupdown"
684                                         " to %s: %d\n", pingroup_name(pingroup),
685                                         pupd_name(pupd), err);
686                 }
687         }
688 }
689
690 void tegra_init_pinmux(void)
691 {
692         tegra2_init_pinmux();
693 }
694
695 #ifdef  CONFIG_DEBUG_FS
696
697 #include <linux/debugfs.h>
698 #include <linux/seq_file.h>
699
700 static void dbg_pad_field(struct seq_file *s, int len)
701 {
702         seq_putc(s, ',');
703
704         while (len-- > -1)
705                 seq_putc(s, ' ');
706 }
707
708 static int dbg_pinmux_show(struct seq_file *s, void *unused)
709 {
710         int i;
711         int len;
712
713         for (i = 0; i < TEGRA_MAX_PINGROUP; i++) {
714                 unsigned long tri;
715                 unsigned long mux;
716                 unsigned long pupd;
717
718                 seq_printf(s, "\t{TEGRA_PINGROUP_%s", pingroups[i].name);
719                 len = strlen(pingroups[i].name);
720                 dbg_pad_field(s, 5 - len);
721
722                 if (pingroups[i].mux_reg < 0) {
723                         seq_printf(s, "TEGRA_MUX_NONE");
724                         len = strlen("NONE");
725                 } else {
726                         mux = (pg_readl(pingroups[i].mux_reg) >>
727                                pingroups[i].mux_bit) & 0x3;
728                         if (pingroups[i].funcs[mux] == TEGRA_MUX_RSVD) {
729                                 seq_printf(s, "TEGRA_MUX_RSVD%1lu", mux+1);
730                                 len = 5;
731                         } else {
732                                 seq_printf(s, "TEGRA_MUX_%s",
733                                            tegra_mux_names[pingroups[i].funcs[mux]]);
734                                 len = strlen(tegra_mux_names[pingroups[i].funcs[mux]]);
735                         }
736                 }
737                 dbg_pad_field(s, 13-len);
738
739                 if (pingroups[i].pupd_reg < 0) {
740                         seq_printf(s, "TEGRA_PUPD_NORMAL");
741                         len = strlen("NORMAL");
742                 } else {
743                         pupd = (pg_readl(pingroups[i].pupd_reg) >>
744                                 pingroups[i].pupd_bit) & 0x3;
745                         seq_printf(s, "TEGRA_PUPD_%s", pupd_name(pupd));
746                         len = strlen(pupd_name(pupd));
747                 }
748                 dbg_pad_field(s, 9 - len);
749
750                 if (pingroups[i].tri_reg < 0) {
751                         seq_printf(s, "TEGRA_TRI_NORMAL");
752                 } else {
753                         tri = (pg_readl(pingroups[i].tri_reg) >>
754                                pingroups[i].tri_bit) & 0x1;
755
756                         seq_printf(s, "TEGRA_TRI_%s", tri_name(tri));
757                 }
758                 seq_printf(s, "},\n");
759         }
760         return 0;
761 }
762
763 static int dbg_pinmux_open(struct inode *inode, struct file *file)
764 {
765         return single_open(file, dbg_pinmux_show, &inode->i_private);
766 }
767
768 static const struct file_operations debug_fops = {
769         .open           = dbg_pinmux_open,
770         .read           = seq_read,
771         .llseek         = seq_lseek,
772         .release        = single_release,
773 };
774
775 static int dbg_drive_pinmux_show(struct seq_file *s, void *unused)
776 {
777         int i;
778         int len;
779
780         for (i = 0; i < TEGRA_MAX_DRIVE_PINGROUP; i++) {
781                 u32 reg;
782
783                 seq_printf(s, "\t{TEGRA_DRIVE_PINGROUP_%s",
784                         drive_pingroups[i].name);
785                 len = strlen(drive_pingroups[i].name);
786                 dbg_pad_field(s, 7 - len);
787
788
789                 reg = pg_readl(drive_pingroups[i].reg);
790                 if (HSM_EN(reg)) {
791                         seq_printf(s, "TEGRA_HSM_ENABLE");
792                         len = 16;
793                 } else {
794                         seq_printf(s, "TEGRA_HSM_DISABLE");
795                         len = 17;
796                 }
797                 dbg_pad_field(s, 17 - len);
798
799                 if (SCHMT_EN(reg)) {
800                         seq_printf(s, "TEGRA_SCHMITT_ENABLE");
801                         len = 21;
802                 } else {
803                         seq_printf(s, "TEGRA_SCHMITT_DISABLE");
804                         len = 22;
805                 }
806                 dbg_pad_field(s, 22 - len);
807
808                 seq_printf(s, "TEGRA_DRIVE_%s", drive_name(LPMD(reg)));
809                 len = strlen(drive_name(LPMD(reg)));
810                 dbg_pad_field(s, 5 - len);
811
812                 seq_printf(s, "TEGRA_PULL_%d", DRVDN(reg));
813                 len = DRVDN(reg) < 10 ? 1 : 2;
814                 dbg_pad_field(s, 2 - len);
815
816                 seq_printf(s, "TEGRA_PULL_%d", DRVUP(reg));
817                 len = DRVUP(reg) < 10 ? 1 : 2;
818                 dbg_pad_field(s, 2 - len);
819
820                 seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWR(reg)));
821                 len = strlen(slew_name(SLWR(reg)));
822                 dbg_pad_field(s, 7 - len);
823
824                 seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWF(reg)));
825
826                 seq_printf(s, "},\n");
827         }
828         return 0;
829 }
830
831 static int dbg_drive_pinmux_open(struct inode *inode, struct file *file)
832 {
833         return single_open(file, dbg_drive_pinmux_show, &inode->i_private);
834 }
835
836 static const struct file_operations debug_drive_fops = {
837         .open           = dbg_drive_pinmux_open,
838         .read           = seq_read,
839         .llseek         = seq_lseek,
840         .release        = single_release,
841 };
842
843 static int __init tegra_pinmux_debuginit(void)
844 {
845         (void) debugfs_create_file("tegra_pinmux", S_IRUGO,
846                                         NULL, NULL, &debug_fops);
847         (void) debugfs_create_file("tegra_pinmux_drive", S_IRUGO,
848                                         NULL, NULL, &debug_drive_fops);
849         return 0;
850 }
851 late_initcall(tegra_pinmux_debuginit);
852 #endif