[ARM/tegra] Add Tegra3 support
[linux-2.6.git] / arch / arm / mach-tegra / pinmux.c
1 /*
2  * linux/arch/arm/mach-tegra/pinmux.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/spinlock.h>
22 #include <linux/io.h>
23
24 #include <mach/iomap.h>
25 #include <mach/pinmux.h>
26
27 #define HSM_EN(reg)     (((reg) >> 2) & 0x1)
28 #define SCHMT_EN(reg)   (((reg) >> 3) & 0x1)
29 #define LPMD(reg)       (((reg) >> 4) & 0x3)
30 #define DRVDN(reg)      (((reg) >> 12) & 0x1f)
31 #define DRVUP(reg)      (((reg) >> 20) & 0x1f)
32 #define SLWR(reg)       (((reg) >> 28) & 0x3)
33 #define SLWF(reg)       (((reg) >> 30) & 0x3)
34
35 static const struct tegra_pingroup_desc *const pingroups = tegra_soc_pingroups;
36 static const struct tegra_drive_pingroup_desc *const drive_pingroups = tegra_soc_drive_pingroups;
37
38 static char *tegra_mux_names[TEGRA_MAX_MUX] = {
39         [TEGRA_MUX_AHB_CLK] = "AHB_CLK",
40         [TEGRA_MUX_APB_CLK] = "APB_CLK",
41         [TEGRA_MUX_AUDIO_SYNC] = "AUDIO_SYNC",
42         [TEGRA_MUX_CRT] = "CRT",
43         [TEGRA_MUX_DAP1] = "DAP1",
44         [TEGRA_MUX_DAP2] = "DAP2",
45         [TEGRA_MUX_DAP3] = "DAP3",
46         [TEGRA_MUX_DAP4] = "DAP4",
47         [TEGRA_MUX_DAP5] = "DAP5",
48         [TEGRA_MUX_DISPLAYA] = "DISPLAYA",
49         [TEGRA_MUX_DISPLAYB] = "DISPLAYB",
50         [TEGRA_MUX_EMC_TEST0_DLL] = "EMC_TEST0_DLL",
51         [TEGRA_MUX_EMC_TEST1_DLL] = "EMC_TEST1_DLL",
52         [TEGRA_MUX_GMI] = "GMI",
53         [TEGRA_MUX_GMI_INT] = "GMI_INT",
54         [TEGRA_MUX_HDMI] = "HDMI",
55         [TEGRA_MUX_I2C] = "I2C",
56         [TEGRA_MUX_I2C2] = "I2C2",
57         [TEGRA_MUX_I2C3] = "I2C3",
58         [TEGRA_MUX_IDE] = "IDE",
59         [TEGRA_MUX_IRDA] = "IRDA",
60         [TEGRA_MUX_KBC] = "KBC",
61         [TEGRA_MUX_MIO] = "MIO",
62         [TEGRA_MUX_MIPI_HS] = "MIPI_HS",
63         [TEGRA_MUX_NAND] = "NAND",
64         [TEGRA_MUX_OSC] = "OSC",
65         [TEGRA_MUX_OWR] = "OWR",
66         [TEGRA_MUX_PCIE] = "PCIE",
67         [TEGRA_MUX_PLLA_OUT] = "PLLA_OUT",
68         [TEGRA_MUX_PLLC_OUT1] = "PLLC_OUT1",
69         [TEGRA_MUX_PLLM_OUT1] = "PLLM_OUT1",
70         [TEGRA_MUX_PLLP_OUT2] = "PLLP_OUT2",
71         [TEGRA_MUX_PLLP_OUT3] = "PLLP_OUT3",
72         [TEGRA_MUX_PLLP_OUT4] = "PLLP_OUT4",
73         [TEGRA_MUX_PWM] = "PWM",
74         [TEGRA_MUX_PWR_INTR] = "PWR_INTR",
75         [TEGRA_MUX_PWR_ON] = "PWR_ON",
76         [TEGRA_MUX_RTCK] = "RTCK",
77         [TEGRA_MUX_SDIO1] = "SDIO1",
78         [TEGRA_MUX_SDIO2] = "SDIO2",
79         [TEGRA_MUX_SDIO3] = "SDIO3",
80         [TEGRA_MUX_SDIO4] = "SDIO4",
81         [TEGRA_MUX_SFLASH] = "SFLASH",
82         [TEGRA_MUX_SPDIF] = "SPDIF",
83         [TEGRA_MUX_SPI1] = "SPI1",
84         [TEGRA_MUX_SPI2] = "SPI2",
85         [TEGRA_MUX_SPI2_ALT] = "SPI2_ALT",
86         [TEGRA_MUX_SPI3] = "SPI3",
87         [TEGRA_MUX_SPI4] = "SPI4",
88         [TEGRA_MUX_TRACE] = "TRACE",
89         [TEGRA_MUX_TWC] = "TWC",
90         [TEGRA_MUX_UARTA] = "UARTA",
91         [TEGRA_MUX_UARTB] = "UARTB",
92         [TEGRA_MUX_UARTC] = "UARTC",
93         [TEGRA_MUX_UARTD] = "UARTD",
94         [TEGRA_MUX_UARTE] = "UARTE",
95         [TEGRA_MUX_ULPI] = "ULPI",
96         [TEGRA_MUX_VI] = "VI",
97         [TEGRA_MUX_VI_SENSOR_CLK] = "VI_SENSOR_CLK",
98         [TEGRA_MUX_XIO] = "XIO",
99 #if defined(CONFIG_ARCH_TEGRA_3x_SOC)
100         [TEGRA_MUX_BLINK] = "BLINK",
101         [TEGRA_MUX_CEC] = "CEC",
102         [TEGRA_MUX_CLK12] = "CLK12",
103         [TEGRA_MUX_DAP] = "DAP",
104         [TEGRA_MUX_DAPSDMMC2] = "DAPSDMMC2",
105         [TEGRA_MUX_DDR] = "DDR",
106         [TEGRA_MUX_DEV3] = "DEV3",
107         [TEGRA_MUX_DTV] = "DTV",
108         [TEGRA_MUX_VI_ALT1] = "VI_ALT1",
109         [TEGRA_MUX_VI_ALT2] = "VI_ALT2",
110         [TEGRA_MUX_VI_ALT3] = "VI_ALT3",
111         [TEGRA_MUX_EMC_DLL] = "EMC_DLL",
112         [TEGRA_MUX_EXTPERIPH1] = "EXTPERIPH1",
113         [TEGRA_MUX_EXTPERIPH2] = "EXTPERIPH2",
114         [TEGRA_MUX_EXTPERIPH3] = "EXTPERIPH3",
115         [TEGRA_MUX_GMI_ALT] = "GMI_ALT",
116         [TEGRA_MUX_HDA] = "HDA",
117         [TEGRA_MUX_HSI] = "HSI",
118         [TEGRA_MUX_I2C4] = "I2C4",
119         [TEGRA_MUX_I2C5] = "I2C5",
120         [TEGRA_MUX_I2CPWR] = "I2CPWR",
121         [TEGRA_MUX_I2S0] = "I2S0",
122         [TEGRA_MUX_I2S1] = "I2S1",
123         [TEGRA_MUX_I2S2] = "I2S2",
124         [TEGRA_MUX_I2S3] = "I2S3",
125         [TEGRA_MUX_I2S4] = "I2S4",
126         [TEGRA_MUX_NAND_ALT] = "NAND_ALT",
127         [TEGRA_MUX_POPSDIO4] = "POPSDIO4",
128         [TEGRA_MUX_POPSDMMC4] = "POPSDMMC4",
129         [TEGRA_MUX_PWM0] = "PWM0",
130         [TEGRA_MUX_PWM1] = "PWM1",
131         [TEGRA_MUX_PWM2] = "PWM2",
132         [TEGRA_MUX_PWM3] = "PWM3",
133         [TEGRA_MUX_SATA] = "SATA",
134         [TEGRA_MUX_SPI5] = "SPI5",
135         [TEGRA_MUX_SPI6] = "SPI6",
136         [TEGRA_MUX_SYSCLK] = "SYSCLK",
137         [TEGRA_MUX_VGP1] = "VGP1",
138         [TEGRA_MUX_VGP2] = "VGP2",
139         [TEGRA_MUX_VGP3] = "VGP3",
140         [TEGRA_MUX_VGP4] = "VGP4",
141         [TEGRA_MUX_VGP5] = "VGP5",
142         [TEGRA_MUX_VGP6] = "VGP6",
143 #endif
144         [TEGRA_MUX_SAFE] = "<safe>",
145 };
146
147 static const char *tegra_drive_names[TEGRA_MAX_DRIVE] = {
148         [TEGRA_DRIVE_DIV_8] = "DIV_8",
149         [TEGRA_DRIVE_DIV_4] = "DIV_4",
150         [TEGRA_DRIVE_DIV_2] = "DIV_2",
151         [TEGRA_DRIVE_DIV_1] = "DIV_1",
152 };
153
154 static const char *tegra_slew_names[TEGRA_MAX_SLEW] = {
155         [TEGRA_SLEW_FASTEST] = "FASTEST",
156         [TEGRA_SLEW_FAST] = "FAST",
157         [TEGRA_SLEW_SLOW] = "SLOW",
158         [TEGRA_SLEW_SLOWEST] = "SLOWEST",
159 };
160
161 static DEFINE_SPINLOCK(mux_lock);
162
163 static const char *pingroup_name(enum tegra_pingroup pg)
164 {
165         if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
166                 return "<UNKNOWN>";
167
168         return pingroups[pg].name;
169 }
170
171 static const char *func_name(enum tegra_mux_func func)
172 {
173         if (func == TEGRA_MUX_RSVD1)
174                 return "RSVD1";
175
176         if (func == TEGRA_MUX_RSVD2)
177                 return "RSVD2";
178
179         if (func == TEGRA_MUX_RSVD3)
180                 return "RSVD3";
181
182         if (func == TEGRA_MUX_RSVD4)
183                 return "RSVD4";
184
185         if (func == TEGRA_MUX_NONE)
186                 return "NONE";
187
188         if (func < 0 || func >=  TEGRA_MAX_MUX)
189                 return "<UNKNOWN>";
190
191         return tegra_mux_names[func];
192 }
193
194
195 static const char *tri_name(unsigned long val)
196 {
197         return val ? "TRISTATE" : "NORMAL";
198 }
199
200 static const char *pupd_name(unsigned long val)
201 {
202         switch (val) {
203         case 0:
204                 return "NORMAL";
205
206         case 1:
207                 return "PULL_DOWN";
208
209         case 2:
210                 return "PULL_UP";
211
212         default:
213                 return "RSVD";
214         }
215 }
216
217 #if defined(TEGRA_PINMUX_HAS_IO_DIRECTION)
218 static const char *io_name(unsigned long val)
219 {
220         switch (val) {
221         case 0:
222                 return "OUTPUT";
223
224         case 1:
225                 return "INPUT";
226
227         default:
228                 return "RSVD";
229         }
230 }
231 #endif
232
233 static inline unsigned long pg_readl(unsigned long offset)
234 {
235         return readl(IO_TO_VIRT(TEGRA_APB_MISC_BASE) + offset);
236 }
237
238 static inline void pg_writel(unsigned long value, unsigned long offset)
239 {
240         writel(value, IO_TO_VIRT(TEGRA_APB_MISC_BASE) + offset);
241 }
242
243 static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config)
244 {
245         int mux = -1;
246         int i;
247         unsigned long reg;
248         unsigned long flags;
249         enum tegra_pingroup pg = config->pingroup;
250         enum tegra_mux_func func = config->func;
251
252         if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
253                 return -ERANGE;
254
255         if (pingroups[pg].mux_reg < 0)
256                 return -EINVAL;
257
258         if (func < 0)
259                 return -ERANGE;
260
261         if (func == TEGRA_MUX_SAFE)
262                 func = pingroups[pg].func_safe;
263
264         if (func & TEGRA_MUX_RSVD) {
265                 mux = func & 0x3;
266         } else {
267                 for (i = 0; i < 4; i++) {
268                         if (pingroups[pg].funcs[i] == func) {
269                                 mux = i;
270                                 break;
271                         }
272                 }
273         }
274
275         if (mux < 0)
276                 return -EINVAL;
277
278         spin_lock_irqsave(&mux_lock, flags);
279
280         reg = pg_readl(pingroups[pg].mux_reg);
281         reg &= ~(0x3 << pingroups[pg].mux_bit);
282         reg |= mux << pingroups[pg].mux_bit;
283 #if defined(TEGRA_PINMUX_HAS_IO_DIRECTION)
284         reg &= ~(0x1 << 5);
285         reg |= ((config->io & 0x1) << 5);
286 #endif
287         pg_writel(reg, pingroups[pg].mux_reg);
288
289         spin_unlock_irqrestore(&mux_lock, flags);
290
291         return 0;
292 }
293
294 int tegra_pinmux_get_func(enum tegra_pingroup pg)
295 {
296         int mux = -1;
297         unsigned long reg;
298         unsigned long flags;
299
300         if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
301                 return -ERANGE;
302
303         if (pingroups[pg].mux_reg < 0)
304                 return -EINVAL;
305
306         spin_lock_irqsave(&mux_lock, flags);
307
308         reg = pg_readl(pingroups[pg].mux_reg);
309         mux = (reg >> pingroups[pg].mux_bit) & 0x3;
310
311         spin_unlock_irqrestore(&mux_lock, flags);
312
313         return mux;
314 }
315
316 int tegra_pinmux_set_tristate(enum tegra_pingroup pg,
317         enum tegra_tristate tristate)
318 {
319         unsigned long reg;
320         unsigned long flags;
321
322         if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
323                 return -ERANGE;
324
325         if (pingroups[pg].tri_reg < 0)
326                 return -EINVAL;
327
328         spin_lock_irqsave(&mux_lock, flags);
329
330         reg = pg_readl(pingroups[pg].tri_reg);
331         reg &= ~(0x1 << pingroups[pg].tri_bit);
332         if (tristate)
333                 reg |= 1 << pingroups[pg].tri_bit;
334         pg_writel(reg, pingroups[pg].tri_reg);
335
336         spin_unlock_irqrestore(&mux_lock, flags);
337
338         return 0;
339 }
340
341 int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg,
342         enum tegra_pullupdown pupd)
343 {
344         unsigned long reg;
345         unsigned long flags;
346
347         if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
348                 return -ERANGE;
349
350         if (pingroups[pg].pupd_reg < 0)
351                 return -EINVAL;
352
353         if (pupd != TEGRA_PUPD_NORMAL &&
354             pupd != TEGRA_PUPD_PULL_DOWN &&
355             pupd != TEGRA_PUPD_PULL_UP)
356                 return -EINVAL;
357
358
359         spin_lock_irqsave(&mux_lock, flags);
360
361         reg = pg_readl(pingroups[pg].pupd_reg);
362         reg &= ~(0x3 << pingroups[pg].pupd_bit);
363         reg |= pupd << pingroups[pg].pupd_bit;
364         pg_writel(reg, pingroups[pg].pupd_reg);
365
366         spin_unlock_irqrestore(&mux_lock, flags);
367
368         return 0;
369 }
370
371 static void tegra_pinmux_config_pingroup(const struct tegra_pingroup_config *config)
372 {
373         enum tegra_pingroup pingroup = config->pingroup;
374         enum tegra_mux_func func     = config->func;
375         enum tegra_pullupdown pupd   = config->pupd;
376         enum tegra_tristate tristate = config->tristate;
377         int err;
378
379         if (pingroups[pingroup].mux_reg >= 0) {
380                 err = tegra_pinmux_set_func(config);
381                 if (err < 0)
382                         pr_err("pinmux: can't set pingroup %s func to %s: %d\n",
383                                pingroup_name(pingroup), func_name(func), err);
384         }
385
386         if (pingroups[pingroup].pupd_reg >= 0) {
387                 err = tegra_pinmux_set_pullupdown(pingroup, pupd);
388                 if (err < 0)
389                         pr_err("pinmux: can't set pingroup %s pullupdown to %s: %d\n",
390                                pingroup_name(pingroup), pupd_name(pupd), err);
391         }
392
393         if (pingroups[pingroup].tri_reg >= 0) {
394                 err = tegra_pinmux_set_tristate(pingroup, tristate);
395                 if (err < 0)
396                         pr_err("pinmux: can't set pingroup %s tristate to %s: %d\n",
397                                pingroup_name(pingroup), tri_name(func), err);
398         }
399 }
400
401 void tegra_pinmux_config_table(const struct tegra_pingroup_config *config, int len)
402 {
403         int i;
404
405         for (i = 0; i < len; i++)
406                 tegra_pinmux_config_pingroup(&config[i]);
407 }
408
409 static const char *drive_pinmux_name(enum tegra_drive_pingroup pg)
410 {
411         if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
412                 return "<UNKNOWN>";
413
414         return drive_pingroups[pg].name;
415 }
416
417 static const char *enable_name(unsigned long val)
418 {
419         return val ? "ENABLE" : "DISABLE";
420 }
421
422 static const char *drive_name(unsigned long val)
423 {
424         if (val >= TEGRA_MAX_DRIVE)
425                 return "<UNKNOWN>";
426
427         return tegra_drive_names[val];
428 }
429
430 static const char *slew_name(unsigned long val)
431 {
432         if (val >= TEGRA_MAX_SLEW)
433                 return "<UNKNOWN>";
434
435         return tegra_slew_names[val];
436 }
437
438 static int tegra_drive_pinmux_set_hsm(enum tegra_drive_pingroup pg,
439         enum tegra_hsm hsm)
440 {
441         unsigned long flags;
442         u32 reg;
443         if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
444                 return -ERANGE;
445
446         if (hsm != TEGRA_HSM_ENABLE && hsm != TEGRA_HSM_DISABLE)
447                 return -EINVAL;
448
449         spin_lock_irqsave(&mux_lock, flags);
450
451         reg = pg_readl(drive_pingroups[pg].reg);
452         if (hsm == TEGRA_HSM_ENABLE)
453                 reg |= (1 << 2);
454         else
455                 reg &= ~(1 << 2);
456         pg_writel(reg, drive_pingroups[pg].reg);
457
458         spin_unlock_irqrestore(&mux_lock, flags);
459
460         return 0;
461 }
462
463 static int tegra_drive_pinmux_set_schmitt(enum tegra_drive_pingroup pg,
464         enum tegra_schmitt schmitt)
465 {
466         unsigned long flags;
467         u32 reg;
468         if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
469                 return -ERANGE;
470
471         if (schmitt != TEGRA_SCHMITT_ENABLE && schmitt != TEGRA_SCHMITT_DISABLE)
472                 return -EINVAL;
473
474         spin_lock_irqsave(&mux_lock, flags);
475
476         reg = pg_readl(drive_pingroups[pg].reg);
477         if (schmitt == TEGRA_SCHMITT_ENABLE)
478                 reg |= (1 << 3);
479         else
480                 reg &= ~(1 << 3);
481         pg_writel(reg, drive_pingroups[pg].reg);
482
483         spin_unlock_irqrestore(&mux_lock, flags);
484
485         return 0;
486 }
487
488 static int tegra_drive_pinmux_set_drive(enum tegra_drive_pingroup pg,
489         enum tegra_drive drive)
490 {
491         unsigned long flags;
492         u32 reg;
493         if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
494                 return -ERANGE;
495
496         if (drive < 0 || drive >= TEGRA_MAX_DRIVE)
497                 return -EINVAL;
498
499         spin_lock_irqsave(&mux_lock, flags);
500
501         reg = pg_readl(drive_pingroups[pg].reg);
502         reg &= ~(0x3 << 4);
503         reg |= drive << 4;
504         pg_writel(reg, drive_pingroups[pg].reg);
505
506         spin_unlock_irqrestore(&mux_lock, flags);
507
508         return 0;
509 }
510
511 static int tegra_drive_pinmux_set_pull_down(enum tegra_drive_pingroup pg,
512         enum tegra_pull_strength pull_down)
513 {
514         unsigned long flags;
515         u32 reg;
516         if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
517                 return -ERANGE;
518
519         if (pull_down < 0 || pull_down >= TEGRA_MAX_PULL)
520                 return -EINVAL;
521
522         spin_lock_irqsave(&mux_lock, flags);
523
524         reg = pg_readl(drive_pingroups[pg].reg);
525         reg &= ~(0x1f << 12);
526         reg |= pull_down << 12;
527         pg_writel(reg, drive_pingroups[pg].reg);
528
529         spin_unlock_irqrestore(&mux_lock, flags);
530
531         return 0;
532 }
533
534 static int tegra_drive_pinmux_set_pull_up(enum tegra_drive_pingroup pg,
535         enum tegra_pull_strength pull_up)
536 {
537         unsigned long flags;
538         u32 reg;
539         if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
540                 return -ERANGE;
541
542         if (pull_up < 0 || pull_up >= TEGRA_MAX_PULL)
543                 return -EINVAL;
544
545         spin_lock_irqsave(&mux_lock, flags);
546
547         reg = pg_readl(drive_pingroups[pg].reg);
548         reg &= ~(0x1f << 20);
549         reg |= pull_up << 20;
550         pg_writel(reg, drive_pingroups[pg].reg);
551
552         spin_unlock_irqrestore(&mux_lock, flags);
553
554         return 0;
555 }
556
557 static int tegra_drive_pinmux_set_slew_rising(enum tegra_drive_pingroup pg,
558         enum tegra_slew slew_rising)
559 {
560         unsigned long flags;
561         u32 reg;
562         if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
563                 return -ERANGE;
564
565         if (slew_rising < 0 || slew_rising >= TEGRA_MAX_SLEW)
566                 return -EINVAL;
567
568         spin_lock_irqsave(&mux_lock, flags);
569
570         reg = pg_readl(drive_pingroups[pg].reg);
571         reg &= ~(0x3 << 28);
572         reg |= slew_rising << 28;
573         pg_writel(reg, drive_pingroups[pg].reg);
574
575         spin_unlock_irqrestore(&mux_lock, flags);
576
577         return 0;
578 }
579
580 static int tegra_drive_pinmux_set_slew_falling(enum tegra_drive_pingroup pg,
581         enum tegra_slew slew_falling)
582 {
583         unsigned long flags;
584         u32 reg;
585         if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
586                 return -ERANGE;
587
588         if (slew_falling < 0 || slew_falling >= TEGRA_MAX_SLEW)
589                 return -EINVAL;
590
591         spin_lock_irqsave(&mux_lock, flags);
592
593         reg = pg_readl(drive_pingroups[pg].reg);
594         reg &= ~(0x3 << 30);
595         reg |= slew_falling << 30;
596         pg_writel(reg, drive_pingroups[pg].reg);
597
598         spin_unlock_irqrestore(&mux_lock, flags);
599
600         return 0;
601 }
602
603 static void tegra_drive_pinmux_config_pingroup(enum tegra_drive_pingroup pingroup,
604                                           enum tegra_hsm hsm,
605                                           enum tegra_schmitt schmitt,
606                                           enum tegra_drive drive,
607                                           enum tegra_pull_strength pull_down,
608                                           enum tegra_pull_strength pull_up,
609                                           enum tegra_slew slew_rising,
610                                           enum tegra_slew slew_falling)
611 {
612         int err;
613
614         err = tegra_drive_pinmux_set_hsm(pingroup, hsm);
615         if (err < 0)
616                 pr_err("pinmux: can't set pingroup %s hsm to %s: %d\n",
617                         drive_pinmux_name(pingroup),
618                         enable_name(hsm), err);
619
620         err = tegra_drive_pinmux_set_schmitt(pingroup, schmitt);
621         if (err < 0)
622                 pr_err("pinmux: can't set pingroup %s schmitt to %s: %d\n",
623                         drive_pinmux_name(pingroup),
624                         enable_name(schmitt), err);
625
626         err = tegra_drive_pinmux_set_drive(pingroup, drive);
627         if (err < 0)
628                 pr_err("pinmux: can't set pingroup %s drive to %s: %d\n",
629                         drive_pinmux_name(pingroup),
630                         drive_name(drive), err);
631
632         err = tegra_drive_pinmux_set_pull_down(pingroup, pull_down);
633         if (err < 0)
634                 pr_err("pinmux: can't set pingroup %s pull down to %d: %d\n",
635                         drive_pinmux_name(pingroup),
636                         pull_down, err);
637
638         err = tegra_drive_pinmux_set_pull_up(pingroup, pull_up);
639         if (err < 0)
640                 pr_err("pinmux: can't set pingroup %s pull up to %d: %d\n",
641                         drive_pinmux_name(pingroup),
642                         pull_up, err);
643
644         err = tegra_drive_pinmux_set_slew_rising(pingroup, slew_rising);
645         if (err < 0)
646                 pr_err("pinmux: can't set pingroup %s rising slew to %s: %d\n",
647                         drive_pinmux_name(pingroup),
648                         slew_name(slew_rising), err);
649
650         err = tegra_drive_pinmux_set_slew_falling(pingroup, slew_falling);
651         if (err < 0)
652                 pr_err("pinmux: can't set pingroup %s falling slew to %s: %d\n",
653                         drive_pinmux_name(pingroup),
654                         slew_name(slew_falling), err);
655 }
656
657 void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
658         int len)
659 {
660         int i;
661
662         for (i = 0; i < len; i++)
663                 tegra_drive_pinmux_config_pingroup(config[i].pingroup,
664                                                      config[i].hsm,
665                                                      config[i].schmitt,
666                                                      config[i].drive,
667                                                      config[i].pull_down,
668                                                      config[i].pull_up,
669                                                      config[i].slew_rising,
670                                                      config[i].slew_falling);
671 }
672
673 void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config,
674         int len)
675 {
676         int i;
677         struct tegra_pingroup_config c;
678
679         for (i = 0; i < len; i++) {
680                 int err;
681                 c = config[i];
682                 if (c.pingroup < 0 || c.pingroup >= TEGRA_MAX_PINGROUP) {
683                         WARN_ON(1);
684                         continue;
685                 }
686                 c.func = pingroups[c.pingroup].func_safe;
687                 err = tegra_pinmux_set_func(&c);
688                 if (err < 0)
689                         pr_err("%s: tegra_pinmux_set_func returned %d setting "
690                                "%s to %s\n", __func__, err,
691                                pingroup_name(c.pingroup), func_name(c.func));
692         }
693 }
694
695 void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config,
696         int len)
697 {
698         int i;
699
700         for (i = 0; i < len; i++) {
701                 int err;
702                 if (config[i].pingroup < 0 ||
703                     config[i].pingroup >= TEGRA_MAX_PINGROUP) {
704                         WARN_ON(1);
705                         continue;
706                 }
707                 err = tegra_pinmux_set_func(&config[i]);
708                 if (err < 0)
709                         pr_err("%s: tegra_pinmux_set_func returned %d setting "
710                                "%s to %s\n", __func__, err,
711                                pingroup_name(config[i].pingroup),
712                                func_name(config[i].func));
713         }
714 }
715
716 void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config,
717         int len, enum tegra_tristate tristate)
718 {
719         int i;
720         int err;
721         enum tegra_pingroup pingroup;
722
723         for (i = 0; i < len; i++) {
724                 pingroup = config[i].pingroup;
725                 if (pingroups[pingroup].tri_reg >= 0) {
726                         err = tegra_pinmux_set_tristate(pingroup, tristate);
727                         if (err < 0)
728                                 pr_err("pinmux: can't set pingroup %s tristate"
729                                         " to %s: %d\n", pingroup_name(pingroup),
730                                         tri_name(tristate), err);
731                 }
732         }
733 }
734
735 void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
736         int len, enum tegra_pullupdown pupd)
737 {
738         int i;
739         int err;
740         enum tegra_pingroup pingroup;
741
742         for (i = 0; i < len; i++) {
743                 pingroup = config[i].pingroup;
744                 if (pingroups[pingroup].pupd_reg >= 0) {
745                         err = tegra_pinmux_set_pullupdown(pingroup, pupd);
746                         if (err < 0)
747                                 pr_err("pinmux: can't set pingroup %s pullupdown"
748                                         " to %s: %d\n", pingroup_name(pingroup),
749                                         pupd_name(pupd), err);
750                 }
751         }
752 }
753
754 void tegra_init_pinmux(void)
755 {
756         tegra2_init_pinmux();
757 }
758
759 #ifdef  CONFIG_DEBUG_FS
760
761 #include <linux/debugfs.h>
762 #include <linux/seq_file.h>
763
764 static void dbg_pad_field(struct seq_file *s, int len)
765 {
766         seq_putc(s, ',');
767
768         while (len-- > -1)
769                 seq_putc(s, ' ');
770 }
771
772 static int dbg_pinmux_show(struct seq_file *s, void *unused)
773 {
774         int i;
775         int len;
776
777         for (i = 0; i < TEGRA_MAX_PINGROUP; i++) {
778                 unsigned long tri;
779                 unsigned long mux;
780                 unsigned long pupd;
781
782                 seq_printf(s, "\t{TEGRA_PINGROUP_%s", pingroups[i].name);
783                 len = strlen(pingroups[i].name);
784                 dbg_pad_field(s, 15 - len);
785
786                 if (pingroups[i].mux_reg < 0) {
787                         seq_printf(s, "TEGRA_MUX_NONE");
788                         len = strlen("NONE");
789                 } else {
790                         mux = (pg_readl(pingroups[i].mux_reg) >>
791                                pingroups[i].mux_bit) & 0x3;
792                         BUG_ON(pingroups[i].funcs[mux] == 0);
793                         if (pingroups[i].funcs[mux] & TEGRA_MUX_RSVD) {
794                                 seq_printf(s, "TEGRA_MUX_RSVD%1lu", mux+1);
795                                 len = 5;
796                         } else {
797                                 BUG_ON(!tegra_mux_names[pingroups[i].funcs[mux]]);
798                                 seq_printf(s, "TEGRA_MUX_%s",
799                                            tegra_mux_names[pingroups[i].funcs[mux]]);
800                                 len = strlen(tegra_mux_names[pingroups[i].funcs[mux]]);
801                         }
802                 }
803                 dbg_pad_field(s, 13-len);
804
805 #if defined(TEGRA_PINMUX_HAS_IO_DIRECTION)
806                 {
807                         unsigned long io;
808                         io = (pg_readl(pingroups[i].mux_reg) >> 5) & 0x1;
809                         seq_printf(s, "TEGRA_PIN_%s", io_name(io));
810                         len = strlen(io_name(io));
811                         dbg_pad_field(s, 6 - len);
812                 }
813 #endif
814                 if (pingroups[i].pupd_reg < 0) {
815                         seq_printf(s, "TEGRA_PUPD_NORMAL");
816                         len = strlen("NORMAL");
817                 } else {
818                         pupd = (pg_readl(pingroups[i].pupd_reg) >>
819                                 pingroups[i].pupd_bit) & 0x3;
820                         seq_printf(s, "TEGRA_PUPD_%s", pupd_name(pupd));
821                         len = strlen(pupd_name(pupd));
822                 }
823                 dbg_pad_field(s, 9 - len);
824
825                 if (pingroups[i].tri_reg < 0) {
826                         seq_printf(s, "TEGRA_TRI_NORMAL");
827                 } else {
828                         tri = (pg_readl(pingroups[i].tri_reg) >>
829                                pingroups[i].tri_bit) & 0x1;
830
831                         seq_printf(s, "TEGRA_TRI_%s", tri_name(tri));
832                 }
833                 seq_printf(s, "},\n");
834         }
835         return 0;
836 }
837
838 static int dbg_pinmux_open(struct inode *inode, struct file *file)
839 {
840         return single_open(file, dbg_pinmux_show, &inode->i_private);
841 }
842
843 static const struct file_operations debug_fops = {
844         .open           = dbg_pinmux_open,
845         .read           = seq_read,
846         .llseek         = seq_lseek,
847         .release        = single_release,
848 };
849
850 static int dbg_drive_pinmux_show(struct seq_file *s, void *unused)
851 {
852         int i;
853         int len;
854
855         for (i = 0; i < TEGRA_MAX_DRIVE_PINGROUP; i++) {
856                 u32 reg;
857
858                 seq_printf(s, "\t{TEGRA_DRIVE_PINGROUP_%s",
859                         drive_pingroups[i].name);
860                 len = strlen(drive_pingroups[i].name);
861                 dbg_pad_field(s, 7 - len);
862
863
864                 reg = pg_readl(drive_pingroups[i].reg);
865                 if (HSM_EN(reg)) {
866                         seq_printf(s, "TEGRA_HSM_ENABLE");
867                         len = 16;
868                 } else {
869                         seq_printf(s, "TEGRA_HSM_DISABLE");
870                         len = 17;
871                 }
872                 dbg_pad_field(s, 17 - len);
873
874                 if (SCHMT_EN(reg)) {
875                         seq_printf(s, "TEGRA_SCHMITT_ENABLE");
876                         len = 21;
877                 } else {
878                         seq_printf(s, "TEGRA_SCHMITT_DISABLE");
879                         len = 22;
880                 }
881                 dbg_pad_field(s, 22 - len);
882
883                 seq_printf(s, "TEGRA_DRIVE_%s", drive_name(LPMD(reg)));
884                 len = strlen(drive_name(LPMD(reg)));
885                 dbg_pad_field(s, 5 - len);
886
887                 seq_printf(s, "TEGRA_PULL_%d", DRVDN(reg));
888                 len = DRVDN(reg) < 10 ? 1 : 2;
889                 dbg_pad_field(s, 2 - len);
890
891                 seq_printf(s, "TEGRA_PULL_%d", DRVUP(reg));
892                 len = DRVUP(reg) < 10 ? 1 : 2;
893                 dbg_pad_field(s, 2 - len);
894
895                 seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWR(reg)));
896                 len = strlen(slew_name(SLWR(reg)));
897                 dbg_pad_field(s, 7 - len);
898
899                 seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWF(reg)));
900
901                 seq_printf(s, "},\n");
902         }
903         return 0;
904 }
905
906 static int dbg_drive_pinmux_open(struct inode *inode, struct file *file)
907 {
908         return single_open(file, dbg_drive_pinmux_show, &inode->i_private);
909 }
910
911 static const struct file_operations debug_drive_fops = {
912         .open           = dbg_drive_pinmux_open,
913         .read           = seq_read,
914         .llseek         = seq_lseek,
915         .release        = single_release,
916 };
917
918 static int __init tegra_pinmux_debuginit(void)
919 {
920         (void) debugfs_create_file("tegra_pinmux", S_IRUGO,
921                                         NULL, NULL, &debug_fops);
922         (void) debugfs_create_file("tegra_pinmux_drive", S_IRUGO,
923                                         NULL, NULL, &debug_drive_fops);
924         return 0;
925 }
926 late_initcall(tegra_pinmux_debuginit);
927 #endif