2 * linux/arch/arm/mach-tegra/pinmux.c
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (C) 2011 NVIDIA Corporation.
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/errno.h>
22 #include <linux/spinlock.h>
24 #include <linux/platform_device.h>
25 #include <linux/of_device.h>
27 #include <mach/iomap.h>
28 #include <mach/pinmux.h>
30 #define HSM_EN(reg) (((reg) >> 2) & 0x1)
31 #define SCHMT_EN(reg) (((reg) >> 3) & 0x1)
32 #define LPMD(reg) (((reg) >> 4) & 0x3)
33 #define DRVDN(reg, offset) (((reg) >> offset) & 0x1f)
34 #define DRVUP(reg, offset) (((reg) >> offset) & 0x1f)
35 #define SLWR(reg, offset) (((reg) >> offset) & 0x3)
36 #define SLWF(reg, offset) (((reg) >> offset) & 0x3)
38 static const struct tegra_pingroup_desc *pingroups;
39 static const struct tegra_drive_pingroup_desc *drive_pingroups;
40 static const int *gpio_to_pingroups_map;
41 static int pingroup_max;
43 static int gpio_to_pingroups_map_max;
45 static char *tegra_mux_names[TEGRA_MAX_MUX] = {
46 #define TEGRA_MUX(mux) [TEGRA_MUX_##mux] = #mux,
49 [TEGRA_MUX_SAFE] = "<safe>",
52 static const char *tegra_drive_names[TEGRA_MAX_DRIVE] = {
53 [TEGRA_DRIVE_DIV_8] = "DIV_8",
54 [TEGRA_DRIVE_DIV_4] = "DIV_4",
55 [TEGRA_DRIVE_DIV_2] = "DIV_2",
56 [TEGRA_DRIVE_DIV_1] = "DIV_1",
59 static const char *tegra_slew_names[TEGRA_MAX_SLEW] = {
60 [TEGRA_SLEW_FASTEST] = "FASTEST",
61 [TEGRA_SLEW_FAST] = "FAST",
62 [TEGRA_SLEW_SLOW] = "SLOW",
63 [TEGRA_SLEW_SLOWEST] = "SLOWEST",
66 static DEFINE_SPINLOCK(mux_lock);
68 static const char *pingroup_name(int pg)
70 if (pg < 0 || pg >= pingroup_max)
73 return pingroups[pg].name;
76 static const char *func_name(enum tegra_mux_func func)
78 if (func == TEGRA_MUX_RSVD1)
81 if (func == TEGRA_MUX_RSVD2)
84 if (func == TEGRA_MUX_RSVD3)
87 if (func == TEGRA_MUX_RSVD4)
90 if (func == TEGRA_MUX_INVALID)
93 if (func < 0 || func >= TEGRA_MAX_MUX)
96 return tegra_mux_names[func];
100 static const char *tri_name(unsigned long val)
102 return val ? "TRISTATE" : "NORMAL";
105 static const char *pupd_name(unsigned long val)
122 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
123 static const char *lock_name(unsigned long val)
126 case TEGRA_PIN_LOCK_DEFAULT:
127 return "LOCK_DEFUALT";
129 case TEGRA_PIN_LOCK_DISABLE:
130 return "LOCK_DISABLE";
132 case TEGRA_PIN_LOCK_ENABLE:
133 return "LOCK_ENABLE";
135 return "LOCK_DEFAULT";
139 static const char *od_name(unsigned long val)
142 case TEGRA_PIN_OD_DEFAULT:
145 case TEGRA_PIN_OD_DISABLE:
148 case TEGRA_PIN_OD_ENABLE:
155 static const char *ioreset_name(unsigned long val)
158 case TEGRA_PIN_IO_RESET_DEFAULT:
159 return "IO_RESET_DEFAULT";
161 case TEGRA_PIN_IO_RESET_DISABLE:
162 return "IO_RESET_DISABLE";
164 case TEGRA_PIN_IO_RESET_ENABLE:
165 return "IO_RESET_ENABLE";
167 return "IO_RESET_DEFAULT";
172 #if defined(TEGRA_PINMUX_HAS_IO_DIRECTION)
173 static const char *io_name(unsigned long val)
189 static void __iomem **regs;
191 static inline u32 pg_readl(u32 bank, u32 reg)
193 return readl(regs[bank] + reg);
196 static inline void pg_writel(u32 val, u32 bank, u32 reg)
198 writel(val, regs[bank] + reg);
201 int tegra_pinmux_get_pingroup(int gpio_nr)
203 return gpio_to_pingroups_map[gpio_nr];
205 EXPORT_SYMBOL_GPL(tegra_pinmux_get_pingroup);
207 static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config)
214 int pg = config->pingroup;
215 enum tegra_mux_func func = config->func;
217 if (pg < 0 || pg >= pingroup_max)
220 if (pingroups[pg].mux_reg <= 0)
223 if (func == TEGRA_MUX_INVALID) {
224 pr_err("The pingroup %s is not recommended for option %s\n",
225 pingroup_name(pg), func_name(func));
233 if (func == TEGRA_MUX_SAFE)
234 func = pingroups[pg].func_safe;
236 if (func & TEGRA_MUX_RSVD) {
237 for (i = 0; i < 4; i++) {
238 if (pingroups[pg].funcs[i] & TEGRA_MUX_RSVD)
241 if (pingroups[pg].funcs[i] == func) {
248 for (i = 0; i < 4; i++) {
249 if (pingroups[pg].funcs[i] == func) {
258 pr_err("The pingroup %s is not supported option %s\n",
259 pingroup_name(pg), func_name(func));
265 pr_warn("The pingroup %s was configured to %s instead of %s\n",
266 pingroup_name(pg), func_name(pingroups[pg].funcs[mux]),
269 spin_lock_irqsave(&mux_lock, flags);
271 reg = pg_readl(pingroups[pg].mux_bank, pingroups[pg].mux_reg);
272 reg &= ~(0x3 << pingroups[pg].mux_bit);
273 reg |= mux << pingroups[pg].mux_bit;
274 #if defined(TEGRA_PINMUX_HAS_IO_DIRECTION)
276 reg |= ((config->io & 0x1) << 5);
278 pg_writel(reg, pingroups[pg].mux_bank, pingroups[pg].mux_reg);
280 spin_unlock_irqrestore(&mux_lock, flags);
285 int tegra_pinmux_get_func(int tegra_pingroup pg)
291 if (pg < 0 || pg >= pingroup_max)
294 if (pingroups[pg].mux_reg <= 0)
297 spin_lock_irqsave(&mux_lock, flags);
299 reg = pg_readl(pingroups[pg].mux_bank, pingroups[pg].mux_reg);
300 mux = (reg >> pingroups[pg].mux_bit) & 0x3;
302 spin_unlock_irqrestore(&mux_lock, flags);
307 int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate)
312 if (pg < 0 || pg >= pingroup_max)
315 if (pingroups[pg].tri_reg <= 0)
318 spin_lock_irqsave(&mux_lock, flags);
320 reg = pg_readl(pingroups[pg].tri_bank, pingroups[pg].tri_reg);
321 reg &= ~(0x1 << pingroups[pg].tri_bit);
323 reg |= 1 << pingroups[pg].tri_bit;
324 pg_writel(reg, pingroups[pg].tri_bank, pingroups[pg].tri_reg);
326 spin_unlock_irqrestore(&mux_lock, flags);
331 int tegra_pinmux_set_io(int pg, enum tegra_pin_io input)
333 #if defined(TEGRA_PINMUX_HAS_IO_DIRECTION)
336 if (pg < 0 || pg >= pingroup_max)
339 io = pg_readl(pingroups[pg].mux_bank, pingroups[pg].mux_reg);
344 pg_writel(io, pingroups[pg].mux_bank, pingroups[pg].mux_reg);
348 EXPORT_SYMBOL_GPL(tegra_pinmux_set_io);
350 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
351 static int tegra_pinmux_set_lock(int pg, enum tegra_pin_lock lock)
356 if (pg < 0 || pg >= pingroup_max)
359 if (pingroups[pg].mux_reg <= 0)
362 if ((lock == TEGRA_PIN_LOCK_DEFAULT) || (pingroups[pg].lock_bit < 0))
365 spin_lock_irqsave(&mux_lock, flags);
367 reg = pg_readl(pingroups[pg].mux_reg);
368 reg &= ~(0x1 << pingroups[pg].lock_bit);
369 if (lock == TEGRA_PIN_LOCK_ENABLE)
370 reg |= (0x1 << pingroups[pg].lock_bit);
372 pg_writel(reg, pingroups[pg].mux_reg);
374 spin_unlock_irqrestore(&mux_lock, flags);
378 static int tegra_pinmux_set_od(int pg, enum tegra_pin_od od)
383 if (pg < 0 || pg >= pingroup_max)
386 if (pingroups[pg].mux_reg <= 0)
389 if ((od == TEGRA_PIN_OD_DEFAULT) || (pingroups[pg].od_bit < 0))
392 spin_lock_irqsave(&mux_lock, flags);
394 reg = pg_readl(pingroups[pg].mux_bank, pingroups[pg].mux_reg);
395 reg &= ~(0x1 << pingroups[pg].od_bit);
396 if (od == TEGRA_PIN_OD_ENABLE)
397 reg |= 1 << pingroups[pg].od_bit;
399 pg_writel(reg, pingroups[pg].mux_bank, pingroups[pg].mux_reg);
401 spin_unlock_irqrestore(&mux_lock, flags);
406 static int tegra_pinmux_set_ioreset(int pg, enum tegra_pin_ioreset ioreset)
411 if (pg < 0 || pg >= pingroup_max)
414 if (pingroups[pg].mux_reg <= 0)
417 if ((ioreset == TEGRA_PIN_IO_RESET_DEFAULT) || (pingroups[pg].ioreset_bit < 0))
420 spin_lock_irqsave(&mux_lock, flags);
422 reg = pg_readl(pingroups[pg].mux_bank, pingroups[pg].mux_reg);
423 reg &= ~(0x1 << pingroups[pg].ioreset_bit);
424 if (ioreset == TEGRA_PIN_IO_RESET_ENABLE)
425 reg |= 1 << pingroups[pg].ioreset_bit;
427 pg_writel(reg, pingroups[pg].mux_bank, pingroups[pg].mux_reg);
429 spin_unlock_irqrestore(&mux_lock, flags);
435 int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd)
440 if (pg < 0 || pg >= pingroup_max)
443 if (pingroups[pg].pupd_reg <= 0)
446 if (pupd != TEGRA_PUPD_NORMAL &&
447 pupd != TEGRA_PUPD_PULL_DOWN &&
448 pupd != TEGRA_PUPD_PULL_UP)
452 spin_lock_irqsave(&mux_lock, flags);
454 reg = pg_readl(pingroups[pg].pupd_bank, pingroups[pg].pupd_reg);
455 reg &= ~(0x3 << pingroups[pg].pupd_bit);
456 reg |= pupd << pingroups[pg].pupd_bit;
457 pg_writel(reg, pingroups[pg].pupd_bank, pingroups[pg].pupd_reg);
459 spin_unlock_irqrestore(&mux_lock, flags);
464 static void tegra_pinmux_config_pingroup(const struct tegra_pingroup_config *config)
466 int pingroup = config->pingroup;
467 enum tegra_mux_func func = config->func;
468 enum tegra_pullupdown pupd = config->pupd;
469 enum tegra_tristate tristate = config->tristate;
470 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
471 enum tegra_pin_lock lock = config->lock;
472 enum tegra_pin_od od = config->od;
473 enum tegra_pin_ioreset ioreset = config->ioreset;
477 if (pingroups[pingroup].mux_reg > 0) {
478 err = tegra_pinmux_set_func(config);
480 pr_err("pinmux: can't set pingroup %s func to %s: %d\n",
481 pingroup_name(pingroup), func_name(func), err);
484 if (pingroups[pingroup].pupd_reg > 0) {
485 err = tegra_pinmux_set_pullupdown(pingroup, pupd);
487 pr_err("pinmux: can't set pingroup %s pullupdown to %s: %d\n",
488 pingroup_name(pingroup), pupd_name(pupd), err);
491 if (pingroups[pingroup].tri_reg > 0) {
492 err = tegra_pinmux_set_tristate(pingroup, tristate);
494 pr_err("pinmux: can't set pingroup %s tristate to %s: %d\n",
495 pingroup_name(pingroup), tri_name(func), err);
498 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
499 if (pingroups[pingroup].mux_reg > 0) {
500 err = tegra_pinmux_set_lock(pingroup, lock);
502 pr_err("pinmux: can't set pingroup %s lock to %s: %d\n",
503 pingroup_name(pingroup), lock_name(func), err);
506 if (pingroups[pingroup].mux_reg > 0) {
507 err = tegra_pinmux_set_od(pingroup, od);
509 pr_err("pinmux: can't set pingroup %s od to %s: %d\n",
510 pingroup_name(pingroup), od_name(func), err);
513 if (pingroups[pingroup].mux_reg > 0) {
514 err = tegra_pinmux_set_ioreset(pingroup, ioreset);
516 pr_err("pinmux: can't set pingroup %s ioreset to %s: %d\n",
517 pingroup_name(pingroup), ioreset_name(func), err);
522 void tegra_pinmux_config_table(const struct tegra_pingroup_config *config, int len)
526 for (i = 0; i < len; i++)
527 tegra_pinmux_config_pingroup(&config[i]);
529 EXPORT_SYMBOL(tegra_pinmux_config_table);
531 static const char *drive_pinmux_name(int pg)
533 if (pg < 0 || pg >= drive_max)
536 return drive_pingroups[pg].name;
539 static const char *enable_name(unsigned long val)
541 return val ? "ENABLE" : "DISABLE";
544 static const char *drive_name(unsigned long val)
546 if (val >= TEGRA_MAX_DRIVE)
549 return tegra_drive_names[val];
552 static const char *slew_name(unsigned long val)
554 if (val >= TEGRA_MAX_SLEW)
557 return tegra_slew_names[val];
560 static int tegra_drive_pinmux_set_hsm(int pg, enum tegra_hsm hsm)
564 if (pg < 0 || pg >= drive_max)
567 if (hsm != TEGRA_HSM_ENABLE && hsm != TEGRA_HSM_DISABLE)
570 spin_lock_irqsave(&mux_lock, flags);
572 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
573 if (hsm == TEGRA_HSM_ENABLE)
577 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
579 spin_unlock_irqrestore(&mux_lock, flags);
584 static int tegra_drive_pinmux_set_schmitt(int pg, enum tegra_schmitt schmitt)
588 if (pg < 0 || pg >= drive_max)
591 if (schmitt != TEGRA_SCHMITT_ENABLE && schmitt != TEGRA_SCHMITT_DISABLE)
594 spin_lock_irqsave(&mux_lock, flags);
596 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
597 if (schmitt == TEGRA_SCHMITT_ENABLE)
601 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
603 spin_unlock_irqrestore(&mux_lock, flags);
608 static int tegra_drive_pinmux_set_drive(int pg, enum tegra_drive drive)
612 if (pg < 0 || pg >= drive_max)
615 if (drive < 0 || drive >= TEGRA_MAX_DRIVE)
618 spin_lock_irqsave(&mux_lock, flags);
620 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
623 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
625 spin_unlock_irqrestore(&mux_lock, flags);
630 static int tegra_drive_pinmux_set_pull_down(int pg,
631 enum tegra_pull_strength pull_down)
636 if (pg < 0 || pg >= drive_max)
639 if (pull_down < 0 || pull_down >= TEGRA_MAX_PULL)
642 spin_lock_irqsave(&mux_lock, flags);
644 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
645 reg &= ~(drive_pingroups[pg].drvdown_mask <<
646 drive_pingroups[pg].drvdown_offset);
647 reg |= pull_down << drive_pingroups[pg].drvdown_offset;
648 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
650 spin_unlock_irqrestore(&mux_lock, flags);
655 static int tegra_drive_pinmux_set_pull_up(int pg,
656 enum tegra_pull_strength pull_up)
661 if (pg < 0 || pg >= drive_max)
664 if (pull_up < 0 || pull_up >= TEGRA_MAX_PULL)
667 spin_lock_irqsave(&mux_lock, flags);
669 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
670 reg &= ~(drive_pingroups[pg].drvup_mask <<
671 drive_pingroups[pg].drvup_offset);
672 reg |= pull_up << drive_pingroups[pg].drvup_offset;
673 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
675 spin_unlock_irqrestore(&mux_lock, flags);
680 static int tegra_drive_pinmux_set_slew_rising(int pg,
681 enum tegra_slew slew_rising)
685 if (pg < 0 || pg >= drive_max)
688 if (slew_rising < 0 || slew_rising >= TEGRA_MAX_SLEW)
691 spin_lock_irqsave(&mux_lock, flags);
693 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
694 reg &= ~(drive_pingroups[pg].slewrise_mask <<
695 drive_pingroups[pg].slewrise_offset);
696 reg |= slew_rising << drive_pingroups[pg].slewrise_offset;
697 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
699 spin_unlock_irqrestore(&mux_lock, flags);
704 static int tegra_drive_pinmux_set_slew_falling(int pg,
705 enum tegra_slew slew_falling)
709 if (pg < 0 || pg >= drive_max)
712 if (slew_falling < 0 || slew_falling >= TEGRA_MAX_SLEW)
715 spin_lock_irqsave(&mux_lock, flags);
717 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
718 reg &= ~(drive_pingroups[pg].slewfall_mask <<
719 drive_pingroups[pg].slewfall_offset);
720 reg |= slew_falling << drive_pingroups[pg].slewfall_offset;
721 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
723 spin_unlock_irqrestore(&mux_lock, flags);
728 static void tegra_drive_pinmux_config_pingroup(int pingroup,
730 enum tegra_schmitt schmitt,
731 enum tegra_drive drive,
732 enum tegra_pull_strength pull_down,
733 enum tegra_pull_strength pull_up,
734 enum tegra_slew slew_rising,
735 enum tegra_slew slew_falling)
739 err = tegra_drive_pinmux_set_hsm(pingroup, hsm);
741 pr_err("pinmux: can't set pingroup %s hsm to %s: %d\n",
742 drive_pinmux_name(pingroup),
743 enable_name(hsm), err);
745 err = tegra_drive_pinmux_set_schmitt(pingroup, schmitt);
747 pr_err("pinmux: can't set pingroup %s schmitt to %s: %d\n",
748 drive_pinmux_name(pingroup),
749 enable_name(schmitt), err);
751 err = tegra_drive_pinmux_set_drive(pingroup, drive);
753 pr_err("pinmux: can't set pingroup %s drive to %s: %d\n",
754 drive_pinmux_name(pingroup),
755 drive_name(drive), err);
757 err = tegra_drive_pinmux_set_pull_down(pingroup, pull_down);
759 pr_err("pinmux: can't set pingroup %s pull down to %d: %d\n",
760 drive_pinmux_name(pingroup),
763 err = tegra_drive_pinmux_set_pull_up(pingroup, pull_up);
765 pr_err("pinmux: can't set pingroup %s pull up to %d: %d\n",
766 drive_pinmux_name(pingroup),
769 err = tegra_drive_pinmux_set_slew_rising(pingroup, slew_rising);
771 pr_err("pinmux: can't set pingroup %s rising slew to %s: %d\n",
772 drive_pinmux_name(pingroup),
773 slew_name(slew_rising), err);
775 err = tegra_drive_pinmux_set_slew_falling(pingroup, slew_falling);
777 pr_err("pinmux: can't set pingroup %s falling slew to %s: %d\n",
778 drive_pinmux_name(pingroup),
779 slew_name(slew_falling), err);
782 void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
787 for (i = 0; i < len; i++)
788 tegra_drive_pinmux_config_pingroup(config[i].pingroup,
794 config[i].slew_rising,
795 config[i].slew_falling);
798 void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config,
802 struct tegra_pingroup_config c;
804 for (i = 0; i < len; i++) {
807 if (c.pingroup < 0 || c.pingroup >= pingroup_max) {
811 c.func = pingroups[c.pingroup].func_safe;
812 err = tegra_pinmux_set_func(&c);
814 pr_err("%s: tegra_pinmux_set_func returned %d setting "
815 "%s to %s\n", __func__, err,
816 pingroup_name(c.pingroup), func_name(c.func));
820 void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config,
825 for (i = 0; i < len; i++) {
827 if (config[i].pingroup < 0 ||
828 config[i].pingroup >= pingroup_max) {
832 err = tegra_pinmux_set_func(&config[i]);
834 pr_err("%s: tegra_pinmux_set_func returned %d setting "
835 "%s to %s\n", __func__, err,
836 pingroup_name(config[i].pingroup),
837 func_name(config[i].func));
841 void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config,
842 int len, enum tegra_tristate tristate)
848 for (i = 0; i < len; i++) {
849 pingroup = config[i].pingroup;
850 if (pingroups[pingroup].tri_reg > 0) {
851 err = tegra_pinmux_set_tristate(pingroup, tristate);
853 pr_err("pinmux: can't set pingroup %s tristate"
854 " to %s: %d\n", pingroup_name(pingroup),
855 tri_name(tristate), err);
860 void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
861 int len, enum tegra_pullupdown pupd)
867 for (i = 0; i < len; i++) {
868 pingroup = config[i].pingroup;
869 if (pingroups[pingroup].pupd_reg > 0) {
870 err = tegra_pinmux_set_pullupdown(pingroup, pupd);
872 pr_err("pinmux: can't set pingroup %s pullupdown"
873 " to %s: %d\n", pingroup_name(pingroup),
874 pupd_name(pupd), err);
879 static struct of_device_id tegra_pinmux_of_match[] __devinitdata = {
880 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
881 { .compatible = "nvidia,tegra20-pinmux", tegra20_pinmux_init },
883 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
884 { .compatible = "nvidia,tegra30-pinmux", tegra30_pinmux_init },
889 static int __devinit tegra_pinmux_probe(struct platform_device *pdev)
891 struct resource *res;
894 const struct of_device_id *match;
896 match = of_match_device(tegra_pinmux_of_match, &pdev->dev);
899 ((pinmux_init)(match->data))(&pingroups, &pingroup_max,
900 &drive_pingroups, &drive_max, &gpio_to_pingroups_map,
901 &gpio_to_pingroups_max);
902 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
904 /* no device tree available, so we must be on tegra20 */
905 tegra20_pinmux_init(&pingroups, &pingroup_max,
906 &drive_pingroups, &drive_max);
908 pr_warn("non Tegra20 platform requires pinmux devicetree node\n");
912 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
918 for (i = 0; i < pingroup_max; i++) {
919 if (pingroups[i].tri_bank >= nbanks) {
920 dev_err(&pdev->dev, "pingroup %d: bad tri_bank\n", i);
924 if (pingroups[i].mux_bank >= nbanks) {
925 dev_err(&pdev->dev, "pingroup %d: bad mux_bank\n", i);
929 if (pingroups[i].pupd_bank >= nbanks) {
930 dev_err(&pdev->dev, "pingroup %d: bad pupd_bank\n", i);
935 for (i = 0; i < drive_max; i++) {
936 if (drive_pingroups[i].reg_bank >= nbanks) {
938 "drive pingroup %d: bad reg_bank\n", i);
946 regs = devm_kzalloc(&pdev->dev, nbanks * sizeof(*regs), GFP_KERNEL);
948 dev_err(&pdev->dev, "Can't alloc regs pointer\n");
952 for (i = 0; i < nbanks; i++) {
953 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
955 dev_err(&pdev->dev, "Missing MEM resource\n");
959 if (!devm_request_mem_region(&pdev->dev, res->start,
961 dev_name(&pdev->dev))) {
963 "Couldn't request MEM resource %d\n", i);
967 regs[i] = devm_ioremap(&pdev->dev, res->start,
970 dev_err(&pdev->dev, "Couldn't ioremap regs %d\n", i);
978 static struct platform_driver tegra_pinmux_driver = {
980 .name = "tegra-pinmux",
981 .owner = THIS_MODULE,
982 .of_match_table = tegra_pinmux_of_match,
984 .probe = tegra_pinmux_probe,
987 static int __init tegra_pinmux_init(void)
989 return platform_driver_register(&tegra_pinmux_driver);
991 postcore_initcall(tegra_pinmux_init);
993 #ifdef CONFIG_DEBUG_FS
995 #include <linux/debugfs.h>
996 #include <linux/seq_file.h>
998 static void dbg_pad_field(struct seq_file *s, int len)
1006 static int dbg_pinmux_show(struct seq_file *s, void *unused)
1011 for (i = 0; i < pingroup_max; i++) {
1017 seq_printf(s, "\t{TEGRA_PINGROUP_%s", pingroups[i].name);
1018 len = strlen(pingroups[i].name);
1019 dbg_pad_field(s, 15 - len);
1021 if (pingroups[i].mux_reg <= 0) {
1022 seq_printf(s, "TEGRA_MUX_NONE");
1023 len = strlen("NONE");
1025 reg = pg_readl(pingroups[i].mux_bank,
1026 pingroups[i].mux_reg);
1027 mux = (reg >> pingroups[i].mux_bit) & 0x3;
1028 BUG_ON(pingroups[i].funcs[mux] == 0);
1029 if (pingroups[i].funcs[mux] == TEGRA_MUX_INVALID) {
1030 seq_printf(s, "TEGRA_MUX_INVALID");
1032 } else if (pingroups[i].funcs[mux] & TEGRA_MUX_RSVD) {
1033 seq_printf(s, "TEGRA_MUX_RSVD%1lu", mux+1);
1036 BUG_ON(!tegra_mux_names[pingroups[i].funcs[mux]]);
1037 seq_printf(s, "TEGRA_MUX_%s",
1038 tegra_mux_names[pingroups[i].funcs[mux]]);
1039 len = strlen(tegra_mux_names[pingroups[i].funcs[mux]]);
1042 dbg_pad_field(s, 13-len);
1044 #if defined(TEGRA_PINMUX_HAS_IO_DIRECTION)
1047 io = (pg_readl(pingroups[i].mux_bank,
1048 pingroups[i].mux_reg) >> 5) & 0x1;
1049 seq_printf(s, "TEGRA_PIN_%s", io_name(io));
1050 len = strlen(io_name(io));
1051 dbg_pad_field(s, 6 - len);
1054 if (pingroups[i].pupd_reg <= 0) {
1055 seq_printf(s, "TEGRA_PUPD_NORMAL");
1056 len = strlen("NORMAL");
1058 reg = pg_readl(pingroups[i].pupd_bank,
1059 pingroups[i].pupd_reg);
1060 pupd = (reg >> pingroups[i].pupd_bit) & 0x3;
1061 seq_printf(s, "TEGRA_PUPD_%s", pupd_name(pupd));
1062 len = strlen(pupd_name(pupd));
1064 dbg_pad_field(s, 9 - len);
1066 if (pingroups[i].tri_reg <= 0) {
1067 seq_printf(s, "TEGRA_TRI_NORMAL");
1069 reg = pg_readl(pingroups[i].tri_bank,
1070 pingroups[i].tri_reg);
1071 tri = (reg >> pingroups[i].tri_bit) & 0x1;
1073 seq_printf(s, "TEGRA_TRI_%s", tri_name(tri));
1075 seq_printf(s, "},\n");
1080 static int dbg_pinmux_open(struct inode *inode, struct file *file)
1082 return single_open(file, dbg_pinmux_show, &inode->i_private);
1085 static const struct file_operations debug_fops = {
1086 .open = dbg_pinmux_open,
1088 .llseek = seq_lseek,
1089 .release = single_release,
1092 static int dbg_drive_pinmux_show(struct seq_file *s, void *unused)
1098 for (i = 0; i < drive_max; i++) {
1101 seq_printf(s, "\t{TEGRA_DRIVE_PINGROUP_%s",
1102 drive_pingroups[i].name);
1103 len = strlen(drive_pingroups[i].name);
1104 dbg_pad_field(s, 7 - len);
1107 reg = pg_readl(drive_pingroups[i].reg_bank,
1108 drive_pingroups[i].reg);
1110 seq_printf(s, "TEGRA_HSM_ENABLE");
1113 seq_printf(s, "TEGRA_HSM_DISABLE");
1116 dbg_pad_field(s, 17 - len);
1118 if (SCHMT_EN(reg)) {
1119 seq_printf(s, "TEGRA_SCHMITT_ENABLE");
1122 seq_printf(s, "TEGRA_SCHMITT_DISABLE");
1125 dbg_pad_field(s, 22 - len);
1127 seq_printf(s, "TEGRA_DRIVE_%s", drive_name(LPMD(reg)));
1128 len = strlen(drive_name(LPMD(reg)));
1129 dbg_pad_field(s, 5 - len);
1131 offset = drive_pingroups[i].drvdown_offset;
1132 seq_printf(s, "TEGRA_PULL_%d", DRVDN(reg, offset));
1133 len = DRVDN(reg, offset) < 10 ? 1 : 2;
1134 dbg_pad_field(s, 2 - len);
1136 offset = drive_pingroups[i].drvup_offset;
1137 seq_printf(s, "TEGRA_PULL_%d", DRVUP(reg, offset));
1138 len = DRVUP(reg, offset) < 10 ? 1 : 2;
1139 dbg_pad_field(s, 2 - len);
1141 offset = drive_pingroups[i].slewrise_offset;
1142 seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWR(reg, offset)));
1143 len = strlen(slew_name(SLWR(reg, offset)));
1144 dbg_pad_field(s, 7 - len);
1146 offset= drive_pingroups[i].slewfall_offset;
1147 seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWF(reg, offset)));
1149 seq_printf(s, "},\n");
1154 static int dbg_drive_pinmux_open(struct inode *inode, struct file *file)
1156 return single_open(file, dbg_drive_pinmux_show, &inode->i_private);
1159 static const struct file_operations debug_drive_fops = {
1160 .open = dbg_drive_pinmux_open,
1162 .llseek = seq_lseek,
1163 .release = single_release,
1166 static int __init tegra_pinmux_debuginit(void)
1168 (void) debugfs_create_file("tegra_pinmux", S_IRUGO,
1169 NULL, NULL, &debug_fops);
1170 (void) debugfs_create_file("tegra_pinmux_drive", S_IRUGO,
1171 NULL, NULL, &debug_drive_fops);
1174 late_initcall(tegra_pinmux_debuginit);