ARM: tegra3: convert to CONFIG_MULTI_IRQ_HANDLER
[linux-2.6.git] / arch / arm / mach-tegra / p852 / board-p852.c
1 /*
2  * arch/arm/mach-tegra/board-p852.c
3  *
4  * Copyright (c) 2010-2011, NVIDIA Corporation.
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17 #include "board-p852.h"
18 #include <mach/spdif.h>
19
20 unsigned int p852_sku_peripherals;
21 unsigned int p852_spi_peripherals;
22 unsigned int p852_i2s_peripherals;
23 unsigned int p852_uart_peripherals;
24 unsigned int p852_i2c_peripherals;
25 unsigned int p852_sdhci_peripherals;
26 unsigned int p852_display_peripherals;
27
28 /* If enable_usb3 can have two options ehci3=eth or usb*/
29 static char enable_usb3[4];
30
31 int __init parse_enable_usb3(char *arg)
32 {
33         if (!arg)
34                 return 0;
35
36         strncpy(enable_usb3, arg, sizeof(enable_usb3));
37         return 0;
38 }
39
40 early_param("ehci3", parse_enable_usb3);
41
42 static __initdata struct tegra_clk_init_table p852_clk_init_table[] = {
43         /* name         parent          rate       enabled */
44         {"uarta",       "pll_p",      216000000,    true},
45         {"uartb",       "pll_p",      216000000,    true},
46         {"uartc",       "pll_p",      216000000,    true},
47         {"uartd",       "pll_p",      216000000,    true},
48         {"pll_m_out1",  "pll_m",      240000000,    true},
49         {"pll_p_out4",  "pll_p",      240000000,    true},
50         {"host1x",      "pll_p",      166000000,    true},
51         {"disp1",       "pll_p",      216000000,    true},
52         {"vi",          "pll_m",      100000000,    true},
53         {"csus",        "clk_m",      12000000,     true},
54         {"emc",         "pll_m",      600000000,    true},
55         {"pll_c",       "clk_m",      600000000,    true},
56         {"pll_c_out1",  "pll_c",      240000000,    true},
57         {"pwm",         "clk_32k",    32768,        false},
58         {"clk_32k",     NULL,         32768,        true},
59         {"pll_a",       NULL,         56448000,     true},
60         {"pll_a_out0",  "pll_a",      11289600,     true},
61         {"audio",       "pll_a_out0", 11289600,     true},
62         {"audio_2x",    "audio",      22579200,     false},
63         {"vde",         "pll_c",      240000000,    false},
64         {"vi_sensor",   "pll_m",      111000000,    true},
65         {"epp",         "pll_m",      111000000,    true},
66         {"mpe",         "pll_m",      111000000,    true},
67         {"i2s1",        "pll_a_out0", 11289600,     true},
68         {"i2s2",        "pll_a_out0", 11289600,     true},
69         {"ndflash",     "pll_p",      86500000,     true},
70         {"sbc1",        "pll_p",      12000000,     false},
71         {"spdif_in",    "pll_m",      22579000,     true},
72         {"spdif_out",   "pll_a_out0", 5644800,      true},
73         {"sbc2",        "pll_p",      12000000,     false},
74         {"sbc3",        "pll_p",      12000000,     false},
75         {"sbc4",        "pll_p",      12000000,     false},
76         {"nor",         "pll_p",      86500000,     true},
77         {NULL,          NULL,         0,            0},
78 };
79
80 static struct tegra_nand_chip_parms nand_chip_parms[] = {
81         /* Micron 29F4G08ABADA */
82         [0] = {
83                .vendor_id = 0x2C,
84                .device_id = 0xDC,
85                .capacity = 512,
86                .read_id_fourth_byte = 0x95,
87                .timing = {
88                           .trp = 1,
89                           .trh = 1,
90                           .twp = 12,
91                           .twh = 12,
92                           .tcs = 24,
93                           .twhr = 58,
94                           .tcr_tar_trr = 12,
95                           .twb = 116,
96                           .trp_resp = 24,
97                           .tadl = 24,
98                           },
99                },
100         /* Micron 29F4G16ABADA */
101         [1] = {
102                .vendor_id = 0x2C,
103                .device_id = 0xCC,
104                .capacity = 512,
105                .read_id_fourth_byte = 0xD5,
106                .timing = {
107                           .trp = 10,
108                           .trh = 7,
109                           .twp = 10,
110                           .twh = 7,
111                           .tcs = 15,
112                           .twhr = 60,
113                           .tcr_tar_trr = 20,
114                           .twb = 100,
115                           .trp_resp = 20,
116                           .tadl = 70,
117                           },
118                },
119         /* Hynix HY27UF084G2B */
120         [2] = {
121                .vendor_id = 0xAD,
122                .device_id = 0xDC,
123                .read_id_fourth_byte = 0x95,
124                .capacity = 512,
125                .timing = {
126                           .trp = 12,
127                           .trh = 1,
128                           .twp = 12,
129                           .twh = 0,
130                           .tcs = 24,
131                           .twhr = 58,
132                           .tcr_tar_trr = 0,
133                           .twb = 116,
134                           .trp_resp = 24,
135                           .tadl = 24,
136                           },
137                },
138 };
139
140 struct tegra_nand_platform p852_nand_data = {
141         .max_chips = 8,
142         .chip_parms = nand_chip_parms,
143         .nr_chip_parms = ARRAY_SIZE(nand_chip_parms),
144         .wp_gpio = TEGRA_GPIO_PC7,
145 };
146
147 static struct resource resources_nand[] = {
148         [0] = {
149                .start = INT_NANDFLASH,
150                .end = INT_NANDFLASH,
151                .flags = IORESOURCE_IRQ,
152                },
153 };
154
155 static struct platform_device p852_nand_device = {
156         .name = "tegra_nand",
157         .id = -1,
158         .num_resources = ARRAY_SIZE(resources_nand),
159         .resource = resources_nand,
160         .dev = {
161                 .platform_data = &p852_nand_data,
162                 },
163 };
164
165 unsigned int p852_uart_irqs[] = {
166         INT_UARTA,
167         INT_UARTB,
168         INT_UARTC,
169         INT_UARTD,
170 };
171
172 unsigned int p852_uart_bases[] = {
173         TEGRA_UARTA_BASE,
174         TEGRA_UARTB_BASE,
175         TEGRA_UARTC_BASE,
176         TEGRA_UARTD_BASE,
177 };
178
179 static struct platform_device *p852_spi_devices[] __initdata = {
180         &tegra_spi_device1,
181         &tegra_spi_device2,
182         &tegra_spi_device3,
183         &tegra_spi_device4,
184 };
185
186 static struct plat_serial8250_port debug_uart_platform_data[] = {
187         {
188          .flags = UPF_BOOT_AUTOCONF,
189          .iotype = UPIO_MEM,
190          .regshift = 2,
191          .uartclk = 216000000,
192          },
193         {
194          .flags = 0,
195          }
196 };
197
198 #define DEF_8250_PLATFORM_DATA(_base, _irq) {   \
199         .flags = UPF_BOOT_AUTOCONF,             \
200         .iotype = UPIO_MEM,                     \
201         .membase = IO_ADDRESS(_base),           \
202         .mapbase = _base,                       \
203         .irq = _irq,                            \
204         .regshift = 2,                          \
205         .uartclk = 216000000,                   \
206 }
207
208 static struct plat_serial8250_port tegra_8250_uarta_platform_data[] = {
209         DEF_8250_PLATFORM_DATA(TEGRA_UARTA_BASE, INT_UARTA),
210         {
211          .flags = 0,
212          }
213 };
214
215 static struct plat_serial8250_port tegra_8250_uartb_platform_data[] = {
216         DEF_8250_PLATFORM_DATA(TEGRA_UARTB_BASE, INT_UARTB),
217         {
218          .flags = 0,
219          }
220 };
221
222 static struct plat_serial8250_port tegra_8250_uartc_platform_data[] = {
223         DEF_8250_PLATFORM_DATA(TEGRA_UARTC_BASE, INT_UARTC),
224         {
225          .flags = 0,
226          }
227 };
228
229 static struct plat_serial8250_port tegra_8250_uartd_platform_data[] = {
230         DEF_8250_PLATFORM_DATA(TEGRA_UARTD_BASE, INT_UARTD),
231         {
232          .flags = 0,
233          }
234 };
235
236 static struct plat_serial8250_port tegra_8250_uarte_platform_data[] = {
237         DEF_8250_PLATFORM_DATA(TEGRA_UARTE_BASE, INT_UARTE),
238         {
239          .flags = 0,
240          }
241 };
242
243 struct platform_device tegra_8250_uarta_device = {
244         .name = "serial8250",
245         .id = PLAT8250_DEV_PLATFORM,
246         .dev = {
247                 .platform_data = tegra_8250_uarta_platform_data,
248                 },
249 };
250
251 struct platform_device tegra_8250_uartb_device = {
252         .name = "serial8250",
253         .id = PLAT8250_DEV_PLATFORM1,
254         .dev = {
255                 .platform_data = tegra_8250_uartb_platform_data,
256                 },
257 };
258
259 struct platform_device tegra_8250_uartc_device = {
260         .name = "serial8250",
261         .id = PLAT8250_DEV_PLATFORM2,
262         .dev = {
263                 .platform_data = tegra_8250_uartc_platform_data,
264                 },
265 };
266
267 struct platform_device tegra_8250_uartd_device = {
268         .name = "serial8250",
269         .id = PLAT8250_DEV_FOURPORT,
270         .dev = {
271                 .platform_data = tegra_8250_uartd_platform_data,
272                 },
273 };
274
275 struct platform_device tegra_8250_uarte_device = {
276         .name = "serial8250",
277         .id = PLAT8250_DEV_ACCENT,
278         .dev = {
279                 .platform_data = tegra_8250_uarte_platform_data,
280                 },
281 };
282
283 static struct platform_device debug_uart = {
284         .name = "serial8250",
285         .id = PLAT8250_DEV_PLATFORM,
286         .dev = {
287                 .platform_data = debug_uart_platform_data,
288                 },
289 };
290
291
292 static void p852_usb_gpio_config(void)
293 {
294         unsigned int usbeth_mux_gpio = 0, usb_ena_val;
295         unsigned int has_onboard_ethernet = 0;
296         unsigned int p852_eth_reset = TEGRA_GPIO_PD3;
297
298         switch (system_rev) {
299         case P852_SKU13_B00:
300         case P852_SKU23_B00:
301         case P852_SKU23_C01:
302         case P852_SKU8_B00:
303         case P852_SKU8_C01:
304         case P852_SKU9_B00:
305         case P852_SKU9_C01:
306                 {
307                         usbeth_mux_gpio = TEGRA_GPIO_PS3;
308                         has_onboard_ethernet = 1;
309                         usb_ena_val = 1;
310                 }
311                 break;
312         case P852_SKU5_B00:
313         case P852_SKU5_C01:
314                 {
315                         usb_ena_val = 1;
316                         has_onboard_ethernet = 0;
317                 }
318                 break;
319         case P852_SKU1:
320                 {
321                         has_onboard_ethernet = 0;
322                         usb_ena_val = 0;
323                         strncpy(enable_usb3, "usb", sizeof(enable_usb3));
324                 }
325                 break;
326         case P852_SKU1_B00:
327         case P852_SKU1_C0X:
328                 {
329                         has_onboard_ethernet = 0;
330                         usb_ena_val = 1;
331                         strncpy(enable_usb3, "usb", sizeof(enable_usb3));
332                 }
333                 break;
334         default:
335                 {
336                         usbeth_mux_gpio = TEGRA_GPIO_PD4;
337                         has_onboard_ethernet = 1;
338                         usb_ena_val = 0;
339                 }
340         }
341
342         if (has_onboard_ethernet) {
343                 gpio_request_one(usbeth_mux_gpio, GPIOF_OUT_INIT_LOW,
344                                  "eth_ena");
345                 tegra_gpio_enable(usbeth_mux_gpio);
346
347                 /* eth reset */
348                 gpio_request_one(p852_eth_reset, GPIOF_OUT_INIT_LOW,
349                                  "eth_reset");
350                 tegra_gpio_enable(p852_eth_reset);
351                 udelay(1);
352                 gpio_direction_output(p852_eth_reset, 1);
353
354                 if (!strcmp(enable_usb3, "eth"))
355                         gpio_direction_output(usbeth_mux_gpio, 1);
356
357                 /* exporting usbeth_mux_gpio */
358                 gpio_export(usbeth_mux_gpio, true);
359         }
360
361         if (!strcmp(enable_usb3, "usb")) {
362                 gpio_direction_output(TEGRA_GPIO_PB2, usb_ena_val);
363                 gpio_direction_output(TEGRA_GPIO_PW1, usb_ena_val);
364         }
365 }
366
367 static struct platform_device *p852_uart_devices[] __initdata = {
368         &tegra_uarta_device,
369         &tegra_uartb_device,
370         &tegra_uartc_device,
371         &tegra_uartd_device,
372 };
373
374 static struct platform_device *p852_8250_uart_devices[] __initdata = {
375         &tegra_8250_uarta_device,
376         &tegra_8250_uartb_device,
377         &tegra_8250_uartc_device,
378         &tegra_8250_uartd_device,
379         &tegra_8250_uarte_device,
380 };
381
382 static struct platform_device tegra_itu656 = {
383         .name = "tegra_itu656",
384         .id = -1,
385 };
386
387 static struct platform_device *p852_devices[] __initdata = {
388         &tegra_gart_device,
389         &tegra_avp_device,
390         &tegra_itu656,
391 };
392
393 static struct tegra_nor_platform_data p852_nor_data = {
394         .flash = {
395                 .map_name = "cfi_probe",
396                 .width = 2,
397         },
398         .chip_parms = {
399                 /* FIXME: use characterized clock freq */
400                 .timing_default = {
401                         .timing0 = 0xA0200253,
402                         .timing1 = 0x00040406,
403                 },
404                 .timing_read = {
405                         .timing0 = 0xA0200253,
406                         .timing1 = 0x00000A00,
407                 },
408         },
409 };
410
411 #ifdef CONFIG_TEGRA_SPI_I2S
412 struct spi_board_info tegra_spi_i2s_device __initdata = {
413         .modalias = "spi_i2s_pcm",
414         .bus_num = 2,
415         .chip_select = 2,
416         .mode = SPI_MODE_0,
417         .max_speed_hz = 18000000,
418         .platform_data = NULL,
419         .irq = 0,
420 };
421
422 void __init p852_spi_i2s_init(void)
423 {
424         struct tegra_spi_i2s_platform_data *pdata;
425
426         pdata = (struct tegra_spi_i2s_platform_data *)
427             tegra_spi_i2s_device.platform_data;
428         if (pdata->gpio_i2s.active_state) {
429                 gpio_request_one(pdata->gpio_i2s.gpio_no, GPIOF_OUT_INIT_LOW,
430                                  "i2s_cpld_dir1");
431         } else {
432                 gpio_request_one(pdata->gpio_i2s.gpio_no, GPIOF_OUT_INIT_HIGH,
433                                  "i2s_cpld_dir1");
434         }
435         tegra_gpio_enable(pdata->gpio_i2s.gpio_no);
436         if (pdata->gpio_spi.active_state) {
437                 gpio_request_one(pdata->gpio_spi.gpio_no, GPIOF_OUT_INIT_LOW,
438                                  "spi_cpld_dir2");
439         } else {
440                 gpio_request_one(pdata->gpio_spi.gpio_no, GPIOF_OUT_INIT_HIGH,
441                                  "spi_cpld_dir2");
442         }
443
444         tegra_gpio_enable(pdata->gpio_spi.gpio_no);
445         spi_register_board_info(&tegra_spi_i2s_device, 1);
446 }
447 #endif
448
449 #if defined(CONFIG_SPI_TEGRA) && defined(CONFIG_SPI_SPIDEV)
450 static struct spi_board_info tegra_spi_devices[] __initdata = {
451         {
452          .modalias = "spidev",
453          .bus_num = 0,
454          .chip_select = 0,
455          .mode = SPI_MODE_0,
456          .max_speed_hz = 18000000,
457          .platform_data = NULL,
458          .irq = 0,
459          },
460         {
461          .modalias = "spidev",
462          .bus_num = 1,
463          .chip_select = 1,
464          .mode = SPI_MODE_0,
465          .max_speed_hz = 18000000,
466          .platform_data = NULL,
467          .irq = 0,
468          },
469         {
470          .modalias = "spidev",
471          .bus_num = 3,
472          .chip_select = 1,
473          .mode = SPI_MODE_0,
474          .max_speed_hz = 18000000,
475          .platform_data = NULL,
476          .irq = 0,
477          },
478 };
479
480 static void __init p852_register_spidev(void)
481 {
482         spi_register_board_info(tegra_spi_devices,
483                                 ARRAY_SIZE(tegra_spi_devices));
484 }
485 #else
486 #define p852_register_spidev() do {} while (0)
487 #endif
488
489 /*
490   FixMe: Copied below GPIO value from Ventana board.
491   Plz correct it accordingly for embedded board usage
492 */
493 #define TEGRA_GPIO_PV1          169
494
495 static void ulpi_link_platform_open(void)
496 {
497         int reset_gpio = TEGRA_GPIO_PV1;
498
499         gpio_request(reset_gpio, "ulpi_phy_reset");
500         gpio_direction_output(reset_gpio, 0);
501         tegra_gpio_enable(reset_gpio);
502
503         gpio_direction_output(reset_gpio, 0);
504         msleep(5);
505         gpio_direction_output(reset_gpio, 1);
506 }
507
508 static struct tegra_usb_phy_platform_ops ulpi_link_plat_ops = {
509         .open = ulpi_link_platform_open,
510 };
511
512 static struct tegra_usb_platform_data tegra_ehci_ulpi_link_pdata = {
513         .port_otg = false,
514         .has_hostpc = false,
515         .phy_intf = TEGRA_USB_PHY_INTF_ULPI_LINK,
516         .op_mode        = TEGRA_USB_OPMODE_HOST,
517         .u_data.host = {
518                 .vbus_gpio = -1,
519                 .vbus_reg = NULL,
520                 .hot_plug = false,
521                 .remote_wakeup_supported = false,
522                 .power_off_on_suspend = false,
523         },
524         .u_cfg.ulpi = {
525                 .shadow_clk_delay = 10,
526                 .clock_out_delay = 1,
527                 .data_trimmer = 4,
528                 .stpdirnxt_trimmer = 4,
529                 .dir_trimmer = 4,
530                 .clk = "cdev2",
531         },
532         .ops = &ulpi_link_plat_ops,
533 };
534
535 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
536         .port_otg = false,
537         .has_hostpc = false,
538         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
539         .op_mode = TEGRA_USB_OPMODE_HOST,
540         .u_data.host = {
541                 .vbus_gpio = -1,
542                 .vbus_reg = NULL,
543                 .hot_plug = true,
544                 .remote_wakeup_supported = true,
545                 .power_off_on_suspend = false,
546         },
547         .u_cfg.utmi = {
548                .hssync_start_delay = 0,
549                .idle_wait_delay = 17,
550                .elastic_limit = 16,
551                .term_range_adj = 6,
552                .xcvr_setup = 15,
553                .xcvr_lsfslew = 2,
554                .xcvr_lsrslew = 2,
555         },
556 };
557
558 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
559         .port_otg = false,
560         .has_hostpc = false,
561         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
562         .op_mode = TEGRA_USB_OPMODE_HOST,
563         .u_data.host = {
564                 .vbus_gpio = -1,
565                 .vbus_reg = NULL,
566                 .hot_plug = true,
567                 .remote_wakeup_supported = true,
568                 .power_off_on_suspend = false,
569         },
570         .u_cfg.utmi = {
571                .hssync_start_delay = 0,
572                .idle_wait_delay = 17,
573                .elastic_limit = 16,
574                .term_range_adj = 6,
575                .xcvr_setup = 8,
576                .xcvr_lsfslew = 2,
577                .xcvr_lsrslew = 2,
578         },
579 };
580 static void __init p852_usb_init(void)
581 {
582
583         p852_usb_gpio_config();
584         /*
585            if (system_rev == P852_SKU8)
586            {
587            platform_device_register(&tegra_udc_device);
588            }
589            else
590          */
591         {
592                 tegra_ehci1_device.dev.platform_data = &tegra_ehci1_utmi_pdata;
593                 platform_device_register(&tegra_ehci1_device);
594         }
595
596         if (!(p852_sku_peripherals & P852_SKU_ULPI_DISABLE)) {
597                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_ulpi_link_pdata;
598                 platform_device_register(&tegra_ehci2_device);
599         }
600
601         tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
602         platform_device_register(&tegra_ehci3_device);
603 }
604
605 static void __init spi3_pingroup_clear_tristate(void)
606 {
607         /* spi3 mosi, miso, cs, clk */
608         tegra_pinmux_set_tristate(TEGRA_PINGROUP_LSDI, TEGRA_TRI_NORMAL);
609         tegra_pinmux_set_tristate(TEGRA_PINGROUP_LSDA, TEGRA_TRI_NORMAL);
610         tegra_pinmux_set_tristate(TEGRA_PINGROUP_LCSN, TEGRA_TRI_NORMAL);
611         tegra_pinmux_set_tristate(TEGRA_PINGROUP_LSCK, TEGRA_TRI_NORMAL);
612 }
613
614 static void __init p852_spi_init(void)
615 {
616         if (p852_sku_peripherals & P852_SKU_SPI_ENABLE) {
617                 int i = 0;
618                 unsigned int spi_config = 0;
619                 unsigned int spi3_config =
620                     (p852_spi_peripherals >> P852_SPI3_SHIFT) & P852_SPI_MASK;
621
622                 for (i = 0; i < P852_MAX_SPI; i++) {
623                         spi_config =
624                             (p852_spi_peripherals >> (P852_SPI_SHIFT * i)) &
625                             P852_SPI_MASK;
626                         if (spi_config & P852_SPI_ENABLE) {
627                                 if (spi_config & P852_SPI_SLAVE)
628                                         p852_spi_devices[i]->name =
629                                             "tegra_spi_slave";
630                                 platform_device_register(p852_spi_devices[i]);
631                         }
632                 }
633                 /* Default spi3 pingroups are in tristate */
634                 if (spi3_config & P852_SPI_ENABLE)
635                         spi3_pingroup_clear_tristate();
636         }
637 }
638
639 static void __init p852_uart_init(void)
640 {
641         if (p852_sku_peripherals & P852_SKU_UART_ENABLE) {
642                 int i = 0;
643                 unsigned int uart_config = 0, uart8250Id = 0;
644                 int debug_console = -1;
645
646                 /* register the debug console as the first serial console */
647                 for (i = 0; i < P852_MAX_UART; i++) {
648                         uart_config =
649                             (p852_uart_peripherals >> (P852_UART_SHIFT * i));
650                         if (uart_config & P852_UART_DB) {
651                                 debug_console = i;
652                                 debug_uart_platform_data[0].membase =
653                                     IO_ADDRESS(p852_uart_bases[i]);
654                                 debug_uart_platform_data[0].mapbase =
655                                     p852_uart_bases[i];
656                                 debug_uart_platform_data[0].irq =
657                                     p852_uart_irqs[i];
658                                 uart8250Id++;
659                                 platform_device_register(&debug_uart);
660                                 break;
661                         }
662                 }
663
664                 /* register remaining UARTS */
665                 for (i = 0; i < P852_MAX_UART; i++) {
666                         uart_config =
667                             (p852_uart_peripherals >> (P852_UART_SHIFT * i)) &
668                             P852_UART_MASK;
669                         if ((uart_config & P852_UART_ENABLE)
670                             && i != debug_console) {
671                                 if (uart_config & P852_UART_HS) {
672                                         platform_device_register
673                                             (p852_uart_devices[i]);
674                                 } else {
675                                         p852_8250_uart_devices[i]->id =
676                                             uart8250Id++;
677                                         platform_device_register
678                                             (p852_8250_uart_devices[i]);
679                                 }
680                         }
681                 }
682         }
683 }
684
685 static struct platform_device generic_codec_driver = {
686         .name = "generic-dit",
687 };
688
689 static void __init p852_flash_init(void)
690 {
691         if (p852_sku_peripherals & P852_SKU_NAND_ENABLE)
692                 platform_device_register(&p852_nand_device);
693
694         if (p852_sku_peripherals & P852_SKU_NOR_ENABLE) {
695                 tegra_nor_device.resource[2].end = TEGRA_NOR_FLASH_BASE + SZ_64M - 1;
696                 tegra_nor_device.dev.platform_data = &p852_nor_data;
697                 platform_device_register(&tegra_nor_device);
698         }
699 }
700
701 void __init p852_common_init(void)
702 {
703         tegra_clk_init_from_table(p852_clk_init_table);
704
705         p852_pinmux_init();
706
707         p852_i2c_init();
708
709         p852_regulator_init();
710
711         p852_uart_init();
712
713         p852_flash_init();
714
715         platform_add_devices(p852_devices, ARRAY_SIZE(p852_devices));
716
717         p852_panel_init();
718
719         p852_spi_init();
720
721         p852_register_spidev();
722
723         p852_usb_init();
724
725         p852_sdhci_init();
726
727         p852_gpio_init();
728 }
729
730 void __init tegra_p852_init(void)
731 {
732         switch (system_rev) {
733         case P852_SKU3:
734                 p852_sku3_init();
735                 break;
736         case P852_SKU13:
737                 p852_sku13_init();
738                 break;
739         case P852_SKU13_B00:
740         case P852_SKU13_C01:
741                 p852_sku13_b00_init();
742                 break;
743         case P852_SKU23:
744                 p852_sku23_init();
745                 break;
746         case P852_SKU23_B00:
747                 p852_sku23_b00_init();
748                 break;
749         case P852_SKU23_C01:
750                 p852_sku23_c01_init();
751                 break;
752         case P852_SKU1:
753                 p852_sku1_init();
754                 break;
755         case P852_SKU11:
756         case P852_SKU1_B00:
757                 p852_sku1_b00_init();
758                 break;
759         case P852_SKU1_C0X:
760                 p852_sku1_c0x_init();
761                 break;
762         case P852_SKU5_B00:
763                 p852_sku5_b00_init();
764                 break;
765         case P852_SKU5_C01:
766                 p852_sku5_c01_init();
767                 break;
768         case P852_SKU8_B00:
769                 p852_sku8_b00_init();
770                 break;
771         case P852_SKU8_C01:
772                 p852_sku8_c00_init();
773                 break;
774         case P852_SKU9_B00:
775                 p852_sku9_b00_init();
776                 break;
777         case P852_SKU9_C01:
778                 p852_sku9_c00_init();
779                 break;
780         default:
781                 printk(KERN_ERR "Unknow Board Revision\n");
782                 break;
783         }
784 }
785
786 static void __init tegra_p852_reserve(void)
787 {
788         switch (system_rev) {
789         case P852_SKU3:
790         case P852_SKU5_B00:
791         case P852_SKU5_C01:
792         case P852_SKU9_B00:
793         case P852_SKU9_C01:
794                 tegra_reserve(SZ_64M + SZ_16M, SZ_8M, 0);
795                 break;
796         default:
797                 tegra_reserve(SZ_128M, SZ_8M, 0);
798                 break;
799         }
800 }
801
802 MACHINE_START(P852, "Tegra P852")
803         .boot_params    = 0x00000100,
804         .map_io         = tegra_map_common_io,
805         .reserve        = tegra_p852_reserve,
806         .init_early     = tegra_init_early,
807         .init_irq       = tegra_init_irq,
808         .handle_irq     = gic_handle_irq,
809         .timer          = &tegra_timer,
810         .init_machine   = tegra_p852_init,
811 MACHINE_END