2 * arch/arm/mach-tegra/board-p852.c
4 * Copyright (c) 2010-2011, NVIDIA Corporation.
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include "board-p852.h"
18 #include <mach/spdif.h>
20 unsigned int p852_sku_peripherals;
21 unsigned int p852_spi_peripherals;
22 unsigned int p852_i2s_peripherals;
23 unsigned int p852_uart_peripherals;
24 unsigned int p852_i2c_peripherals;
25 unsigned int p852_sdhci_peripherals;
26 unsigned int p852_display_peripherals;
28 /* If enable_usb3 can have two options ehci3=eth or usb*/
29 static char enable_usb3[4];
31 int __init parse_enable_usb3(char *arg)
36 strncpy(enable_usb3, arg, sizeof(enable_usb3));
40 early_param("ehci3", parse_enable_usb3);
42 static __initdata struct tegra_clk_init_table p852_clk_init_table[] = {
43 /* name parent rate enabled */
44 {"uarta", "pll_p", 216000000, true},
45 {"uartb", "pll_p", 216000000, true},
46 {"uartc", "pll_p", 216000000, true},
47 {"uartd", "pll_p", 216000000, true},
48 {"pll_m_out1", "pll_m", 240000000, true},
49 {"pll_p_out4", "pll_p", 240000000, true},
50 {"host1x", "pll_p", 166000000, true},
51 {"disp1", "pll_p", 216000000, true},
52 {"vi", "pll_m", 100000000, true},
53 {"csus", "clk_m", 12000000, true},
54 {"emc", "pll_m", 600000000, true},
55 {"pll_c", "clk_m", 600000000, true},
56 {"pll_c_out1", "pll_c", 240000000, true},
57 {"pwm", "clk_32k", 32768, false},
58 {"clk_32k", NULL, 32768, true},
59 {"pll_a", NULL, 56448000, true},
60 {"pll_a_out0", "pll_a", 11289600, true},
61 {"audio", "pll_a_out0", 11289600, true},
62 {"audio_2x", "audio", 22579200, false},
63 {"vde", "pll_c", 240000000, false},
64 {"vi_sensor", "pll_m", 111000000, true},
65 {"epp", "pll_m", 111000000, true},
66 {"mpe", "pll_m", 111000000, true},
67 {"i2s1", "pll_a_out0", 11289600, true},
68 {"i2s2", "pll_a_out0", 11289600, true},
69 {"ndflash", "pll_p", 86500000, true},
70 {"sbc1", "pll_p", 12000000, false},
71 {"spdif_in", "pll_m", 22579000, true},
72 {"spdif_out", "pll_a_out0", 5644800, true},
73 {"sbc2", "pll_p", 12000000, false},
74 {"sbc3", "pll_p", 12000000, false},
75 {"sbc4", "pll_p", 12000000, false},
76 {"nor", "pll_p", 86500000, true},
80 static struct tegra_nand_chip_parms nand_chip_parms[] = {
81 /* Micron 29F4G08ABADA */
86 .read_id_fourth_byte = 0x95,
100 /* Micron 29F4G16ABADA */
105 .read_id_fourth_byte = 0xD5,
119 /* Hynix HY27UF084G2B */
123 .read_id_fourth_byte = 0x95,
140 struct tegra_nand_platform p852_nand_data = {
142 .chip_parms = nand_chip_parms,
143 .nr_chip_parms = ARRAY_SIZE(nand_chip_parms),
144 .wp_gpio = TEGRA_GPIO_PC7,
147 static struct resource resources_nand[] = {
149 .start = INT_NANDFLASH,
150 .end = INT_NANDFLASH,
151 .flags = IORESOURCE_IRQ,
155 static struct platform_device p852_nand_device = {
156 .name = "tegra_nand",
158 .num_resources = ARRAY_SIZE(resources_nand),
159 .resource = resources_nand,
161 .platform_data = &p852_nand_data,
165 unsigned int p852_uart_irqs[] = {
172 unsigned int p852_uart_bases[] = {
179 static struct platform_device *p852_spi_devices[] __initdata = {
186 static struct plat_serial8250_port debug_uart_platform_data[] = {
188 .flags = UPF_BOOT_AUTOCONF,
191 .uartclk = 216000000,
198 #define DEF_8250_PLATFORM_DATA(_base, _irq) { \
199 .flags = UPF_BOOT_AUTOCONF, \
200 .iotype = UPIO_MEM, \
201 .membase = IO_ADDRESS(_base), \
205 .uartclk = 216000000, \
208 static struct plat_serial8250_port tegra_8250_uarta_platform_data[] = {
209 DEF_8250_PLATFORM_DATA(TEGRA_UARTA_BASE, INT_UARTA),
215 static struct plat_serial8250_port tegra_8250_uartb_platform_data[] = {
216 DEF_8250_PLATFORM_DATA(TEGRA_UARTB_BASE, INT_UARTB),
222 static struct plat_serial8250_port tegra_8250_uartc_platform_data[] = {
223 DEF_8250_PLATFORM_DATA(TEGRA_UARTC_BASE, INT_UARTC),
229 static struct plat_serial8250_port tegra_8250_uartd_platform_data[] = {
230 DEF_8250_PLATFORM_DATA(TEGRA_UARTD_BASE, INT_UARTD),
236 static struct plat_serial8250_port tegra_8250_uarte_platform_data[] = {
237 DEF_8250_PLATFORM_DATA(TEGRA_UARTE_BASE, INT_UARTE),
243 struct platform_device tegra_8250_uarta_device = {
244 .name = "serial8250",
245 .id = PLAT8250_DEV_PLATFORM,
247 .platform_data = tegra_8250_uarta_platform_data,
251 struct platform_device tegra_8250_uartb_device = {
252 .name = "serial8250",
253 .id = PLAT8250_DEV_PLATFORM1,
255 .platform_data = tegra_8250_uartb_platform_data,
259 struct platform_device tegra_8250_uartc_device = {
260 .name = "serial8250",
261 .id = PLAT8250_DEV_PLATFORM2,
263 .platform_data = tegra_8250_uartc_platform_data,
267 struct platform_device tegra_8250_uartd_device = {
268 .name = "serial8250",
269 .id = PLAT8250_DEV_FOURPORT,
271 .platform_data = tegra_8250_uartd_platform_data,
275 struct platform_device tegra_8250_uarte_device = {
276 .name = "serial8250",
277 .id = PLAT8250_DEV_ACCENT,
279 .platform_data = tegra_8250_uarte_platform_data,
283 static struct platform_device debug_uart = {
284 .name = "serial8250",
285 .id = PLAT8250_DEV_PLATFORM,
287 .platform_data = debug_uart_platform_data,
292 static void p852_usb_gpio_config(void)
294 unsigned int usbeth_mux_gpio = 0, usb_ena_val;
295 unsigned int has_onboard_ethernet = 0;
296 unsigned int p852_eth_reset = TEGRA_GPIO_PD3;
298 switch (system_rev) {
307 usbeth_mux_gpio = TEGRA_GPIO_PS3;
308 has_onboard_ethernet = 1;
316 has_onboard_ethernet = 0;
321 has_onboard_ethernet = 0;
323 strncpy(enable_usb3, "usb", sizeof(enable_usb3));
329 has_onboard_ethernet = 0;
331 strncpy(enable_usb3, "usb", sizeof(enable_usb3));
336 usbeth_mux_gpio = TEGRA_GPIO_PD4;
337 has_onboard_ethernet = 1;
342 if (has_onboard_ethernet) {
343 gpio_request_one(usbeth_mux_gpio, GPIOF_OUT_INIT_LOW,
345 tegra_gpio_enable(usbeth_mux_gpio);
348 gpio_request_one(p852_eth_reset, GPIOF_OUT_INIT_LOW,
350 tegra_gpio_enable(p852_eth_reset);
352 gpio_direction_output(p852_eth_reset, 1);
354 if (!strcmp(enable_usb3, "eth"))
355 gpio_direction_output(usbeth_mux_gpio, 1);
357 /* exporting usbeth_mux_gpio */
358 gpio_export(usbeth_mux_gpio, true);
361 if (!strcmp(enable_usb3, "usb")) {
362 gpio_direction_output(TEGRA_GPIO_PB2, usb_ena_val);
363 gpio_direction_output(TEGRA_GPIO_PW1, usb_ena_val);
367 static struct platform_device *p852_uart_devices[] __initdata = {
374 static struct platform_device *p852_8250_uart_devices[] __initdata = {
375 &tegra_8250_uarta_device,
376 &tegra_8250_uartb_device,
377 &tegra_8250_uartc_device,
378 &tegra_8250_uartd_device,
379 &tegra_8250_uarte_device,
382 static struct platform_device tegra_itu656 = {
383 .name = "tegra_itu656",
387 static struct platform_device *p852_devices[] __initdata = {
393 static struct tegra_nor_platform_data p852_nor_data = {
395 .map_name = "cfi_probe",
399 /* FIXME: use characterized clock freq */
401 .timing0 = 0xA0200253,
402 .timing1 = 0x00040406,
405 .timing0 = 0xA0200253,
406 .timing1 = 0x00000A00,
411 #ifdef CONFIG_TEGRA_SPI_I2S
412 struct spi_board_info tegra_spi_i2s_device __initdata = {
413 .modalias = "spi_i2s_pcm",
417 .max_speed_hz = 18000000,
418 .platform_data = NULL,
422 void __init p852_spi_i2s_init(void)
424 struct tegra_spi_i2s_platform_data *pdata;
426 pdata = (struct tegra_spi_i2s_platform_data *)
427 tegra_spi_i2s_device.platform_data;
428 if (pdata->gpio_i2s.active_state) {
429 gpio_request_one(pdata->gpio_i2s.gpio_no, GPIOF_OUT_INIT_LOW,
432 gpio_request_one(pdata->gpio_i2s.gpio_no, GPIOF_OUT_INIT_HIGH,
435 tegra_gpio_enable(pdata->gpio_i2s.gpio_no);
436 if (pdata->gpio_spi.active_state) {
437 gpio_request_one(pdata->gpio_spi.gpio_no, GPIOF_OUT_INIT_LOW,
440 gpio_request_one(pdata->gpio_spi.gpio_no, GPIOF_OUT_INIT_HIGH,
444 tegra_gpio_enable(pdata->gpio_spi.gpio_no);
445 spi_register_board_info(&tegra_spi_i2s_device, 1);
449 #if defined(CONFIG_SPI_TEGRA) && defined(CONFIG_SPI_SPIDEV)
450 static struct spi_board_info tegra_spi_devices[] __initdata = {
452 .modalias = "spidev",
456 .max_speed_hz = 18000000,
457 .platform_data = NULL,
461 .modalias = "spidev",
465 .max_speed_hz = 18000000,
466 .platform_data = NULL,
470 .modalias = "spidev",
474 .max_speed_hz = 18000000,
475 .platform_data = NULL,
480 static void __init p852_register_spidev(void)
482 spi_register_board_info(tegra_spi_devices,
483 ARRAY_SIZE(tegra_spi_devices));
486 #define p852_register_spidev() do {} while (0)
490 FixMe: Copied below GPIO value from Ventana board.
491 Plz correct it accordingly for embedded board usage
493 #define TEGRA_GPIO_PV1 169
495 static void ulpi_link_platform_open(void)
497 int reset_gpio = TEGRA_GPIO_PV1;
499 gpio_request(reset_gpio, "ulpi_phy_reset");
500 gpio_direction_output(reset_gpio, 0);
501 tegra_gpio_enable(reset_gpio);
503 gpio_direction_output(reset_gpio, 0);
505 gpio_direction_output(reset_gpio, 1);
508 static struct tegra_usb_phy_platform_ops ulpi_link_plat_ops = {
509 .open = ulpi_link_platform_open,
512 static struct tegra_usb_platform_data tegra_ehci_ulpi_link_pdata = {
515 .phy_intf = TEGRA_USB_PHY_INTF_ULPI_LINK,
516 .op_mode = TEGRA_USB_OPMODE_HOST,
521 .remote_wakeup_supported = false,
522 .power_off_on_suspend = false,
525 .shadow_clk_delay = 10,
526 .clock_out_delay = 1,
528 .stpdirnxt_trimmer = 4,
532 .ops = &ulpi_link_plat_ops,
535 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
538 .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
539 .op_mode = TEGRA_USB_OPMODE_HOST,
544 .remote_wakeup_supported = true,
545 .power_off_on_suspend = false,
548 .hssync_start_delay = 0,
549 .idle_wait_delay = 17,
558 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
561 .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
562 .op_mode = TEGRA_USB_OPMODE_HOST,
567 .remote_wakeup_supported = true,
568 .power_off_on_suspend = false,
571 .hssync_start_delay = 0,
572 .idle_wait_delay = 17,
580 static void __init p852_usb_init(void)
583 p852_usb_gpio_config();
585 if (system_rev == P852_SKU8)
587 platform_device_register(&tegra_udc_device);
592 tegra_ehci1_device.dev.platform_data = &tegra_ehci1_utmi_pdata;
593 platform_device_register(&tegra_ehci1_device);
596 if (!(p852_sku_peripherals & P852_SKU_ULPI_DISABLE)) {
597 tegra_ehci2_device.dev.platform_data = &tegra_ehci_ulpi_link_pdata;
598 platform_device_register(&tegra_ehci2_device);
601 tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
602 platform_device_register(&tegra_ehci3_device);
605 static void __init spi3_pingroup_clear_tristate(void)
607 /* spi3 mosi, miso, cs, clk */
608 tegra_pinmux_set_tristate(TEGRA_PINGROUP_LSDI, TEGRA_TRI_NORMAL);
609 tegra_pinmux_set_tristate(TEGRA_PINGROUP_LSDA, TEGRA_TRI_NORMAL);
610 tegra_pinmux_set_tristate(TEGRA_PINGROUP_LCSN, TEGRA_TRI_NORMAL);
611 tegra_pinmux_set_tristate(TEGRA_PINGROUP_LSCK, TEGRA_TRI_NORMAL);
614 static void __init p852_spi_init(void)
616 if (p852_sku_peripherals & P852_SKU_SPI_ENABLE) {
618 unsigned int spi_config = 0;
619 unsigned int spi3_config =
620 (p852_spi_peripherals >> P852_SPI3_SHIFT) & P852_SPI_MASK;
622 for (i = 0; i < P852_MAX_SPI; i++) {
624 (p852_spi_peripherals >> (P852_SPI_SHIFT * i)) &
626 if (spi_config & P852_SPI_ENABLE) {
627 if (spi_config & P852_SPI_SLAVE)
628 p852_spi_devices[i]->name =
630 platform_device_register(p852_spi_devices[i]);
633 /* Default spi3 pingroups are in tristate */
634 if (spi3_config & P852_SPI_ENABLE)
635 spi3_pingroup_clear_tristate();
639 static void __init p852_uart_init(void)
641 if (p852_sku_peripherals & P852_SKU_UART_ENABLE) {
643 unsigned int uart_config = 0, uart8250Id = 0;
644 int debug_console = -1;
646 /* register the debug console as the first serial console */
647 for (i = 0; i < P852_MAX_UART; i++) {
649 (p852_uart_peripherals >> (P852_UART_SHIFT * i));
650 if (uart_config & P852_UART_DB) {
652 debug_uart_platform_data[0].membase =
653 IO_ADDRESS(p852_uart_bases[i]);
654 debug_uart_platform_data[0].mapbase =
656 debug_uart_platform_data[0].irq =
659 platform_device_register(&debug_uart);
664 /* register remaining UARTS */
665 for (i = 0; i < P852_MAX_UART; i++) {
667 (p852_uart_peripherals >> (P852_UART_SHIFT * i)) &
669 if ((uart_config & P852_UART_ENABLE)
670 && i != debug_console) {
671 if (uart_config & P852_UART_HS) {
672 platform_device_register
673 (p852_uart_devices[i]);
675 p852_8250_uart_devices[i]->id =
677 platform_device_register
678 (p852_8250_uart_devices[i]);
685 static struct platform_device generic_codec_driver = {
686 .name = "generic-dit",
689 static void __init p852_flash_init(void)
691 if (p852_sku_peripherals & P852_SKU_NAND_ENABLE)
692 platform_device_register(&p852_nand_device);
694 if (p852_sku_peripherals & P852_SKU_NOR_ENABLE) {
695 tegra_nor_device.resource[2].end = TEGRA_NOR_FLASH_BASE + SZ_64M - 1;
696 tegra_nor_device.dev.platform_data = &p852_nor_data;
697 platform_device_register(&tegra_nor_device);
701 void __init p852_common_init(void)
703 tegra_clk_init_from_table(p852_clk_init_table);
709 p852_regulator_init();
715 platform_add_devices(p852_devices, ARRAY_SIZE(p852_devices));
721 p852_register_spidev();
730 void __init tegra_p852_init(void)
732 switch (system_rev) {
741 p852_sku13_b00_init();
747 p852_sku23_b00_init();
750 p852_sku23_c01_init();
757 p852_sku1_b00_init();
760 p852_sku1_c0x_init();
763 p852_sku5_b00_init();
766 p852_sku5_c01_init();
769 p852_sku8_b00_init();
772 p852_sku8_c00_init();
775 p852_sku9_b00_init();
778 p852_sku9_c00_init();
781 printk(KERN_ERR "Unknow Board Revision\n");
786 static void __init tegra_p852_reserve(void)
788 switch (system_rev) {
794 tegra_reserve(SZ_64M + SZ_16M, SZ_8M, 0);
797 tegra_reserve(SZ_128M, SZ_8M, 0);
802 MACHINE_START(P852, "Tegra P852")
803 .boot_params = 0x00000100,
804 .map_io = tegra_map_common_io,
805 .reserve = tegra_p852_reserve,
806 .init_early = tegra_init_early,
807 .init_irq = tegra_init_irq,
808 .timer = &tegra_timer,
809 .init_machine = tegra_p852_init,