2 * arch/arm/mach-tegra/mc.c
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (C) 2011 NVIDIA Corporation
8 * Erik Gilling <konkers@google.com>
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
22 #include <linux/spinlock.h>
24 #include <mach/iomap.h>
27 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
28 static DEFINE_SPINLOCK(tegra_mc_lock);
30 void tegra_mc_set_priority(unsigned long client, unsigned long prio)
32 void __iomem *mc_base = IO_TO_VIRT(TEGRA_MC_BASE);
33 unsigned long reg = client >> 8;
34 int field = client & 0xff;
38 spin_lock_irqsave(&tegra_mc_lock, flags);
39 val = readl(mc_base + reg);
40 val &= ~(TEGRA_MC_PRIO_MASK << field);
42 writel(val, mc_base + reg);
43 spin_unlock_irqrestore(&tegra_mc_lock, flags);
47 int tegra_mc_get_tiled_memory_bandwidth_multiplier(void)
53 /* !!!FIXME!!! IMPLEMENT tegra_mc_set_priority() */
55 #include "tegra3_emc.h"
58 * If using T30/DDR3, the 2nd 16 bytes part of DDR3 atom is 2nd line and is
59 * discarded in tiling mode.
61 int tegra_mc_get_tiled_memory_bandwidth_multiplier(void)
65 type = tegra_emc_get_dram_type();
66 WARN_ONCE(type == -1, "unknown type DRAM because DVFS is disabled\n");
68 if (type == DRAM_TYPE_DDR3)