e7aeb8c794bebb6b3a0313061a7f076ebfad6bf6
[linux-2.6.git] / arch / arm / mach-tegra / include / mach / dc.h
1 /*
2  * arch/arm/mach-tegra/include/mach/dc.h
3  *
4  * Copyright (C) 2010 Google, Inc.
5  *
6  * Author:
7  *      Erik Gilling <konkers@google.com>
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #ifndef __MACH_TEGRA_DC_H
21 #define __MACH_TEGRA_DC_H
22
23 #include <linux/pm.h>
24
25 #define TEGRA_MAX_DC            2
26 #define DC_N_WINDOWS            3
27
28
29 /* DSI pixel data format */
30 enum {
31         TEGRA_DSI_PIXEL_FORMAT_16BIT_P,
32         TEGRA_DSI_PIXEL_FORMAT_18BIT_P,
33         TEGRA_DSI_PIXEL_FORMAT_18BIT_NP,
34         TEGRA_DSI_PIXEL_FORMAT_24BIT_P,
35 };
36
37 /* DSI virtual channel number */
38 enum {
39         TEGRA_DSI_VIRTUAL_CHANNEL_0,
40         TEGRA_DSI_VIRTUAL_CHANNEL_1,
41         TEGRA_DSI_VIRTUAL_CHANNEL_2,
42         TEGRA_DSI_VIRTUAL_CHANNEL_3,
43 };
44
45 /* DSI transmit method for video data */
46 enum {
47         TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE,
48         TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE,
49 };
50
51 /* DSI HS clock mode */
52 enum {
53         TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS,
54         TEGRA_DSI_VIDEO_CLOCK_TX_ONLY,
55 };
56
57 /* DSI burst mode setting in video mode */
58 enum {
59         TEGRA_DSI_VIDEO_NONE_BURST_MODE,
60         TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END,
61         TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED,
62         TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED,
63         TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED,
64         TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED,
65         TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED,
66         TEGRA_DSI_VIDEO_BURST_MODE_MANUAL,
67 };
68
69 enum {
70         TEGRA_DSI_PACKET_CMD,
71         TEGRA_DSI_DELAY_MS,
72 };
73
74 struct tegra_dsi_cmd {
75         u8      cmd_type;
76         u8      data_id;
77         union {
78                 u16 data_len;
79                 u16 delay_ms;
80                 struct{
81                         u8 data0;
82                         u8 data1;
83                 }sp;
84         }sp_len_dly;
85         u8      *pdata;
86 };
87
88 #define DSI_CMD_SHORT(di, p0, p1)       { \
89                                         .cmd_type = TEGRA_DSI_PACKET_CMD, \
90                                         .data_id = di, \
91                                         .sp_len_dly.sp.data0 = p0, \
92                                         .sp_len_dly.sp.data1 = p1, \
93                                         }
94 #define DSI_DLY_MS(ms)  { \
95                         .cmd_type = TEGRA_DSI_DELAY_MS, \
96                         .sp_len_dly.delay_ms = ms, \
97                         }
98
99 #define DSI_CMD_LONG(di, ptr)   { \
100                                 .cmd_type = TEGRA_DSI_PACKET_CMD, \
101                                 .data_id = di, \
102                                 .sp_len_dly.data_len = ARRAY_SIZE(ptr), \
103                                 .pdata = ptr, \
104                                 }
105
106 struct dsi_phy_timing_ns {
107         u16             t_hsdexit_ns;
108         u16             t_hstrail_ns;
109         u16             t_hsprepr_ns;
110         u16             t_datzero_ns;
111
112         u16             t_clktrail_ns;
113         u16             t_clkpost_ns;
114         u16             t_clkzero_ns;
115         u16             t_tlpx_ns;
116 };
117
118 struct tegra_dsi_out {
119         u8              n_data_lanes;                   /* required*/
120         u8              pixel_format;                   /* required*/
121         u8              refresh_rate;                   /* required*/
122         u8              virtual_channel;                /* required*/
123
124         bool            panel_has_frame_buffer; /* required*/
125
126         struct tegra_dsi_cmd*   dsi_init_cmd;           /* required*/
127         u16             n_init_cmd;                     /* required*/
128
129         u8              video_data_type;                /* required*/
130         u8              video_clock_mode;
131         u8              video_burst_mode;
132
133         u16             panel_buffer_size_byte;
134         u16             panel_reset_timeout_msec;
135
136         bool            hs_cmd_mode_supported;
137         bool            hs_cmd_mode_on_blank_supported;
138         bool            enable_hs_clock_on_lp_cmd_mode;
139
140         u32             max_panel_freq_khz;
141         u32             lp_cmd_mode_freq_khz;
142         u32             hs_clk_in_lp_cmd_mode_freq_khz;
143         u32             burst_mode_freq_khz;
144
145         struct dsi_phy_timing_ns phy_timing;
146 };
147
148 struct tegra_dc_mode {
149         int     pclk;
150         int     h_ref_to_sync;
151         int     v_ref_to_sync;
152         int     h_sync_width;
153         int     v_sync_width;
154         int     h_back_porch;
155         int     v_back_porch;
156         int     h_active;
157         int     v_active;
158         int     h_front_porch;
159         int     v_front_porch;
160         int     stereo_mode;
161         u32     flags;
162 };
163
164 #define TEGRA_DC_MODE_FLAG_NEG_V_SYNC   (1 << 0)
165 #define TEGRA_DC_MODE_FLAG_NEG_H_SYNC   (1 << 1)
166
167 enum {
168         TEGRA_DC_OUT_RGB,
169         TEGRA_DC_OUT_HDMI,
170         TEGRA_DC_OUT_DSI,
171 };
172
173 struct tegra_dc_out_pin {
174         int     name;
175         int     pol;
176 };
177
178 enum {
179         TEGRA_DC_OUT_PIN_DATA_ENABLE,
180         TEGRA_DC_OUT_PIN_H_SYNC,
181         TEGRA_DC_OUT_PIN_V_SYNC,
182         TEGRA_DC_OUT_PIN_PIXEL_CLOCK,
183 };
184
185 enum {
186         TEGRA_DC_OUT_PIN_POL_LOW,
187         TEGRA_DC_OUT_PIN_POL_HIGH,
188 };
189
190 enum {
191         TEGRA_DC_DISABLE_DITHER = 1,
192         TEGRA_DC_ORDERED_DITHER,
193         TEGRA_DC_ERRDIFF_DITHER,
194 };
195
196 enum {
197         TEGRA_PIN_OUT_CONFIG_SEL_LHP0_LD21,
198         TEGRA_PIN_OUT_CONFIG_SEL_LHP1_LD18,
199         TEGRA_PIN_OUT_CONFIG_SEL_LHP2_LD19,
200         TEGRA_PIN_OUT_CONFIG_SEL_LVP0_LVP0_Out,
201         TEGRA_PIN_OUT_CONFIG_SEL_LVP1_LD20,
202
203         TEGRA_PIN_OUT_CONFIG_SEL_LM1_M1,
204         TEGRA_PIN_OUT_CONFIG_SEL_LM1_LD21,
205         TEGRA_PIN_OUT_CONFIG_SEL_LM1_PM1,
206
207         TEGRA_PIN_OUT_CONFIG_SEL_LDI_LD22,
208         TEGRA_PIN_OUT_CONFIG_SEL_LPP_LD23,
209         TEGRA_PIN_OUT_CONFIG_SEL_LDC_SDC,
210         TEGRA_PIN_OUT_CONFIG_SEL_LSPI_DE,
211 };
212
213 struct tegra_dc_out {
214         int                     type;
215         unsigned                flags;
216
217         /* size in mm */
218         unsigned                h_size;
219         unsigned                v_size;
220
221         int                     dcc_bus;
222         int                     hotplug_gpio;
223
224         unsigned                order;
225         unsigned                align;
226         unsigned                depth;
227         unsigned                dither;
228
229         unsigned                height; /* mm */
230         unsigned                width; /* mm */
231
232         struct tegra_dc_mode    *modes;
233         int                     n_modes;
234
235         struct tegra_dsi_out    *dsi;
236
237         struct tegra_dc_out_pin *out_pins;
238         unsigned                n_out_pins;
239
240         u8                      *out_sel_configs;
241         unsigned                n_out_sel_configs;
242
243         int     (*enable)(void);
244         int     (*postpoweron)(void);
245         int     (*disable)(void);
246 };
247
248 /* bits for tegra_dc_out.flags */
249 #define TEGRA_DC_OUT_HOTPLUG_HIGH               (0 << 1)
250 #define TEGRA_DC_OUT_HOTPLUG_LOW                (1 << 1)
251 #define TEGRA_DC_OUT_HOTPLUG_MASK               (1 << 1)
252 #define TEGRA_DC_OUT_NVHDCP_POLICY_ALWAYS_ON    (0 << 2)
253 #define TEGRA_DC_OUT_NVHDCP_POLICY_ON_DEMAND    (1 << 2)
254 #define TEGRA_DC_OUT_NVHDCP_POLICY_MASK         (1 << 2)
255
256 #define TEGRA_DC_ALIGN_MSB              0
257 #define TEGRA_DC_ALIGN_LSB              1
258
259 #define TEGRA_DC_ORDER_RED_BLUE         0
260 #define TEGRA_DC_ORDER_BLUE_RED         1
261
262 struct tegra_dc;
263 struct nvmap_handle_ref;
264
265 struct tegra_dc_win {
266         u8                      idx;
267         u8                      fmt;
268         u32                     flags;
269
270         void                    *virt_addr;
271         dma_addr_t              phys_addr;
272         unsigned                offset;
273         unsigned                offset_u;
274         unsigned                offset_v;
275         unsigned                stride;
276         unsigned                stride_uv;
277         unsigned                x;
278         unsigned                y;
279         unsigned                w;
280         unsigned                h;
281         unsigned                out_x;
282         unsigned                out_y;
283         unsigned                out_w;
284         unsigned                out_h;
285         unsigned                z;
286
287         int                     dirty;
288         int                     underflows;
289         struct tegra_dc         *dc;
290
291         struct nvmap_handle_ref *cur_handle;
292 };
293
294
295 #define TEGRA_WIN_FLAG_ENABLED          (1 << 0)
296 #define TEGRA_WIN_FLAG_BLEND_PREMULT    (1 << 1)
297 #define TEGRA_WIN_FLAG_BLEND_COVERAGE   (1 << 2)
298 #define TEGRA_WIN_FLAG_INVERT_H         (1 << 3)
299 #define TEGRA_WIN_FLAG_INVERT_V         (1 << 4)
300 #define TEGRA_WIN_FLAG_TILED            (1 << 5)
301
302 #define TEGRA_WIN_BLEND_FLAGS_MASK \
303         (TEGRA_WIN_FLAG_BLEND_PREMULT | TEGRA_WIN_FLAG_BLEND_COVERAGE)
304
305 /* Note: These are the actual values written to the DC_WIN_COLOR_DEPTH register
306  * and may change in new tegra architectures.
307  */
308 #define TEGRA_WIN_FMT_P1                0
309 #define TEGRA_WIN_FMT_P2                1
310 #define TEGRA_WIN_FMT_P4                2
311 #define TEGRA_WIN_FMT_P8                3
312 #define TEGRA_WIN_FMT_B4G4R4A4          4
313 #define TEGRA_WIN_FMT_B5G5R5A           5
314 #define TEGRA_WIN_FMT_B5G6R5            6
315 #define TEGRA_WIN_FMT_AB5G5R5           7
316 #define TEGRA_WIN_FMT_B8G8R8A8          12
317 #define TEGRA_WIN_FMT_R8G8B8A8          13
318 #define TEGRA_WIN_FMT_B6x2G6x2R6x2A8    14
319 #define TEGRA_WIN_FMT_R6x2G6x2B6x2A8    15
320 #define TEGRA_WIN_FMT_YCbCr422          16
321 #define TEGRA_WIN_FMT_YUV422            17
322 #define TEGRA_WIN_FMT_YCbCr420P         18
323 #define TEGRA_WIN_FMT_YUV420P           19
324 #define TEGRA_WIN_FMT_YCbCr422P         20
325 #define TEGRA_WIN_FMT_YUV422P           21
326 #define TEGRA_WIN_FMT_YCbCr422R         22
327 #define TEGRA_WIN_FMT_YUV422R           23
328 #define TEGRA_WIN_FMT_YCbCr422RA        24
329 #define TEGRA_WIN_FMT_YUV422RA          25
330
331 struct tegra_fb_data {
332         int             win;
333
334         int             xres;
335         int             yres;
336         int             bits_per_pixel; /* -1 means autodetect */
337
338         unsigned long   flags;
339 };
340
341 #define TEGRA_FB_FLIP_ON_PROBE          (1 << 0)
342
343 struct tegra_dc_platform_data {
344         unsigned long           flags;
345         unsigned long           emc_clk_rate;
346         struct tegra_dc_out     *default_out;
347         struct tegra_fb_data    *fb;
348 };
349
350 #define TEGRA_DC_FLAG_ENABLED           (1 << 0)
351
352 struct tegra_dc *tegra_dc_get_dc(unsigned idx);
353 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win);
354
355 void tegra_dc_enable(struct tegra_dc *dc);
356 void tegra_dc_disable(struct tegra_dc *dc);
357
358 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc);
359 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc);
360 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, u32 val);
361
362 /* tegra_dc_update_windows and tegra_dc_sync_windows do not support windows
363  * with differenct dcs in one call
364  */
365 int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n);
366 int tegra_dc_sync_windows(struct tegra_dc_win *windows[], int n);
367
368 int tegra_dc_set_mode(struct tegra_dc *dc, const struct tegra_dc_mode *mode);
369 struct fb_videomode;
370 int tegra_dc_set_fb_mode(struct tegra_dc *dc, const struct fb_videomode *fbmode,
371         bool stereo_mode);
372
373 unsigned tegra_dc_get_out_height(struct tegra_dc *dc);
374 unsigned tegra_dc_get_out_width(struct tegra_dc *dc);
375
376 /* PM0 and PM1 signal control */
377 #define TEGRA_PWM_PM0 0
378 #define TEGRA_PWM_PM1 1
379
380 struct tegra_dc_pwm_params {
381         int which_pwm;
382         unsigned int period;
383         unsigned int clk_div;
384         unsigned int clk_select;
385         unsigned int duty_cycle;
386 };
387
388 void tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg);
389
390 #endif