video: tegra: detect fbmem alignment on probe
[linux-2.6.git] / arch / arm / mach-tegra / include / mach / dc.h
1 /*
2  * arch/arm/mach-tegra/include/mach/dc.h
3  *
4  * Copyright (C) 2010 Google, Inc.
5  *
6  * Author:
7  *      Erik Gilling <konkers@google.com>
8  *
9  * Copyright (C) 2010-2011 NVIDIA Corporation
10  *
11  * This software is licensed under the terms of the GNU General Public
12  * License version 2, as published by the Free Software Foundation, and
13  * may be copied, distributed, and modified under those terms.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  */
21
22 #ifndef __MACH_TEGRA_DC_H
23 #define __MACH_TEGRA_DC_H
24
25 #include <linux/pm.h>
26 #include <linux/types.h>
27 #include <drm/drm_fixed.h>
28
29 #define TEGRA_MAX_DC            2
30 #define DC_N_WINDOWS            3
31
32
33 /* DSI pixel data format */
34 enum {
35         TEGRA_DSI_PIXEL_FORMAT_16BIT_P,
36         TEGRA_DSI_PIXEL_FORMAT_18BIT_P,
37         TEGRA_DSI_PIXEL_FORMAT_18BIT_NP,
38         TEGRA_DSI_PIXEL_FORMAT_24BIT_P,
39 };
40
41 /* DSI virtual channel number */
42 enum {
43         TEGRA_DSI_VIRTUAL_CHANNEL_0,
44         TEGRA_DSI_VIRTUAL_CHANNEL_1,
45         TEGRA_DSI_VIRTUAL_CHANNEL_2,
46         TEGRA_DSI_VIRTUAL_CHANNEL_3,
47 };
48
49 /* DSI transmit method for video data */
50 enum {
51         TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE,
52         TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE,
53 };
54
55 /* DSI HS clock mode */
56 enum {
57         TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS,
58         TEGRA_DSI_VIDEO_CLOCK_TX_ONLY,
59 };
60
61 /* DSI burst mode setting in video mode. Each mode is assigned with a
62  * fixed value. The rationale behind this is to avoid change of these
63  * values, since the calculation of dsi clock depends on them. */
64 enum {
65         TEGRA_DSI_VIDEO_NONE_BURST_MODE = 0,
66         TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END = 1,
67         TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED = 2,
68         TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED = 3,
69         TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED = 4,
70         TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED = 5,
71         TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED = 6,
72 };
73
74 enum {
75         TEGRA_DSI_PACKET_CMD,
76         TEGRA_DSI_DELAY_MS,
77 };
78
79 struct tegra_dsi_cmd {
80         u8      cmd_type;
81         u8      data_id;
82         union {
83                 u16 data_len;
84                 u16 delay_ms;
85                 struct {
86                         u8 data0;
87                         u8 data1;
88                 } sp;
89         } sp_len_dly;
90         u8      *pdata;
91 };
92
93 #define DSI_CMD_SHORT(di, p0, p1)       { \
94                                         .cmd_type = TEGRA_DSI_PACKET_CMD, \
95                                         .data_id = di, \
96                                         .sp_len_dly.sp.data0 = p0, \
97                                         .sp_len_dly.sp.data1 = p1, \
98                                         }
99 #define DSI_DLY_MS(ms)  { \
100                         .cmd_type = TEGRA_DSI_DELAY_MS, \
101                         .sp_len_dly.delay_ms = ms, \
102                         }
103
104 #define DSI_CMD_LONG(di, ptr)   { \
105                                 .cmd_type = TEGRA_DSI_PACKET_CMD, \
106                                 .data_id = di, \
107                                 .sp_len_dly.data_len = ARRAY_SIZE(ptr), \
108                                 .pdata = ptr, \
109                                 }
110
111 struct dsi_phy_timing_ns {
112         u16             t_hsdexit_ns;
113         u16             t_hstrail_ns;
114         u16             t_datzero_ns;
115         u16             t_hsprepare_ns;
116
117         u16             t_clktrail_ns;
118         u16             t_clkpost_ns;
119         u16             t_clkzero_ns;
120         u16             t_tlpx_ns;
121
122         u16             t_clkprepare_ns;
123         u16             t_clkpre_ns;
124         u16             t_wakeup_ns;
125
126         u16             t_taget_ns;
127         u16             t_tasure_ns;
128         u16             t_tago_ns;
129 };
130
131 struct tegra_dsi_out {
132         u8              n_data_lanes;                   /* required */
133         u8              pixel_format;                   /* required */
134         u8              refresh_rate;                   /* required */
135         u8              rated_refresh_rate;
136         u8              panel_reset;                    /* required */
137         u8              virtual_channel;                /* required */
138         u8              dsi_instance;
139         u8              chip_id;
140         u8              chip_rev;
141
142         bool            panel_has_frame_buffer; /* required*/
143
144         struct tegra_dsi_cmd    *dsi_init_cmd;          /* required */
145         u16             n_init_cmd;                     /* required */
146
147         struct tegra_dsi_cmd    *dsi_early_suspend_cmd;
148         u16             n_early_suspend_cmd;
149
150         struct tegra_dsi_cmd    *dsi_late_resume_cmd;
151         u16             n_late_resume_cmd;
152
153         struct tegra_dsi_cmd    *dsi_suspend_cmd;       /* required */
154         u16             n_suspend_cmd;                  /* required */
155
156         u8              video_data_type;                /* required */
157         u8              video_clock_mode;
158         u8              video_burst_mode;
159
160         u16             panel_buffer_size_byte;
161         u16             panel_reset_timeout_msec;
162
163         bool            hs_cmd_mode_supported;
164         bool            hs_cmd_mode_on_blank_supported;
165         bool            enable_hs_clock_on_lp_cmd_mode;
166         bool            no_pkt_seq_eot; /* 1st generation panel may not
167                                          * support eot. Don't set it for
168                                          * most panels. */
169         bool            te_polarity_low;
170         bool            power_saving_suspend;
171
172         u32             max_panel_freq_khz;
173         u32             lp_cmd_mode_freq_khz;
174         u32             lp_read_cmd_mode_freq_khz;
175         u32             hs_clk_in_lp_cmd_mode_freq_khz;
176         u32             burst_mode_freq_khz;
177
178         struct dsi_phy_timing_ns phy_timing;
179 };
180
181 enum {
182         TEGRA_DC_STEREO_MODE_2D,
183         TEGRA_DC_STEREO_MODE_3D
184 };
185
186 enum {
187         TEGRA_DC_STEREO_LANDSCAPE,
188         TEGRA_DC_STEREO_PORTRAIT
189 };
190
191 struct tegra_stereo_out {
192         int  mode_2d_3d;
193         int  orientation;
194
195         void (*set_mode)(int mode);
196         void (*set_orientation)(int orientation);
197 };
198
199 struct tegra_dc_mode {
200         int     pclk;
201         int     rated_pclk;
202         int     h_ref_to_sync;
203         int     v_ref_to_sync;
204         int     h_sync_width;
205         int     v_sync_width;
206         int     h_back_porch;
207         int     v_back_porch;
208         int     h_active;
209         int     v_active;
210         int     h_front_porch;
211         int     v_front_porch;
212         int     stereo_mode;
213         u32     flags;
214 };
215
216 #define TEGRA_DC_MODE_FLAG_NEG_V_SYNC   (1 << 0)
217 #define TEGRA_DC_MODE_FLAG_NEG_H_SYNC   (1 << 1)
218
219 enum {
220         TEGRA_DC_OUT_RGB,
221         TEGRA_DC_OUT_HDMI,
222         TEGRA_DC_OUT_DSI,
223 };
224
225 struct tegra_dc_out_pin {
226         int     name;
227         int     pol;
228 };
229
230 enum {
231         TEGRA_DC_OUT_PIN_DATA_ENABLE,
232         TEGRA_DC_OUT_PIN_H_SYNC,
233         TEGRA_DC_OUT_PIN_V_SYNC,
234         TEGRA_DC_OUT_PIN_PIXEL_CLOCK,
235 };
236
237 enum {
238         TEGRA_DC_OUT_PIN_POL_LOW,
239         TEGRA_DC_OUT_PIN_POL_HIGH,
240 };
241
242 enum {
243         TEGRA_DC_DISABLE_DITHER = 1,
244         TEGRA_DC_ORDERED_DITHER,
245         TEGRA_DC_ERRDIFF_DITHER,
246 };
247
248 typedef u8 tegra_dc_bl_output[256];
249 typedef u8 *p_tegra_dc_bl_output;
250
251 struct tegra_dc_sd_blp {
252         u16 time_constant;
253         u8 step;
254 };
255
256 struct tegra_dc_sd_fc {
257         u8 time_limit;
258         u8 threshold;
259 };
260
261 struct tegra_dc_sd_rgb {
262         u8 r;
263         u8 g;
264         u8 b;
265 };
266
267 struct tegra_dc_sd_agg_priorities {
268         u8 pri_lvl;
269         u8 agg[4];
270 };
271
272 struct tegra_dc_sd_settings {
273         unsigned enable;
274         bool use_auto_pwm;
275         u8 hw_update_delay;
276         u8 aggressiveness;
277         short bin_width;
278         u8 phase_in_settings;
279         u8 phase_in_adjustments;
280         u8 cmd;
281         u8 final_agg;
282         u16 cur_agg_step;
283         u16 phase_settings_step;
284         u16 phase_adj_step;
285         u16 num_phase_in_steps;
286
287         struct tegra_dc_sd_agg_priorities agg_priorities;
288
289         bool use_vid_luma;
290         struct tegra_dc_sd_rgb coeff;
291
292         struct tegra_dc_sd_fc fc;
293         struct tegra_dc_sd_blp blp;
294         u8 bltf[4][4][4];
295         struct tegra_dc_sd_rgb lut[4][9];
296
297         atomic_t *sd_brightness;
298         struct platform_device *bl_device;
299 };
300
301 enum {
302         NO_CMD = 0x0,
303         ENABLE = 0x1,
304         DISABLE = 0x2,
305         PHASE_IN = 0x4,
306         AGG_CHG = 0x8,
307 };
308
309 enum {
310         TEGRA_PIN_OUT_CONFIG_SEL_LHP0_LD21,
311         TEGRA_PIN_OUT_CONFIG_SEL_LHP1_LD18,
312         TEGRA_PIN_OUT_CONFIG_SEL_LHP2_LD19,
313         TEGRA_PIN_OUT_CONFIG_SEL_LVP0_LVP0_Out,
314         TEGRA_PIN_OUT_CONFIG_SEL_LVP1_LD20,
315
316         TEGRA_PIN_OUT_CONFIG_SEL_LM1_M1,
317         TEGRA_PIN_OUT_CONFIG_SEL_LM1_LD21,
318         TEGRA_PIN_OUT_CONFIG_SEL_LM1_PM1,
319
320         TEGRA_PIN_OUT_CONFIG_SEL_LDI_LD22,
321         TEGRA_PIN_OUT_CONFIG_SEL_LPP_LD23,
322         TEGRA_PIN_OUT_CONFIG_SEL_LDC_SDC,
323         TEGRA_PIN_OUT_CONFIG_SEL_LSPI_DE,
324 };
325
326 struct tegra_dc_out {
327         int                             type;
328         unsigned                        flags;
329
330         /* size in mm */
331         unsigned                        h_size;
332         unsigned                        v_size;
333
334         int                             dcc_bus;
335         int                             hotplug_gpio;
336         const char                      *parent_clk;
337         const char                      *parent_clk_backup;
338
339         unsigned                        max_pixclock;
340         unsigned                        order;
341         unsigned                        align;
342         unsigned                        depth;
343         unsigned                        dither;
344
345         struct tegra_dc_mode            *modes;
346         int                             n_modes;
347
348         struct tegra_dsi_out            *dsi;
349         struct tegra_stereo_out         *stereo;
350
351         unsigned                        height; /* mm */
352         unsigned                        width; /* mm */
353
354         struct tegra_dc_out_pin         *out_pins;
355         unsigned                        n_out_pins;
356
357         struct tegra_dc_sd_settings     *sd_settings;
358
359         u8                      *out_sel_configs;
360         unsigned                n_out_sel_configs;
361
362         int     (*enable)(void);
363         int     (*postpoweron)(void);
364         int     (*disable)(void);
365
366         int     (*hotplug_init)(void);
367         int     (*postsuspend)(void);
368 };
369
370 /* bits for tegra_dc_out.flags */
371 #define TEGRA_DC_OUT_HOTPLUG_HIGH               (0 << 1)
372 #define TEGRA_DC_OUT_HOTPLUG_LOW                (1 << 1)
373 #define TEGRA_DC_OUT_HOTPLUG_MASK               (1 << 1)
374 #define TEGRA_DC_OUT_NVHDCP_POLICY_ALWAYS_ON    (0 << 2)
375 #define TEGRA_DC_OUT_NVHDCP_POLICY_ON_DEMAND    (1 << 2)
376 #define TEGRA_DC_OUT_NVHDCP_POLICY_MASK         (1 << 2)
377 #define TEGRA_DC_OUT_CONTINUOUS_MODE            (0 << 3)
378 #define TEGRA_DC_OUT_ONE_SHOT_MODE              (1 << 3)
379 #define TEGRA_DC_OUT_N_SHOT_MODE                (1 << 4)
380
381 #define TEGRA_DC_ALIGN_MSB              0
382 #define TEGRA_DC_ALIGN_LSB              1
383
384 #define TEGRA_DC_ORDER_RED_BLUE         0
385 #define TEGRA_DC_ORDER_BLUE_RED         1
386
387 struct tegra_dc;
388 struct nvmap_handle_ref;
389
390 struct tegra_dc_csc {
391         unsigned short yof;
392         unsigned short kyrgb;
393         unsigned short kur;
394         unsigned short kvr;
395         unsigned short kug;
396         unsigned short kvg;
397         unsigned short kub;
398         unsigned short kvb;
399 };
400
401 /* palette lookup table */
402 struct tegra_dc_lut {
403         u8 r[256];
404         u8 g[256];
405         u8 b[256];
406 };
407
408 struct tegra_dc_win {
409         u8                      idx;
410         u8                      fmt;
411         u8                      ppflags; /* see TEGRA_WIN_PPFLAG* */
412         u32                     flags;
413
414         void                    *virt_addr;
415         dma_addr_t              phys_addr;
416         dma_addr_t              phys_addr_u;
417         dma_addr_t              phys_addr_v;
418         unsigned                stride;
419         unsigned                stride_uv;
420         fixed20_12              x;
421         fixed20_12              y;
422         fixed20_12              w;
423         fixed20_12              h;
424         unsigned                out_x;
425         unsigned                out_y;
426         unsigned                out_w;
427         unsigned                out_h;
428         unsigned                z;
429         u8                      global_alpha;
430
431         struct tegra_dc_csc     csc;
432
433         int                     dirty;
434         int                     underflows;
435         struct tegra_dc         *dc;
436
437         struct nvmap_handle_ref *cur_handle;
438         unsigned                bandwidth;
439         unsigned                new_bandwidth;
440         struct tegra_dc_lut     lut;
441 };
442
443 #define TEGRA_WIN_PPFLAG_CP_ENABLE      (1 << 0) /* enable RGB color lut */
444 #define TEGRA_WIN_PPFLAG_CP_FBOVERRIDE  (1 << 1) /* override fbdev color lut */
445
446 #define TEGRA_WIN_FLAG_ENABLED          (1 << 0)
447 #define TEGRA_WIN_FLAG_BLEND_PREMULT    (1 << 1)
448 #define TEGRA_WIN_FLAG_BLEND_COVERAGE   (1 << 2)
449 #define TEGRA_WIN_FLAG_INVERT_H         (1 << 3)
450 #define TEGRA_WIN_FLAG_INVERT_V         (1 << 4)
451 #define TEGRA_WIN_FLAG_TILED            (1 << 5)
452 #define TEGRA_WIN_FLAG_H_FILTER         (1 << 6)
453 #define TEGRA_WIN_FLAG_V_FILTER         (1 << 7)
454
455
456 #define TEGRA_WIN_BLEND_FLAGS_MASK \
457         (TEGRA_WIN_FLAG_BLEND_PREMULT | TEGRA_WIN_FLAG_BLEND_COVERAGE)
458
459 /* Note: These are the actual values written to the DC_WIN_COLOR_DEPTH register
460  * and may change in new tegra architectures.
461  */
462 #define TEGRA_WIN_FMT_P1                0
463 #define TEGRA_WIN_FMT_P2                1
464 #define TEGRA_WIN_FMT_P4                2
465 #define TEGRA_WIN_FMT_P8                3
466 #define TEGRA_WIN_FMT_B4G4R4A4          4
467 #define TEGRA_WIN_FMT_B5G5R5A           5
468 #define TEGRA_WIN_FMT_B5G6R5            6
469 #define TEGRA_WIN_FMT_AB5G5R5           7
470 #define TEGRA_WIN_FMT_B8G8R8A8          12
471 #define TEGRA_WIN_FMT_R8G8B8A8          13
472 #define TEGRA_WIN_FMT_B6x2G6x2R6x2A8    14
473 #define TEGRA_WIN_FMT_R6x2G6x2B6x2A8    15
474 #define TEGRA_WIN_FMT_YCbCr422          16
475 #define TEGRA_WIN_FMT_YUV422            17
476 #define TEGRA_WIN_FMT_YCbCr420P         18
477 #define TEGRA_WIN_FMT_YUV420P           19
478 #define TEGRA_WIN_FMT_YCbCr422P         20
479 #define TEGRA_WIN_FMT_YUV422P           21
480 #define TEGRA_WIN_FMT_YCbCr422R         22
481 #define TEGRA_WIN_FMT_YUV422R           23
482 #define TEGRA_WIN_FMT_YCbCr422RA        24
483 #define TEGRA_WIN_FMT_YUV422RA          25
484
485 struct tegra_fb_data {
486         int             win;
487
488         int             xres;
489         int             yres;
490         int             bits_per_pixel; /* -1 means autodetect */
491
492         unsigned long   flags;
493 };
494
495 #define TEGRA_FB_FLIP_ON_PROBE          (1 << 0)
496
497 struct tegra_dc_platform_data {
498         unsigned long           flags;
499         unsigned long           emc_clk_rate;
500         struct tegra_dc_out     *default_out;
501         struct tegra_fb_data    *fb;
502 };
503
504 #define TEGRA_DC_FLAG_ENABLED           (1 << 0)
505
506 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win);
507 struct tegra_dc *tegra_dc_get_dc(unsigned idx);
508 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win);
509 bool tegra_dc_get_connected(struct tegra_dc *);
510 bool tegra_dc_hpd(struct tegra_dc *dc);
511
512
513 void tegra_dc_blank(struct tegra_dc *dc);
514
515 void tegra_dc_enable(struct tegra_dc *dc);
516 void tegra_dc_disable(struct tegra_dc *dc);
517
518 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i);
519 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i);
520 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val);
521
522 /* tegra_dc_update_windows and tegra_dc_sync_windows do not support windows
523  * with differenct dcs in one call
524  */
525 int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n);
526 int tegra_dc_sync_windows(struct tegra_dc_win *windows[], int n);
527
528 int tegra_dc_set_mode(struct tegra_dc *dc, const struct tegra_dc_mode *mode);
529 struct fb_videomode;
530 int tegra_dc_set_fb_mode(struct tegra_dc *dc, const struct fb_videomode *fbmode,
531         bool stereo_mode);
532
533 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc);
534 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc);
535 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc);
536
537 /* PM0 and PM1 signal control */
538 #define TEGRA_PWM_PM0 0
539 #define TEGRA_PWM_PM1 1
540
541 struct tegra_dc_pwm_params {
542         int which_pwm;
543         void (*switch_to_sfio)(int);
544         int gpio_conf_to_sfio;
545         unsigned int period;
546         unsigned int clk_div;
547         unsigned int clk_select;
548         unsigned int duty_cycle;
549 };
550
551 void tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg);
552
553 int tegra_dsi_send_panel_short_cmd(struct tegra_dc *dc, u8 *pdata, u8 data_len);
554 void tegra_dc_host_trigger(struct tegra_dc *dc);
555
556 int tegra_dc_update_csc(struct tegra_dc *dc, int win_index);
557
558 int tegra_dc_update_lut(struct tegra_dc *dc, int win_index, int fboveride);
559
560 /*
561  * In order to get a dc's current EDID, first call tegra_dc_get_edid() from an
562  * interruptible context.  The returned value (if non-NULL) points to a
563  * snapshot of the current state; after copying data from it, call
564  * tegra_dc_put_edid() on that pointer.  Do not dereference anything through
565  * that pointer after calling tegra_dc_put_edid().
566  */
567 struct tegra_dc_edid {
568         size_t          len;
569         u8              buf[0];
570 };
571 struct tegra_dc_edid *tegra_dc_get_edid(struct tegra_dc *dc);
572 void tegra_dc_put_edid(struct tegra_dc_edid *edid);
573
574 #endif