4ea988218fc3986fb82f420b092c588d1997ccc8
[linux-2.6.git] / arch / arm / mach-tegra / include / mach / dc.h
1 /*
2  * arch/arm/mach-tegra/include/mach/dc.h
3  *
4  * Copyright (C) 2010 Google, Inc.
5  *
6  * Author:
7  *      Erik Gilling <konkers@google.com>
8  *
9  * Copyright (C) 2010-2011 NVIDIA Corporation
10  *
11  * This software is licensed under the terms of the GNU General Public
12  * License version 2, as published by the Free Software Foundation, and
13  * may be copied, distributed, and modified under those terms.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  */
21
22 #ifndef __MACH_TEGRA_DC_H
23 #define __MACH_TEGRA_DC_H
24
25 #include <linux/pm.h>
26 #include <linux/types.h>
27
28 #define TEGRA_MAX_DC            2
29 #define DC_N_WINDOWS            3
30
31
32 /* DSI pixel data format */
33 enum {
34         TEGRA_DSI_PIXEL_FORMAT_16BIT_P,
35         TEGRA_DSI_PIXEL_FORMAT_18BIT_P,
36         TEGRA_DSI_PIXEL_FORMAT_18BIT_NP,
37         TEGRA_DSI_PIXEL_FORMAT_24BIT_P,
38 };
39
40 /* DSI virtual channel number */
41 enum {
42         TEGRA_DSI_VIRTUAL_CHANNEL_0,
43         TEGRA_DSI_VIRTUAL_CHANNEL_1,
44         TEGRA_DSI_VIRTUAL_CHANNEL_2,
45         TEGRA_DSI_VIRTUAL_CHANNEL_3,
46 };
47
48 /* DSI transmit method for video data */
49 enum {
50         TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE,
51         TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE,
52 };
53
54 /* DSI HS clock mode */
55 enum {
56         TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS,
57         TEGRA_DSI_VIDEO_CLOCK_TX_ONLY,
58 };
59
60 /* DSI burst mode setting in video mode. Each mode is assigned with a
61  * fixed value. The rationale behind this is to avoid change of these
62  * values, since the calculation of dsi clock depends on them. */
63 enum {
64         TEGRA_DSI_VIDEO_NONE_BURST_MODE = 0,
65         TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END = 1,
66         TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED = 2,
67         TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED = 3,
68         TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED = 4,
69         TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED = 5,
70         TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED = 6,
71 };
72
73 enum {
74         TEGRA_DSI_PACKET_CMD,
75         TEGRA_DSI_DELAY_MS,
76 };
77
78 struct tegra_dsi_cmd {
79         u8      cmd_type;
80         u8      data_id;
81         union {
82                 u16 data_len;
83                 u16 delay_ms;
84                 struct{
85                         u8 data0;
86                         u8 data1;
87                 }sp;
88         }sp_len_dly;
89         u8      *pdata;
90 };
91
92 #define DSI_CMD_SHORT(di, p0, p1)       { \
93                                         .cmd_type = TEGRA_DSI_PACKET_CMD, \
94                                         .data_id = di, \
95                                         .sp_len_dly.sp.data0 = p0, \
96                                         .sp_len_dly.sp.data1 = p1, \
97                                         }
98 #define DSI_DLY_MS(ms)  { \
99                         .cmd_type = TEGRA_DSI_DELAY_MS, \
100                         .sp_len_dly.delay_ms = ms, \
101                         }
102
103 #define DSI_CMD_LONG(di, ptr)   { \
104                                 .cmd_type = TEGRA_DSI_PACKET_CMD, \
105                                 .data_id = di, \
106                                 .sp_len_dly.data_len = ARRAY_SIZE(ptr), \
107                                 .pdata = ptr, \
108                                 }
109
110 struct dsi_phy_timing_ns {
111         u16             t_hsdexit_ns;
112         u16             t_hstrail_ns;
113         u16             t_hsprepr_ns;
114         u16             t_datzero_ns;
115
116         u16             t_clktrail_ns;
117         u16             t_clkpost_ns;
118         u16             t_clkzero_ns;
119         u16             t_tlpx_ns;
120 };
121
122 struct tegra_dsi_out {
123         u8              n_data_lanes;                   /* required */
124         u8              pixel_format;                   /* required */
125         u8              refresh_rate;                   /* required */
126         u8              panel_reset;                    /* required */
127         u8              virtual_channel;                /* required */
128         u8              dsi_instance;
129
130         bool            panel_has_frame_buffer; /* required*/
131
132         struct tegra_dsi_cmd*   dsi_init_cmd;           /* required */
133         u16             n_init_cmd;                     /* required */
134
135         struct tegra_dsi_cmd*   dsi_suspend_cmd;        /* required */
136         u16             n_suspend_cmd;                  /* required */
137
138         u8              video_data_type;                /* required */
139         u8              video_clock_mode;
140         u8              video_burst_mode;
141
142         u16             panel_buffer_size_byte;
143         u16             panel_reset_timeout_msec;
144
145         bool            hs_cmd_mode_supported;
146         bool            hs_cmd_mode_on_blank_supported;
147         bool            enable_hs_clock_on_lp_cmd_mode;
148         bool            no_pkt_seq_eot; /* 1st generation panel may not
149                                          * support eot. Don't set it for
150                                          * most panels. */
151
152         u32             max_panel_freq_khz;
153         u32             lp_cmd_mode_freq_khz;
154         u32             hs_clk_in_lp_cmd_mode_freq_khz;
155         u32             burst_mode_freq_khz;
156
157         struct dsi_phy_timing_ns phy_timing;
158 };
159
160 enum {
161         TEGRA_DC_STEREO_MODE_2D,
162         TEGRA_DC_STEREO_MODE_3D
163 };
164
165 enum {
166         TEGRA_DC_STEREO_LANDSCAPE,
167         TEGRA_DC_STEREO_PORTRAIT
168 };
169
170 struct tegra_stereo_out {
171         int  mode_2d_3d;
172         int  orientation;
173
174         void (*set_mode)(int mode);
175         void (*set_orientation)(int orientation);
176 };
177
178 struct tegra_dc_mode {
179         int     pclk;
180         int     h_ref_to_sync;
181         int     v_ref_to_sync;
182         int     h_sync_width;
183         int     v_sync_width;
184         int     h_back_porch;
185         int     v_back_porch;
186         int     h_active;
187         int     v_active;
188         int     h_front_porch;
189         int     v_front_porch;
190         int     stereo_mode;
191         u32     flags;
192 };
193
194 #define TEGRA_DC_MODE_FLAG_NEG_V_SYNC   (1 << 0)
195 #define TEGRA_DC_MODE_FLAG_NEG_H_SYNC   (1 << 1)
196
197 enum {
198         TEGRA_DC_OUT_RGB,
199         TEGRA_DC_OUT_HDMI,
200         TEGRA_DC_OUT_DSI,
201 };
202
203 struct tegra_dc_out_pin {
204         int     name;
205         int     pol;
206 };
207
208 enum {
209         TEGRA_DC_OUT_PIN_DATA_ENABLE,
210         TEGRA_DC_OUT_PIN_H_SYNC,
211         TEGRA_DC_OUT_PIN_V_SYNC,
212         TEGRA_DC_OUT_PIN_PIXEL_CLOCK,
213 };
214
215 enum {
216         TEGRA_DC_OUT_PIN_POL_LOW,
217         TEGRA_DC_OUT_PIN_POL_HIGH,
218 };
219
220 enum {
221         TEGRA_DC_DISABLE_DITHER = 1,
222         TEGRA_DC_ORDERED_DITHER,
223         TEGRA_DC_ERRDIFF_DITHER,
224 };
225
226 struct tegra_dc_sd_blp {
227         u16 time_constant;
228         u8 step;
229 };
230
231 struct tegra_dc_sd_fc {
232         u8 time_limit;
233         u8 threshold;
234 };
235
236 struct tegra_dc_sd_rgb {
237         u8 r;
238         u8 g;
239         u8 b;
240 };
241
242 struct tegra_dc_sd_settings {
243         unsigned enable;
244         bool use_auto_pwm;
245         u8 hw_update_delay;
246         unsigned bin_width;
247         u8 aggressiveness;
248
249         bool use_vid_luma;
250         struct tegra_dc_sd_rgb coeff;
251
252         struct tegra_dc_sd_fc fc;
253         struct tegra_dc_sd_blp blp;
254         u8 bltf[4][4][4];
255         struct tegra_dc_sd_rgb lut[4][9];
256
257         atomic_t *sd_brightness;
258         struct platform_device *bl_device;
259 };
260
261 enum {
262         TEGRA_PIN_OUT_CONFIG_SEL_LHP0_LD21,
263         TEGRA_PIN_OUT_CONFIG_SEL_LHP1_LD18,
264         TEGRA_PIN_OUT_CONFIG_SEL_LHP2_LD19,
265         TEGRA_PIN_OUT_CONFIG_SEL_LVP0_LVP0_Out,
266         TEGRA_PIN_OUT_CONFIG_SEL_LVP1_LD20,
267
268         TEGRA_PIN_OUT_CONFIG_SEL_LM1_M1,
269         TEGRA_PIN_OUT_CONFIG_SEL_LM1_LD21,
270         TEGRA_PIN_OUT_CONFIG_SEL_LM1_PM1,
271
272         TEGRA_PIN_OUT_CONFIG_SEL_LDI_LD22,
273         TEGRA_PIN_OUT_CONFIG_SEL_LPP_LD23,
274         TEGRA_PIN_OUT_CONFIG_SEL_LDC_SDC,
275         TEGRA_PIN_OUT_CONFIG_SEL_LSPI_DE,
276 };
277
278 struct tegra_dc_out {
279         int                             type;
280         unsigned                        flags;
281
282         /* size in mm */
283         unsigned                        h_size;
284         unsigned                        v_size;
285
286         int                             dcc_bus;
287         int                             hotplug_gpio;
288         const char                      *parent_clk;
289
290         unsigned                        max_pixclock;
291         unsigned                        order;
292         unsigned                        align;
293         unsigned                        depth;
294         unsigned                        dither;
295
296         struct tegra_dc_mode            *modes;
297         int                             n_modes;
298
299         struct tegra_dsi_out            *dsi;
300         struct tegra_stereo_out         *stereo;
301
302         unsigned                        height; /* mm */
303         unsigned                        width; /* mm */
304
305         struct tegra_dc_out_pin         *out_pins;
306         unsigned                        n_out_pins;
307
308         struct tegra_dc_sd_settings     *sd_settings;
309
310         u8                      *out_sel_configs;
311         unsigned                n_out_sel_configs;
312
313         int     (*enable)(void);
314         int     (*postpoweron)(void);
315         int     (*disable)(void);
316
317         int     (*hotplug_init)(void);
318         int     (*postsuspend)(void);
319 };
320
321 /* bits for tegra_dc_out.flags */
322 #define TEGRA_DC_OUT_HOTPLUG_HIGH               (0 << 1)
323 #define TEGRA_DC_OUT_HOTPLUG_LOW                (1 << 1)
324 #define TEGRA_DC_OUT_HOTPLUG_MASK               (1 << 1)
325 #define TEGRA_DC_OUT_NVHDCP_POLICY_ALWAYS_ON    (0 << 2)
326 #define TEGRA_DC_OUT_NVHDCP_POLICY_ON_DEMAND    (1 << 2)
327 #define TEGRA_DC_OUT_NVHDCP_POLICY_MASK         (1 << 2)
328
329 #define TEGRA_DC_ALIGN_MSB              0
330 #define TEGRA_DC_ALIGN_LSB              1
331
332 #define TEGRA_DC_ORDER_RED_BLUE         0
333 #define TEGRA_DC_ORDER_BLUE_RED         1
334
335 struct tegra_dc;
336 struct nvmap_handle_ref;
337
338 struct tegra_dc_win {
339         u8                      idx;
340         u8                      fmt;
341         u32                     flags;
342
343         void                    *virt_addr;
344         dma_addr_t              phys_addr;
345         unsigned                offset;
346         unsigned                offset_u;
347         unsigned                offset_v;
348         unsigned                stride;
349         unsigned                stride_uv;
350         unsigned                x;
351         unsigned                y;
352         unsigned                w;
353         unsigned                h;
354         unsigned                out_x;
355         unsigned                out_y;
356         unsigned                out_w;
357         unsigned                out_h;
358         unsigned                z;
359
360         int                     dirty;
361         int                     underflows;
362         struct tegra_dc         *dc;
363
364         struct nvmap_handle_ref *cur_handle;
365 };
366
367
368 #define TEGRA_WIN_FLAG_ENABLED          (1 << 0)
369 #define TEGRA_WIN_FLAG_BLEND_PREMULT    (1 << 1)
370 #define TEGRA_WIN_FLAG_BLEND_COVERAGE   (1 << 2)
371 #define TEGRA_WIN_FLAG_INVERT_H         (1 << 3)
372 #define TEGRA_WIN_FLAG_INVERT_V         (1 << 4)
373 #define TEGRA_WIN_FLAG_TILED            (1 << 5)
374
375 #define TEGRA_WIN_BLEND_FLAGS_MASK \
376         (TEGRA_WIN_FLAG_BLEND_PREMULT | TEGRA_WIN_FLAG_BLEND_COVERAGE)
377
378 /* Note: These are the actual values written to the DC_WIN_COLOR_DEPTH register
379  * and may change in new tegra architectures.
380  */
381 #define TEGRA_WIN_FMT_P1                0
382 #define TEGRA_WIN_FMT_P2                1
383 #define TEGRA_WIN_FMT_P4                2
384 #define TEGRA_WIN_FMT_P8                3
385 #define TEGRA_WIN_FMT_B4G4R4A4          4
386 #define TEGRA_WIN_FMT_B5G5R5A           5
387 #define TEGRA_WIN_FMT_B5G6R5            6
388 #define TEGRA_WIN_FMT_AB5G5R5           7
389 #define TEGRA_WIN_FMT_B8G8R8A8          12
390 #define TEGRA_WIN_FMT_R8G8B8A8          13
391 #define TEGRA_WIN_FMT_B6x2G6x2R6x2A8    14
392 #define TEGRA_WIN_FMT_R6x2G6x2B6x2A8    15
393 #define TEGRA_WIN_FMT_YCbCr422          16
394 #define TEGRA_WIN_FMT_YUV422            17
395 #define TEGRA_WIN_FMT_YCbCr420P         18
396 #define TEGRA_WIN_FMT_YUV420P           19
397 #define TEGRA_WIN_FMT_YCbCr422P         20
398 #define TEGRA_WIN_FMT_YUV422P           21
399 #define TEGRA_WIN_FMT_YCbCr422R         22
400 #define TEGRA_WIN_FMT_YUV422R           23
401 #define TEGRA_WIN_FMT_YCbCr422RA        24
402 #define TEGRA_WIN_FMT_YUV422RA          25
403
404 struct tegra_fb_data {
405         int             win;
406
407         int             xres;
408         int             yres;
409         int             bits_per_pixel; /* -1 means autodetect */
410
411         unsigned long   flags;
412 };
413
414 #define TEGRA_FB_FLIP_ON_PROBE          (1 << 0)
415
416 struct tegra_dc_platform_data {
417         unsigned long           flags;
418         unsigned long           emc_clk_rate;
419         struct tegra_dc_out     *default_out;
420         struct tegra_fb_data    *fb;
421 };
422
423 #define TEGRA_DC_FLAG_ENABLED           (1 << 0)
424
425 struct tegra_dc *tegra_dc_get_dc(unsigned idx);
426 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win);
427
428 void tegra_dc_enable(struct tegra_dc *dc);
429 void tegra_dc_disable(struct tegra_dc *dc);
430
431 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc);
432 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc);
433 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, u32 val);
434
435 int tegra_dc_set_default_emc(struct tegra_dc *dc);
436 int tegra_dc_set_dynamic_emc(struct tegra_dc_win *windows[], int n);
437
438 /* tegra_dc_update_windows and tegra_dc_sync_windows do not support windows
439  * with differenct dcs in one call
440  */
441 int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n);
442 int tegra_dc_sync_windows(struct tegra_dc_win *windows[], int n);
443
444 int tegra_dc_set_mode(struct tegra_dc *dc, const struct tegra_dc_mode *mode);
445 struct fb_videomode;
446 int tegra_dc_set_fb_mode(struct tegra_dc *dc, const struct fb_videomode *fbmode,
447         bool stereo_mode);
448
449 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc);
450 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc);
451 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc);
452
453 /* PM0 and PM1 signal control */
454 #define TEGRA_PWM_PM0 0
455 #define TEGRA_PWM_PM1 1
456
457 struct tegra_dc_pwm_params {
458         int which_pwm;
459         unsigned int period;
460         unsigned int clk_div;
461         unsigned int clk_select;
462         unsigned int duty_cycle;
463 };
464
465 void tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg);
466
467 #endif