f25b84d44786782a4833007b7034d05701dcf320
[linux-2.6.git] / arch / arm / mach-tegra / devices.c
1 /*
2  * Copyright (C) 2010,2011 Google, Inc.
3  *
4  * Author:
5  *      Colin Cross <ccross@android.com>
6  *      Erik Gilling <ccross@android.com>
7  *
8  * This software is licensed under the terms of the GNU General Public
9  * License version 2, as published by the Free Software Foundation, and
10  * may be copied, distributed, and modified under those terms.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  */
18
19
20 #include <linux/resource.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/fsl_devices.h>
24 #include <linux/serial_8250.h>
25 #include <linux/i2c-tegra.h>
26 #include <linux/platform_data/tegra_usb.h>
27 #include <asm/pmu.h>
28 #include <mach/irqs.h>
29 #include <mach/iomap.h>
30 #include <mach/dma.h>
31 #include <mach/usb_phy.h>
32 #include "gpio-names.h"
33
34 static struct resource i2c_resource1[] = {
35         [0] = {
36                 .start  = INT_I2C,
37                 .end    = INT_I2C,
38                 .flags  = IORESOURCE_IRQ,
39         },
40         [1] = {
41                 .start  = TEGRA_I2C_BASE,
42                 .end    = TEGRA_I2C_BASE + TEGRA_I2C_SIZE-1,
43                 .flags  = IORESOURCE_MEM,
44         },
45 };
46
47 static struct resource i2c_resource2[] = {
48         [0] = {
49                 .start  = INT_I2C2,
50                 .end    = INT_I2C2,
51                 .flags  = IORESOURCE_IRQ,
52         },
53         [1] = {
54                 .start  = TEGRA_I2C2_BASE,
55                 .end    = TEGRA_I2C2_BASE + TEGRA_I2C2_SIZE-1,
56                 .flags  = IORESOURCE_MEM,
57         },
58 };
59
60 static struct resource i2c_resource3[] = {
61         [0] = {
62                 .start  = INT_I2C3,
63                 .end    = INT_I2C3,
64                 .flags  = IORESOURCE_IRQ,
65         },
66         [1] = {
67                 .start  = TEGRA_I2C3_BASE,
68                 .end    = TEGRA_I2C3_BASE + TEGRA_I2C3_SIZE-1,
69                 .flags  = IORESOURCE_MEM,
70         },
71 };
72
73 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
74 static struct resource i2c_resource4[] = {
75         [0] = {
76                 .start  = INT_DVC,
77                 .end    = INT_DVC,
78                 .flags  = IORESOURCE_IRQ,
79         },
80         [1] = {
81                 .start  = TEGRA_DVC_BASE,
82                 .end    = TEGRA_DVC_BASE + TEGRA_DVC_SIZE-1,
83                 .flags  = IORESOURCE_MEM,
84         },
85 };
86
87 #elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
88 static struct resource i2c_resource4[] = {
89         [0] = {
90                 .start  = INT_I2C4,
91                 .end    = INT_I2C4,
92                 .flags  = IORESOURCE_IRQ,
93         },
94         [1] = {
95                 .start  = TEGRA_I2C4_BASE,
96                 .end    = TEGRA_I2C4_BASE + TEGRA_I2C4_SIZE-1,
97                 .flags  = IORESOURCE_MEM,
98         },
99 };
100
101 static struct resource i2c_resource5[] = {
102         [0] = {
103                 .start  = INT_I2C5,
104                 .end    = INT_I2C5,
105                 .flags  = IORESOURCE_IRQ,
106         },
107         [1] = {
108                 .start  = TEGRA_I2C5_BASE,
109                 .end    = TEGRA_I2C5_BASE + TEGRA_I2C5_SIZE-1,
110                 .flags  = IORESOURCE_MEM,
111         },
112 };
113 #endif
114
115 static struct tegra_i2c_platform_data tegra_i2c1_platform_data = {
116         .bus_clk_rate   = { 400000 },
117 };
118
119 static struct tegra_i2c_platform_data tegra_i2c2_platform_data = {
120         .bus_clk_rate   = { 400000 },
121 };
122
123 static struct tegra_i2c_platform_data tegra_i2c3_platform_data = {
124         .bus_clk_rate   = { 400000 },
125 };
126
127 static struct tegra_i2c_platform_data tegra_dvc_platform_data = {
128         .bus_clk_rate   = { 400000 },
129 };
130
131 struct platform_device tegra_i2c_device1 = {
132         .name           = "tegra-i2c",
133         .id             = 0,
134         .resource       = i2c_resource1,
135         .num_resources  = ARRAY_SIZE(i2c_resource1),
136         .dev = {
137                 .platform_data = &tegra_i2c1_platform_data,
138         },
139 };
140
141 struct platform_device tegra_i2c_device2 = {
142         .name           = "tegra-i2c",
143         .id             = 1,
144         .resource       = i2c_resource2,
145         .num_resources  = ARRAY_SIZE(i2c_resource2),
146         .dev = {
147                 .platform_data = &tegra_i2c2_platform_data,
148         },
149 };
150
151 struct platform_device tegra_i2c_device3 = {
152         .name           = "tegra-i2c",
153         .id             = 2,
154         .resource       = i2c_resource3,
155         .num_resources  = ARRAY_SIZE(i2c_resource3),
156         .dev = {
157                 .platform_data = &tegra_i2c3_platform_data,
158         },
159 };
160
161 struct platform_device tegra_i2c_device4 = {
162         .name           = "tegra-i2c",
163         .id             = 3,
164         .resource       = i2c_resource4,
165         .num_resources  = ARRAY_SIZE(i2c_resource4),
166         .dev = {
167                 .platform_data = &tegra_dvc_platform_data,
168         },
169 };
170
171 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
172 struct platform_device tegra_i2c_device5 = {
173         .name           = "tegra-i2c",
174         .id             = 4,
175         .resource       = i2c_resource5,
176         .num_resources  = ARRAY_SIZE(i2c_resource5),
177         .dev = {
178                 .platform_data = 0,
179         },
180 };
181 #endif
182
183 static struct resource spi_resource1[] = {
184         [0] = {
185                 .start  = INT_SPI_1,
186                 .end    = INT_SPI_1,
187                 .flags  = IORESOURCE_IRQ,
188         },
189         [1] = {
190                 .start  = TEGRA_SPI1_BASE,
191                 .end    = TEGRA_SPI1_BASE + TEGRA_SPI1_SIZE-1,
192                 .flags  = IORESOURCE_MEM,
193         },
194 };
195
196 static struct resource spi_resource2[] = {
197         [0] = {
198                 .start  = INT_SPI_2,
199                 .end    = INT_SPI_2,
200                 .flags  = IORESOURCE_IRQ,
201         },
202         [1] = {
203                 .start  = TEGRA_SPI2_BASE,
204                 .end    = TEGRA_SPI2_BASE + TEGRA_SPI2_SIZE-1,
205                 .flags  = IORESOURCE_MEM,
206         },
207 };
208
209 static struct resource spi_resource3[] = {
210         [0] = {
211                 .start  = INT_SPI_3,
212                 .end    = INT_SPI_3,
213                 .flags  = IORESOURCE_IRQ,
214         },
215         [1] = {
216                 .start  = TEGRA_SPI3_BASE,
217                 .end    = TEGRA_SPI3_BASE + TEGRA_SPI3_SIZE-1,
218                 .flags  = IORESOURCE_MEM,
219         },
220 };
221
222 static struct resource spi_resource4[] = {
223         [0] = {
224                 .start  = INT_SPI_4,
225                 .end    = INT_SPI_4,
226                 .flags  = IORESOURCE_IRQ,
227         },
228         [1] = {
229                 .start  = TEGRA_SPI4_BASE,
230                 .end    = TEGRA_SPI4_BASE + TEGRA_SPI4_SIZE-1,
231                 .flags  = IORESOURCE_MEM,
232         },
233 };
234 #if defined(CONFIG_ARCH_TEGRA_3x_SOC)
235 static struct resource spi_resource5[] = {
236         [0] = {
237                 .start  = INT_SPI_5,
238                 .end    = INT_SPI_5,
239                 .flags  = IORESOURCE_IRQ,
240         },
241         [1] = {
242                 .start  = TEGRA_SPI5_BASE,
243                 .end    = TEGRA_SPI5_BASE + TEGRA_SPI5_SIZE-1,
244                 .flags  = IORESOURCE_MEM,
245         },
246 };
247
248 static struct resource spi_resource6[] = {
249         [0] = {
250                 .start  = INT_SPI_6,
251                 .end    = INT_SPI_6,
252                 .flags  = IORESOURCE_IRQ,
253         },
254         [1] = {
255                 .start  = TEGRA_SPI6_BASE,
256                 .end    = TEGRA_SPI6_BASE + TEGRA_SPI6_SIZE-1,
257                 .flags  = IORESOURCE_MEM,
258         },
259 };
260 #endif
261
262 struct platform_device tegra_spi_device1 = {
263         .name           = "spi_tegra",
264         .id             = 0,
265         .resource       = spi_resource1,
266         .num_resources  = ARRAY_SIZE(spi_resource1),
267         .dev            = {
268                 .coherent_dma_mask      = 0xffffffff,
269         },
270 };
271
272 struct platform_device tegra_spi_device2 = {
273         .name           = "spi_tegra",
274         .id             = 1,
275         .resource       = spi_resource2,
276         .num_resources  = ARRAY_SIZE(spi_resource2),
277         .dev            = {
278                 .coherent_dma_mask      = 0xffffffff,
279         },
280 };
281
282 struct platform_device tegra_spi_device3 = {
283         .name           = "spi_tegra",
284         .id             = 2,
285         .resource       = spi_resource3,
286         .num_resources  = ARRAY_SIZE(spi_resource3),
287         .dev            = {
288                 .coherent_dma_mask      = 0xffffffff,
289         },
290 };
291
292 struct platform_device tegra_spi_device4 = {
293         .name           = "spi_tegra",
294         .id             = 3,
295         .resource       = spi_resource4,
296         .num_resources  = ARRAY_SIZE(spi_resource4),
297         .dev            = {
298                 .coherent_dma_mask      = 0xffffffff,
299         },
300 };
301 #if defined(CONFIG_ARCH_TEGRA_3x_SOC)
302 struct platform_device tegra_spi_device5 = {
303         .name           = "spi_tegra",
304         .id             = 4,
305         .resource       = spi_resource5,
306         .num_resources  = ARRAY_SIZE(spi_resource5),
307         .dev  = {
308                 .coherent_dma_mask      = 0xffffffff,
309         },
310 };
311
312 struct platform_device tegra_spi_device6 = {
313         .name           = "spi_tegra",
314         .id             = 5,
315         .resource       = spi_resource6,
316         .num_resources  = ARRAY_SIZE(spi_resource6),
317         .dev  = {
318                 .coherent_dma_mask      = 0xffffffff,
319         },
320 };
321 #endif
322
323 struct platform_device tegra_spi_slave_device1 = {
324         .name           = "spi_slave_tegra",
325         .id             = 0,
326         .resource       = spi_resource1,
327         .num_resources  = ARRAY_SIZE(spi_resource1),
328         .dev  = {
329                 .coherent_dma_mask      = 0xffffffff,
330         },
331 };
332
333 struct platform_device tegra_spi_slave_device2 = {
334         .name           = "spi_slave_tegra",
335         .id             = 1,
336         .resource       = spi_resource2,
337         .num_resources  = ARRAY_SIZE(spi_resource2),
338         .dev  = {
339                 .coherent_dma_mask      = 0xffffffff,
340         },
341 };
342
343 struct platform_device tegra_spi_slave_device3 = {
344         .name           = "spi_slave_tegra",
345         .id             = 2,
346         .resource       = spi_resource3,
347         .num_resources  = ARRAY_SIZE(spi_resource3),
348         .dev  = {
349                 .coherent_dma_mask      = 0xffffffff,
350         },
351 };
352
353 struct platform_device tegra_spi_slave_device4 = {
354         .name           = "spi_slave_tegra",
355         .id             = 3,
356         .resource       = spi_resource4,
357         .num_resources  = ARRAY_SIZE(spi_resource4),
358         .dev  = {
359                 .coherent_dma_mask      = 0xffffffff,
360         },
361 };
362 #if defined(CONFIG_ARCH_TEGRA_3x_SOC)
363 struct platform_device tegra_spi_slave_device5 = {
364         .name           = "spi_slave_tegra",
365         .id             = 4,
366         .resource       = spi_resource5,
367         .num_resources  = ARRAY_SIZE(spi_resource5),
368         .dev  = {
369                 .coherent_dma_mask      = 0xffffffff,
370         },
371 };
372
373 struct platform_device tegra_spi_slave_device6 = {
374         .name           = "spi_slave_tegra",
375         .id             = 5,
376         .resource       = spi_resource6,
377         .num_resources  = ARRAY_SIZE(spi_resource6),
378         .dev  = {
379                 .coherent_dma_mask      = 0xffffffff,
380         },
381 };
382 #endif
383
384
385
386 static struct resource sdhci_resource1[] = {
387         [0] = {
388                 .start  = INT_SDMMC1,
389                 .end    = INT_SDMMC1,
390                 .flags  = IORESOURCE_IRQ,
391         },
392         [1] = {
393                 .start  = TEGRA_SDMMC1_BASE,
394                 .end    = TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE-1,
395                 .flags  = IORESOURCE_MEM,
396         },
397 };
398
399 static struct resource sdhci_resource2[] = {
400         [0] = {
401                 .start  = INT_SDMMC2,
402                 .end    = INT_SDMMC2,
403                 .flags  = IORESOURCE_IRQ,
404         },
405         [1] = {
406                 .start  = TEGRA_SDMMC2_BASE,
407                 .end    = TEGRA_SDMMC2_BASE + TEGRA_SDMMC2_SIZE-1,
408                 .flags  = IORESOURCE_MEM,
409         },
410 };
411
412 static struct resource sdhci_resource3[] = {
413         [0] = {
414                 .start  = INT_SDMMC3,
415                 .end    = INT_SDMMC3,
416                 .flags  = IORESOURCE_IRQ,
417         },
418         [1] = {
419                 .start  = TEGRA_SDMMC3_BASE,
420                 .end    = TEGRA_SDMMC3_BASE + TEGRA_SDMMC3_SIZE-1,
421                 .flags  = IORESOURCE_MEM,
422         },
423 };
424
425 static struct resource sdhci_resource4[] = {
426         [0] = {
427                 .start  = INT_SDMMC4,
428                 .end    = INT_SDMMC4,
429                 .flags  = IORESOURCE_IRQ,
430         },
431         [1] = {
432                 .start  = TEGRA_SDMMC4_BASE,
433                 .end    = TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE-1,
434                 .flags  = IORESOURCE_MEM,
435         },
436 };
437
438 /* board files should fill in platform_data register the devices themselvs.
439  * See board-harmony.c for an example
440  */
441 struct platform_device tegra_sdhci_device1 = {
442         .name           = "sdhci-tegra",
443         .id             = 0,
444         .resource       = sdhci_resource1,
445         .num_resources  = ARRAY_SIZE(sdhci_resource1),
446 };
447
448 struct platform_device tegra_sdhci_device2 = {
449         .name           = "sdhci-tegra",
450         .id             = 1,
451         .resource       = sdhci_resource2,
452         .num_resources  = ARRAY_SIZE(sdhci_resource2),
453 };
454
455 struct platform_device tegra_sdhci_device3 = {
456         .name           = "sdhci-tegra",
457         .id             = 2,
458         .resource       = sdhci_resource3,
459         .num_resources  = ARRAY_SIZE(sdhci_resource3),
460 };
461
462 struct platform_device tegra_sdhci_device4 = {
463         .name           = "sdhci-tegra",
464         .id             = 3,
465         .resource       = sdhci_resource4,
466         .num_resources  = ARRAY_SIZE(sdhci_resource4),
467 };
468
469 static struct resource tegra_usb1_resources[] = {
470         [0] = {
471                 .start  = TEGRA_USB_BASE,
472                 .end    = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
473                 .flags  = IORESOURCE_MEM,
474         },
475         [1] = {
476                 .start  = INT_USB,
477                 .end    = INT_USB,
478                 .flags  = IORESOURCE_IRQ,
479         },
480 };
481
482 static struct resource tegra_usb2_resources[] = {
483         [0] = {
484                 .start  = TEGRA_USB2_BASE,
485                 .end    = TEGRA_USB2_BASE + TEGRA_USB2_SIZE - 1,
486                 .flags  = IORESOURCE_MEM,
487         },
488         [1] = {
489                 .start  = INT_USB2,
490                 .end    = INT_USB2,
491                 .flags  = IORESOURCE_IRQ,
492         },
493 };
494
495 static struct resource tegra_usb3_resources[] = {
496         [0] = {
497                 .start  = TEGRA_USB3_BASE,
498                 .end    = TEGRA_USB3_BASE + TEGRA_USB3_SIZE - 1,
499                 .flags  = IORESOURCE_MEM,
500         },
501         [1] = {
502                 .start  = INT_USB3,
503                 .end    = INT_USB3,
504                 .flags  = IORESOURCE_IRQ,
505         },
506 };
507
508 static struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
509         /* All existing boards use GPIO PV0 for phy reset */
510         .reset_gpio = TEGRA_GPIO_PV0,
511         .clk = "cdev2",
512 };
513
514 static struct tegra_ehci_platform_data tegra_ehci1_pdata = {
515         .operating_mode = TEGRA_USB_OTG,
516         .power_down_on_bus_suspend = 1,
517 };
518
519 static struct tegra_ehci_platform_data tegra_ehci2_pdata = {
520         .phy_config = &tegra_ehci2_ulpi_phy_config,
521         .operating_mode = TEGRA_USB_HOST,
522         .power_down_on_bus_suspend = 1,
523 };
524
525 static struct tegra_ehci_platform_data tegra_ehci3_pdata = {
526         .operating_mode = TEGRA_USB_HOST,
527         .power_down_on_bus_suspend = 1,
528 };
529
530 static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32);
531
532 struct platform_device tegra_ehci1_device = {
533         .name   = "tegra-ehci",
534         .id     = 0,
535         .dev    = {
536                 .dma_mask       = &tegra_ehci_dmamask,
537                 .coherent_dma_mask = DMA_BIT_MASK(32),
538                 .platform_data = &tegra_ehci1_pdata,
539         },
540         .resource = tegra_usb1_resources,
541         .num_resources = ARRAY_SIZE(tegra_usb1_resources),
542 };
543
544 struct platform_device tegra_ehci2_device = {
545         .name   = "tegra-ehci",
546         .id     = 1,
547         .dev    = {
548                 .dma_mask       = &tegra_ehci_dmamask,
549                 .coherent_dma_mask = DMA_BIT_MASK(32),
550                 .platform_data = &tegra_ehci2_pdata,
551         },
552         .resource = tegra_usb2_resources,
553         .num_resources = ARRAY_SIZE(tegra_usb2_resources),
554 };
555
556 struct platform_device tegra_ehci3_device = {
557         .name   = "tegra-ehci",
558         .id     = 2,
559         .dev    = {
560                 .dma_mask       = &tegra_ehci_dmamask,
561                 .coherent_dma_mask = DMA_BIT_MASK(32),
562                 .platform_data = &tegra_ehci3_pdata,
563         },
564         .resource = tegra_usb3_resources,
565         .num_resources = ARRAY_SIZE(tegra_usb3_resources),
566 };
567
568 static struct resource tegra_pmu_resources[] = {
569         [0] = {
570                 .start  = INT_CPU0_PMU_INTR,
571                 .end    = INT_CPU0_PMU_INTR,
572                 .flags  = IORESOURCE_IRQ,
573         },
574         [1] = {
575                 .start  = INT_CPU1_PMU_INTR,
576                 .end    = INT_CPU1_PMU_INTR,
577                 .flags  = IORESOURCE_IRQ,
578         },
579 #if defined(CONFIG_ARCH_TEGRA_3x_SOC)
580         [2] = {
581                 .start  = INT_CPU2_PMU_INTR,
582                 .end    = INT_CPU2_PMU_INTR,
583                 .flags  = IORESOURCE_IRQ,
584         },
585         [3] = {
586                 .start  = INT_CPU3_PMU_INTR,
587                 .end    = INT_CPU3_PMU_INTR,
588                 .flags  = IORESOURCE_IRQ,
589         },
590 #endif
591 };
592
593 struct platform_device tegra_pmu_device = {
594         .name           = "arm-pmu",
595         .id             = ARM_PMU_DEVICE_CPU,
596         .num_resources  = ARRAY_SIZE(tegra_pmu_resources),
597         .resource       = tegra_pmu_resources,
598 };
599
600 static struct resource tegra_uarta_resources[] = {
601         [0] = {
602                 .start  = TEGRA_UARTA_BASE,
603                 .end    = TEGRA_UARTA_BASE + TEGRA_UARTA_SIZE - 1,
604                 .flags  = IORESOURCE_MEM,
605         },
606         [1] = {
607                 .start  = INT_UARTA,
608                 .end    = INT_UARTA,
609                 .flags  = IORESOURCE_IRQ,
610         },
611 };
612
613 static struct resource tegra_uartb_resources[] = {
614         [0] = {
615                 .start  = TEGRA_UARTB_BASE,
616                 .end    = TEGRA_UARTB_BASE + TEGRA_UARTB_SIZE - 1,
617                 .flags  = IORESOURCE_MEM,
618         },
619         [1] = {
620                 .start  = INT_UARTB,
621                 .end    = INT_UARTB,
622                 .flags  = IORESOURCE_IRQ,
623         },
624 };
625
626 static struct resource tegra_uartc_resources[] = {
627         [0] = {
628                 .start  = TEGRA_UARTC_BASE,
629                 .end    = TEGRA_UARTC_BASE + TEGRA_UARTC_SIZE - 1,
630                 .flags  = IORESOURCE_MEM,
631         },
632         [1] = {
633                 .start  = INT_UARTC,
634                 .end    = INT_UARTC,
635                 .flags  = IORESOURCE_IRQ,
636         },
637 };
638
639 static struct resource tegra_uartd_resources[] = {
640         [0] = {
641                 .start  = TEGRA_UARTD_BASE,
642                 .end    = TEGRA_UARTD_BASE + TEGRA_UARTD_SIZE - 1,
643                 .flags  = IORESOURCE_MEM,
644         },
645         [1] = {
646                 .start  = INT_UARTD,
647                 .end    = INT_UARTD,
648                 .flags  = IORESOURCE_IRQ,
649         },
650 };
651
652 static struct resource tegra_uarte_resources[] = {
653         [0] = {
654                 .start  = TEGRA_UARTE_BASE,
655                 .end    = TEGRA_UARTE_BASE + TEGRA_UARTE_SIZE - 1,
656                 .flags  = IORESOURCE_MEM,
657         },
658         [1] = {
659                 .start  = INT_UARTE,
660                 .end    = INT_UARTE,
661                 .flags  = IORESOURCE_IRQ,
662         },
663 };
664
665 struct platform_device tegra_uarta_device = {
666         .name   = "tegra_uart",
667         .id     = 0,
668         .num_resources  = ARRAY_SIZE(tegra_uarta_resources),
669         .resource       = tegra_uarta_resources,
670         .dev    = {
671                 .coherent_dma_mask      = DMA_BIT_MASK(32),
672         },
673 };
674
675 struct platform_device tegra_uartb_device = {
676         .name   = "tegra_uart",
677         .id     = 1,
678         .num_resources  = ARRAY_SIZE(tegra_uartb_resources),
679         .resource       = tegra_uartb_resources,
680         .dev    = {
681                 .coherent_dma_mask      = DMA_BIT_MASK(32),
682         },
683 };
684
685 struct platform_device tegra_uartc_device = {
686         .name   = "tegra_uart",
687         .id     = 2,
688         .num_resources  = ARRAY_SIZE(tegra_uartc_resources),
689         .resource       = tegra_uartc_resources,
690         .dev    = {
691                 .coherent_dma_mask      = DMA_BIT_MASK(32),
692         },
693 };
694
695 struct platform_device tegra_uartd_device = {
696         .name   = "tegra_uart",
697         .id     = 3,
698         .num_resources  = ARRAY_SIZE(tegra_uartd_resources),
699         .resource       = tegra_uartd_resources,
700         .dev    = {
701                 .coherent_dma_mask      = DMA_BIT_MASK(32),
702         },
703 };
704
705 struct platform_device tegra_uarte_device = {
706         .name   = "tegra_uart",
707         .id     = 4,
708         .num_resources  = ARRAY_SIZE(tegra_uarte_resources),
709         .resource       = tegra_uarte_resources,
710         .dev    = {
711                 .coherent_dma_mask      = DMA_BIT_MASK(32),
712         },
713 };
714
715 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
716 static struct resource i2s_resource1[] = {
717         [0] = {
718                 .start  = INT_I2S1,
719                 .end    = INT_I2S1,
720                 .flags  = IORESOURCE_IRQ
721         },
722         [1] = {
723                 .start  = TEGRA_DMA_REQ_SEL_I2S_1,
724                 .end    = TEGRA_DMA_REQ_SEL_I2S_1,
725                 .flags  = IORESOURCE_DMA
726         },
727         [2] = {
728                 .start  = TEGRA_I2S1_BASE,
729                 .end    = TEGRA_I2S1_BASE + TEGRA_I2S1_SIZE - 1,
730                 .flags  = IORESOURCE_MEM
731         }
732 };
733
734 struct platform_device tegra_i2s_device1 = {
735         .name           = "tegra-i2s",
736         .id             = 0,
737         .resource       = i2s_resource1,
738         .num_resources  = ARRAY_SIZE(i2s_resource1),
739 };
740
741 static struct resource i2s_resource2[] = {
742         [0] = {
743                 .start  = INT_I2S2,
744                 .end    = INT_I2S2,
745                 .flags  = IORESOURCE_IRQ
746         },
747         [1] = {
748                 .start  = TEGRA_DMA_REQ_SEL_I2S2_1,
749                 .end    = TEGRA_DMA_REQ_SEL_I2S2_1,
750                 .flags  = IORESOURCE_DMA
751         },
752         [2] = {
753                 .start  = TEGRA_I2S2_BASE,
754                 .end    = TEGRA_I2S2_BASE + TEGRA_I2S2_SIZE - 1,
755                 .flags  = IORESOURCE_MEM
756         }
757 };
758
759 struct platform_device tegra_i2s_device2 = {
760         .name           = "tegra-i2s",
761         .id             = 1,
762         .resource       = i2s_resource2,
763         .num_resources  = ARRAY_SIZE(i2s_resource2),
764 };
765
766 struct platform_device tegra_pcm_device = {
767         .name = "tegra-pcm-audio",
768         .id = -1,
769 };
770
771
772 static struct resource spdif_resource[] = {
773         [0] = {
774                 .start  = INT_SPDIF,
775                 .end    = INT_SPDIF,
776                 .flags  = IORESOURCE_IRQ
777         },
778         [1] = {
779                 .start  = TEGRA_DMA_REQ_SEL_SPD_I,
780                 .end    = TEGRA_DMA_REQ_SEL_SPD_I,
781                 .flags  = IORESOURCE_DMA
782         },
783         [2] = {
784                 .start  = TEGRA_SPDIF_BASE,
785                 .end    = TEGRA_SPDIF_BASE + TEGRA_SPDIF_SIZE - 1,
786                 .flags  = IORESOURCE_MEM
787         }
788 };
789
790 #elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
791 static struct resource audio_resource[] = {
792         [0] = {
793                 .start  = TEGRA_AUDIO_CLUSTER_BASE,
794                 .end    = TEGRA_AUDIO_CLUSTER_BASE + TEGRA_AUDIO_CLUSTER_SIZE - 1,
795                 .flags  = IORESOURCE_MEM
796         }
797 };
798
799 struct platform_device tegra_audio_device = {
800         .name           = "audio",
801         .id             = 1,
802         .resource       = audio_resource,
803         .num_resources  = ARRAY_SIZE(audio_resource),
804 };
805
806 /* FIXME : Temporarly adding - find the right solution */
807
808 static struct resource spdif_resource[] = {
809         [0] = {
810                 .start  = TEGRA_DMA_REQ_SEL_APBIF_CH3,
811                 .end    = TEGRA_DMA_REQ_SEL_APBIF_CH3,
812                 .flags  = IORESOURCE_DMA
813         },
814         [1] = {
815                 .start  = TEGRA_SPDIF_BASE,
816                 .end    = TEGRA_SPDIF_BASE + TEGRA_SPDIF_SIZE - 1,
817                 .flags  = IORESOURCE_MEM
818         }
819 };
820 #endif
821
822 struct platform_device tegra_spdif_device = {
823         .name           = "spdif_out",
824         .id             = -1,
825         .resource       = spdif_resource,
826         .num_resources  = ARRAY_SIZE(spdif_resource),
827 };
828
829 #if defined(CONFIG_SND_HDA_TEGRA)
830 static u64 tegra_hda_dma_mask = DMA_BIT_MASK(32);
831
832 static struct resource tegra_hda_resources[] = {
833         [0] = {
834                 .start  = TEGRA_HDA_BASE,
835                 .end    = TEGRA_HDA_BASE + TEGRA_HDA_SIZE - 1 ,
836                 .flags  = IORESOURCE_MEM
837         },
838         [1] = {
839                 .start  = INT_HDA,
840                 .end    = INT_HDA,
841                 .flags  = IORESOURCE_IRQ
842         },
843 };
844
845 struct platform_device tegra_hda_device = {
846         .name           = "tegra-hda",
847         .id             = 0,
848         .dev = {
849                 .coherent_dma_mask      = DMA_BIT_MASK(32),
850                 .dma_mask               = &tegra_hda_dma_mask,
851         },
852         .resource       = tegra_hda_resources,
853         .num_resources  = ARRAY_SIZE(tegra_hda_resources),
854 };
855 #endif
856
857 static struct resource w1_resources[] = {
858         [0] = {
859                 .start = INT_OWR,
860                 .end   = INT_OWR,
861                 .flags = IORESOURCE_IRQ
862         },
863         [1] = {
864                 .start = TEGRA_OWR_BASE,
865                 .end = TEGRA_OWR_BASE + TEGRA_OWR_SIZE - 1,
866                 .flags = IORESOURCE_MEM
867         }
868 };
869
870 struct platform_device tegra_w1_device = {
871         .name          = "tegra_w1",
872         .id            = -1,
873         .resource      = w1_resources,
874         .num_resources = ARRAY_SIZE(w1_resources),
875 };
876
877 static struct resource tegra_udc_resources[] = {
878         [0] = {
879                 .start  = TEGRA_USB_BASE,
880                 .end    = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
881                 .flags  = IORESOURCE_MEM,
882         },
883         [1] = {
884                 .start  = INT_USB,
885                 .end    = INT_USB,
886                 .flags  = IORESOURCE_IRQ,
887         },
888 };
889
890 static u64 tegra_udc_dmamask = DMA_BIT_MASK(32);
891
892 static struct fsl_usb2_platform_data tegra_udc_pdata = {
893         .operating_mode = FSL_USB2_DR_DEVICE,
894         .phy_mode       = FSL_USB2_PHY_UTMI,
895 };
896
897 struct platform_device tegra_udc_device = {
898         .name   = "fsl-tegra-udc",
899         .id     = -1,
900         .dev    = {
901                 .dma_mask       = &tegra_udc_dmamask,
902                 .coherent_dma_mask = DMA_BIT_MASK(32),
903                 .platform_data  = &tegra_udc_pdata,
904         },
905         .resource = tegra_udc_resources,
906         .num_resources = ARRAY_SIZE(tegra_udc_resources),
907 };
908
909 static struct resource tegra_otg_resources[] = {
910         [0] = {
911                 .start  = TEGRA_USB_BASE,
912                 .end    = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
913                 .flags  = IORESOURCE_MEM,
914         },
915         [1] = {
916                 .start  = INT_USB,
917                 .end    = INT_USB,
918                 .flags  = IORESOURCE_IRQ,
919         },
920 };
921
922 struct platform_device tegra_otg_device = {
923         .name           = "tegra-otg",
924         .id             = -1,
925         .resource       = tegra_otg_resources,
926         .num_resources  = ARRAY_SIZE(tegra_otg_resources),
927 };
928
929 #ifdef CONFIG_SATA_AHCI_TEGRA
930 static u64 tegra_sata_dma_mask = DMA_BIT_MASK(32);
931
932 static struct resource tegra_sata_resources[] = {
933         [0] = {
934                 .start = TEGRA_SATA_BAR5_BASE,
935                 .end = TEGRA_SATA_BAR5_BASE + TEGRA_SATA_BAR5_SIZE - 1,
936                 .flags = IORESOURCE_MEM,
937         },
938         [1] = {
939                 .start = TEGRA_SATA_CONFIG_BASE,
940                 .end = TEGRA_SATA_CONFIG_BASE + TEGRA_SATA_CONFIG_SIZE - 1,
941                 .flags = IORESOURCE_MEM,
942         },
943         [2] = {
944                 .start = INT_SATA_CTL,
945                 .end = INT_SATA_CTL,
946                 .flags = IORESOURCE_IRQ,
947         },
948 };
949
950 struct platform_device tegra_sata_device = {
951         .name   = "tegra-sata",
952         .id     = 0,
953         .dev    = {
954                 .platform_data = 0,
955                 .coherent_dma_mask = DMA_BIT_MASK(32),
956                 .dma_mask = &tegra_sata_dma_mask,
957         },
958         .resource = tegra_sata_resources,
959         .num_resources = ARRAY_SIZE(tegra_sata_resources),
960 };
961 #endif
962
963 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
964 static struct resource das_resource[] = {
965         [0] = {
966                 .start  = TEGRA_APB_MISC_BASE,
967                 .end    = TEGRA_APB_MISC_BASE + TEGRA_APB_MISC_SIZE - 1,
968                 .flags  = IORESOURCE_MEM
969         }
970 };
971
972 struct platform_device tegra_das_device = {
973         .name           = "tegra_das",
974         .id             = -1,
975         .resource       = das_resource,
976         .num_resources  = ARRAY_SIZE(das_resource),
977 };
978 #endif
979
980 #if defined(CONFIG_TEGRA_IOVMM_GART)
981 static struct resource tegra_gart_resources[] = {
982         [0] = {
983                 .name   = "mc",
984                 .flags  = IORESOURCE_MEM,
985                 .start  = TEGRA_MC_BASE,
986                 .end    = TEGRA_MC_BASE + TEGRA_MC_SIZE - 1,
987         },
988         [1] = {
989                 .name   = "gart",
990                 .flags  = IORESOURCE_MEM,
991                 .start  = TEGRA_GART_BASE,
992                 .end    = TEGRA_GART_BASE + TEGRA_GART_SIZE - 1,
993         }
994 };
995
996 struct platform_device tegra_gart_device = {
997         .name           = "tegra_gart",
998         .id             = -1,
999         .num_resources  = ARRAY_SIZE(tegra_gart_resources),
1000         .resource       = tegra_gart_resources
1001 };
1002 #endif
1003
1004 #if defined(CONFIG_TEGRA_IOVMM_SMMU)
1005 static struct resource tegra_smmu_resources[] = {
1006         [0] = {
1007                 .name   = "mc",
1008                 .flags  = IORESOURCE_MEM,
1009                 .start  = TEGRA_MC_BASE,
1010                 .end    = TEGRA_MC_BASE + TEGRA_MC_SIZE - 1,
1011         },
1012         [1] = {
1013                 .name   = "smmu",
1014                 .flags  = IORESOURCE_MEM,
1015                 .start  = TEGRA_SMMU_BASE,
1016                 .end    = TEGRA_SMMU_BASE + TEGRA_SMMU_SIZE - 1,
1017         }
1018 };
1019
1020 struct platform_device tegra_smmu_device = {
1021         .name           = "tegra_smmu",
1022         .id             = -1,
1023         .num_resources  = ARRAY_SIZE(tegra_smmu_resources),
1024         .resource       = tegra_smmu_resources
1025 };
1026 #endif
1027
1028 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
1029 #define CLK_RESET_RST_SOURCE    0x0
1030 static struct resource tegra_wdt_resources[] = {
1031         [0] = {
1032                 .start  = TEGRA_CLK_RESET_BASE + CLK_RESET_RST_SOURCE,
1033                 .end    = TEGRA_CLK_RESET_BASE + CLK_RESET_RST_SOURCE + 4 - 1,
1034                 .flags  = IORESOURCE_MEM,
1035         },
1036         [1] = {
1037                 .start  = TEGRA_TMR1_BASE,
1038                 .end    = TEGRA_TMR1_BASE + TEGRA_TMR1_SIZE - 1,
1039                 .flags  = IORESOURCE_MEM,
1040         },
1041         [2] = {
1042                 .start  = INT_TMR1,
1043                 .end    = INT_TMR1,
1044                 .flags  = IORESOURCE_IRQ,
1045         },
1046 };
1047 #elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
1048 static struct resource tegra_wdt_resources[] = {
1049         [0] = {
1050                 .start  = TEGRA_WDT0_BASE,
1051                 .end    = TEGRA_WDT0_BASE + TEGRA_WDT0_SIZE - 1,
1052                 .flags  = IORESOURCE_MEM,
1053         },
1054         [1] = {
1055                 .start  = TEGRA_TMR10_BASE,
1056                 .end    = TEGRA_TMR10_BASE + TEGRA_TMR10_SIZE - 1,
1057                 .flags  = IORESOURCE_MEM,
1058         },
1059         [2] = {
1060                 .start  = INT_WDT_CPU,
1061                 .end    = INT_WDT_CPU,
1062                 .flags  = IORESOURCE_IRQ,
1063         },
1064 };
1065 #endif
1066
1067 struct platform_device tegra_wdt_device = {
1068         .name           = "tegra_wdt",
1069         .id             = -1,
1070         .num_resources  = ARRAY_SIZE(tegra_wdt_resources),
1071         .resource       = tegra_wdt_resources,
1072 };
1073
1074 static struct resource tegra_pwfm0_resource = {
1075         .start  = TEGRA_PWFM0_BASE,
1076         .end    = TEGRA_PWFM0_BASE + TEGRA_PWFM0_SIZE - 1,
1077         .flags  = IORESOURCE_MEM,
1078 };
1079
1080 static struct resource tegra_pwfm1_resource = {
1081         .start  = TEGRA_PWFM1_BASE,
1082         .end    = TEGRA_PWFM1_BASE + TEGRA_PWFM1_SIZE - 1,
1083         .flags  = IORESOURCE_MEM,
1084 };
1085
1086 static struct resource tegra_pwfm2_resource = {
1087         .start  = TEGRA_PWFM2_BASE,
1088         .end    = TEGRA_PWFM2_BASE + TEGRA_PWFM2_SIZE - 1,
1089         .flags  = IORESOURCE_MEM,
1090 };
1091
1092 static struct resource tegra_pwfm3_resource = {
1093         .start  = TEGRA_PWFM3_BASE,
1094         .end    = TEGRA_PWFM3_BASE + TEGRA_PWFM3_SIZE - 1,
1095         .flags  = IORESOURCE_MEM,
1096 };
1097
1098 struct platform_device tegra_pwfm0_device = {
1099         .name           = "tegra_pwm",
1100         .id             = 0,
1101         .num_resources  = 1,
1102         .resource       = &tegra_pwfm0_resource,
1103 };
1104
1105 struct platform_device tegra_pwfm1_device = {
1106         .name           = "tegra_pwm",
1107         .id             = 1,
1108         .num_resources  = 1,
1109         .resource       = &tegra_pwfm1_resource,
1110 };
1111
1112 struct platform_device tegra_pwfm2_device = {
1113         .name           = "tegra_pwm",
1114         .id             = 2,
1115         .num_resources  = 1,
1116         .resource       = &tegra_pwfm2_resource,
1117 };
1118
1119 struct platform_device tegra_pwfm3_device = {
1120         .name           = "tegra_pwm",
1121         .id             = 3,
1122         .num_resources  = 1,
1123         .resource       = &tegra_pwfm3_resource,
1124 };
1125
1126 static struct resource tegra_grhost_resources[] = {
1127         {
1128                 .start = TEGRA_HOST1X_BASE,
1129                 .end = TEGRA_HOST1X_BASE + TEGRA_HOST1X_SIZE - 1,
1130                 .flags = IORESOURCE_MEM,
1131         },
1132         {
1133                 .start = TEGRA_DISPLAY_BASE,
1134                 .end = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE - 1,
1135                 .flags = IORESOURCE_MEM,
1136         },
1137         {
1138                 .start = TEGRA_DISPLAY2_BASE,
1139                 .end = TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1,
1140                 .flags = IORESOURCE_MEM,
1141         },
1142         {
1143                 .start = TEGRA_VI_BASE,
1144                 .end = TEGRA_VI_BASE + TEGRA_VI_SIZE - 1,
1145                 .flags = IORESOURCE_MEM,
1146         },
1147         {
1148                 .start = TEGRA_ISP_BASE,
1149                 .end = TEGRA_ISP_BASE + TEGRA_ISP_SIZE - 1,
1150                 .flags = IORESOURCE_MEM,
1151         },
1152         {
1153                 .start = TEGRA_MPE_BASE,
1154                 .end = TEGRA_MPE_BASE + TEGRA_MPE_SIZE - 1,
1155                 .flags = IORESOURCE_MEM,
1156         },
1157         {
1158                 .start = INT_SYNCPT_THRESH_BASE,
1159                 .end = INT_SYNCPT_THRESH_BASE + INT_SYNCPT_THRESH_NR - 1,
1160                 .flags = IORESOURCE_IRQ,
1161         },
1162         {
1163                 .start = INT_HOST1X_MPCORE_GENERAL,
1164                 .end = INT_HOST1X_MPCORE_GENERAL,
1165                 .flags = IORESOURCE_IRQ,
1166         },
1167 };
1168
1169 struct platform_device tegra_grhost_device = {
1170         .name = "tegra_grhost",
1171         .id = -1,
1172         .resource = tegra_grhost_resources,
1173         .num_resources = ARRAY_SIZE(tegra_grhost_resources),
1174 };
1175
1176 static struct resource tegra_avp_resources[] = {
1177         [0] = {
1178                 .start  = INT_SHR_SEM_INBOX_IBF,
1179                 .end    = INT_SHR_SEM_INBOX_IBF,
1180                 .flags  = IORESOURCE_IRQ,
1181                 .name   = "mbox_from_avp_pending",
1182         },
1183 };
1184
1185 struct platform_device tegra_avp_device = {
1186         .name           = "tegra-avp",
1187         .id             = -1,
1188         .num_resources  = ARRAY_SIZE(tegra_avp_resources),
1189         .resource       = tegra_avp_resources,
1190         .dev  = {
1191                 .coherent_dma_mask      = 0xffffffffULL,
1192         },
1193 };
1194
1195 static struct resource tegra_aes_resources[] = {
1196         {
1197                 .start  = TEGRA_VDE_BASE,
1198                 .end    = TEGRA_VDE_BASE + TEGRA_VDE_BASE - 1,
1199                 .flags  = IORESOURCE_MEM,
1200         },
1201         {
1202                 .start  = TEGRA_BSEA_BASE,
1203                 .end    = TEGRA_BSEA_BASE + TEGRA_BSEA_SIZE - 1,
1204                 .flags  = IORESOURCE_MEM,
1205         },
1206 };
1207
1208 static u64 tegra_aes_dma_mask = DMA_BIT_MASK(32);
1209
1210 struct platform_device tegra_aes_device = {
1211         .name           = "tegra-aes",
1212         .id             = -1,
1213         .resource       = tegra_aes_resources,
1214         .num_resources  = ARRAY_SIZE(tegra_aes_resources),
1215         .dev    = {
1216                 .dma_mask = &tegra_aes_dma_mask,
1217                 .coherent_dma_mask = DMA_BIT_MASK(32),
1218         },
1219 };