e055e1d7e84c2b932136e134e90321d24bbf891e
[linux-2.6.git] / arch / arm / mach-tegra / devices.c
1 /*
2  * Copyright (C) 2010,2011 Google, Inc.
3  *
4  * Author:
5  *      Colin Cross <ccross@android.com>
6  *      Erik Gilling <ccross@android.com>
7  *
8  * Copyright (C) 2010-2011 NVIDIA Corporation.
9  *
10  * This software is licensed under the terms of the GNU General Public
11  * License version 2, as published by the Free Software Foundation, and
12  * may be copied, distributed, and modified under those terms.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  */
20
21
22 #include <linux/resource.h>
23 #include <linux/platform_device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/fsl_devices.h>
26 #include <linux/serial_8250.h>
27 #include <linux/i2c-tegra.h>
28 #include <linux/platform_data/tegra_usb.h>
29 #include <linux/tegra_avp.h>
30 #include <linux/nvhost.h>
31 #include <asm/pmu.h>
32 #include <mach/irqs.h>
33 #include <mach/iomap.h>
34 #include <mach/dma.h>
35 #include <mach/usb_phy.h>
36 #include "gpio-names.h"
37 #include "tegra_smmu.h"
38
39 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
40 #define UART_SOURCE_RATE 408000000
41 #else
42 #define UART_SOURCE_RATE 216000000
43 #endif
44
45 static struct resource i2c_resource1[] = {
46         [0] = {
47                 .start  = INT_I2C,
48                 .end    = INT_I2C,
49                 .flags  = IORESOURCE_IRQ,
50         },
51         [1] = {
52                 .start  = TEGRA_I2C_BASE,
53                 .end    = TEGRA_I2C_BASE + TEGRA_I2C_SIZE-1,
54                 .flags  = IORESOURCE_MEM,
55         },
56 };
57
58 static struct resource i2c_resource2[] = {
59         [0] = {
60                 .start  = INT_I2C2,
61                 .end    = INT_I2C2,
62                 .flags  = IORESOURCE_IRQ,
63         },
64         [1] = {
65                 .start  = TEGRA_I2C2_BASE,
66                 .end    = TEGRA_I2C2_BASE + TEGRA_I2C2_SIZE-1,
67                 .flags  = IORESOURCE_MEM,
68         },
69 };
70
71 static struct resource i2c_resource3[] = {
72         [0] = {
73                 .start  = INT_I2C3,
74                 .end    = INT_I2C3,
75                 .flags  = IORESOURCE_IRQ,
76         },
77         [1] = {
78                 .start  = TEGRA_I2C3_BASE,
79                 .end    = TEGRA_I2C3_BASE + TEGRA_I2C3_SIZE-1,
80                 .flags  = IORESOURCE_MEM,
81         },
82 };
83
84 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
85 static struct resource i2c_resource4[] = {
86         [0] = {
87                 .start  = INT_DVC,
88                 .end    = INT_DVC,
89                 .flags  = IORESOURCE_IRQ,
90         },
91         [1] = {
92                 .start  = TEGRA_DVC_BASE,
93                 .end    = TEGRA_DVC_BASE + TEGRA_DVC_SIZE-1,
94                 .flags  = IORESOURCE_MEM,
95         },
96 };
97
98 #else
99 static struct resource i2c_resource4[] = {
100         [0] = {
101                 .start  = INT_I2C4,
102                 .end    = INT_I2C4,
103                 .flags  = IORESOURCE_IRQ,
104         },
105         [1] = {
106                 .start  = TEGRA_I2C4_BASE,
107                 .end    = TEGRA_I2C4_BASE + TEGRA_I2C4_SIZE-1,
108                 .flags  = IORESOURCE_MEM,
109         },
110 };
111
112 static struct resource i2c_resource5[] = {
113         [0] = {
114                 .start  = INT_I2C5,
115                 .end    = INT_I2C5,
116                 .flags  = IORESOURCE_IRQ,
117         },
118         [1] = {
119                 .start  = TEGRA_I2C5_BASE,
120                 .end    = TEGRA_I2C5_BASE + TEGRA_I2C5_SIZE-1,
121                 .flags  = IORESOURCE_MEM,
122         },
123 };
124 #endif
125
126 static struct tegra_i2c_platform_data tegra_i2c1_platform_data = {
127         .bus_clk_rate   = { 400000 },
128 };
129
130 static struct tegra_i2c_platform_data tegra_i2c2_platform_data = {
131         .bus_clk_rate   = { 400000 },
132 };
133
134 static struct tegra_i2c_platform_data tegra_i2c3_platform_data = {
135         .bus_clk_rate   = { 400000 },
136 };
137
138 static struct tegra_i2c_platform_data tegra_dvc_platform_data = {
139         .bus_clk_rate   = { 400000 },
140 };
141
142 struct platform_device tegra_i2c_device1 = {
143         .name           = "tegra-i2c",
144         .id             = 0,
145         .resource       = i2c_resource1,
146         .num_resources  = ARRAY_SIZE(i2c_resource1),
147         .dev = {
148                 .platform_data = &tegra_i2c1_platform_data,
149         },
150 };
151
152 struct platform_device tegra_i2c_device2 = {
153         .name           = "tegra-i2c",
154         .id             = 1,
155         .resource       = i2c_resource2,
156         .num_resources  = ARRAY_SIZE(i2c_resource2),
157         .dev = {
158                 .platform_data = &tegra_i2c2_platform_data,
159         },
160 };
161
162 struct platform_device tegra_i2c_device3 = {
163         .name           = "tegra-i2c",
164         .id             = 2,
165         .resource       = i2c_resource3,
166         .num_resources  = ARRAY_SIZE(i2c_resource3),
167         .dev = {
168                 .platform_data = &tegra_i2c3_platform_data,
169         },
170 };
171
172 struct platform_device tegra_i2c_device4 = {
173         .name           = "tegra-i2c",
174         .id             = 3,
175         .resource       = i2c_resource4,
176         .num_resources  = ARRAY_SIZE(i2c_resource4),
177         .dev = {
178                 .platform_data = &tegra_dvc_platform_data,
179         },
180 };
181
182 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
183 struct platform_device tegra_i2c_device5 = {
184         .name           = "tegra-i2c",
185         .id             = 4,
186         .resource       = i2c_resource5,
187         .num_resources  = ARRAY_SIZE(i2c_resource5),
188         .dev = {
189                 .platform_data = 0,
190         },
191 };
192 #endif
193
194 static struct resource spi_resource1[] = {
195         [0] = {
196                 .start  = INT_SPI_1,
197                 .end    = INT_SPI_1,
198                 .flags  = IORESOURCE_IRQ,
199         },
200         [1] = {
201                 .start  = TEGRA_SPI1_BASE,
202                 .end    = TEGRA_SPI1_BASE + TEGRA_SPI1_SIZE-1,
203                 .flags  = IORESOURCE_MEM,
204         },
205 };
206
207 static struct resource spi_resource2[] = {
208         [0] = {
209                 .start  = INT_SPI_2,
210                 .end    = INT_SPI_2,
211                 .flags  = IORESOURCE_IRQ,
212         },
213         [1] = {
214                 .start  = TEGRA_SPI2_BASE,
215                 .end    = TEGRA_SPI2_BASE + TEGRA_SPI2_SIZE-1,
216                 .flags  = IORESOURCE_MEM,
217         },
218 };
219
220 static struct resource spi_resource3[] = {
221         [0] = {
222                 .start  = INT_SPI_3,
223                 .end    = INT_SPI_3,
224                 .flags  = IORESOURCE_IRQ,
225         },
226         [1] = {
227                 .start  = TEGRA_SPI3_BASE,
228                 .end    = TEGRA_SPI3_BASE + TEGRA_SPI3_SIZE-1,
229                 .flags  = IORESOURCE_MEM,
230         },
231 };
232
233 static struct resource spi_resource4[] = {
234         [0] = {
235                 .start  = INT_SPI_4,
236                 .end    = INT_SPI_4,
237                 .flags  = IORESOURCE_IRQ,
238         },
239         [1] = {
240                 .start  = TEGRA_SPI4_BASE,
241                 .end    = TEGRA_SPI4_BASE + TEGRA_SPI4_SIZE-1,
242                 .flags  = IORESOURCE_MEM,
243         },
244 };
245 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
246 static struct resource spi_resource5[] = {
247         [0] = {
248                 .start  = INT_SPI_5,
249                 .end    = INT_SPI_5,
250                 .flags  = IORESOURCE_IRQ,
251         },
252         [1] = {
253                 .start  = TEGRA_SPI5_BASE,
254                 .end    = TEGRA_SPI5_BASE + TEGRA_SPI5_SIZE-1,
255                 .flags  = IORESOURCE_MEM,
256         },
257 };
258
259 static struct resource spi_resource6[] = {
260         [0] = {
261                 .start  = INT_SPI_6,
262                 .end    = INT_SPI_6,
263                 .flags  = IORESOURCE_IRQ,
264         },
265         [1] = {
266                 .start  = TEGRA_SPI6_BASE,
267                 .end    = TEGRA_SPI6_BASE + TEGRA_SPI6_SIZE-1,
268                 .flags  = IORESOURCE_MEM,
269         },
270 };
271 #endif
272
273 struct platform_device tegra_spi_device1 = {
274         .name           = "spi_tegra",
275         .id             = 0,
276         .resource       = spi_resource1,
277         .num_resources  = ARRAY_SIZE(spi_resource1),
278         .dev            = {
279                 .coherent_dma_mask      = 0xffffffff,
280         },
281 };
282
283 struct platform_device tegra_spi_device2 = {
284         .name           = "spi_tegra",
285         .id             = 1,
286         .resource       = spi_resource2,
287         .num_resources  = ARRAY_SIZE(spi_resource2),
288         .dev            = {
289                 .coherent_dma_mask      = 0xffffffff,
290         },
291 };
292
293 struct platform_device tegra_spi_device3 = {
294         .name           = "spi_tegra",
295         .id             = 2,
296         .resource       = spi_resource3,
297         .num_resources  = ARRAY_SIZE(spi_resource3),
298         .dev            = {
299                 .coherent_dma_mask      = 0xffffffff,
300         },
301 };
302
303 struct platform_device tegra_spi_device4 = {
304         .name           = "spi_tegra",
305         .id             = 3,
306         .resource       = spi_resource4,
307         .num_resources  = ARRAY_SIZE(spi_resource4),
308         .dev            = {
309                 .coherent_dma_mask      = 0xffffffff,
310         },
311 };
312 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
313 struct platform_device tegra_spi_device5 = {
314         .name           = "spi_tegra",
315         .id             = 4,
316         .resource       = spi_resource5,
317         .num_resources  = ARRAY_SIZE(spi_resource5),
318         .dev  = {
319                 .coherent_dma_mask      = 0xffffffff,
320         },
321 };
322
323 struct platform_device tegra_spi_device6 = {
324         .name           = "spi_tegra",
325         .id             = 5,
326         .resource       = spi_resource6,
327         .num_resources  = ARRAY_SIZE(spi_resource6),
328         .dev  = {
329                 .coherent_dma_mask      = 0xffffffff,
330         },
331 };
332 #endif
333
334 struct platform_device tegra_spi_slave_device1 = {
335         .name           = "spi_slave_tegra",
336         .id             = 0,
337         .resource       = spi_resource1,
338         .num_resources  = ARRAY_SIZE(spi_resource1),
339         .dev  = {
340                 .coherent_dma_mask      = 0xffffffff,
341         },
342 };
343
344 struct platform_device tegra_spi_slave_device2 = {
345         .name           = "spi_slave_tegra",
346         .id             = 1,
347         .resource       = spi_resource2,
348         .num_resources  = ARRAY_SIZE(spi_resource2),
349         .dev  = {
350                 .coherent_dma_mask      = 0xffffffff,
351         },
352 };
353
354 struct platform_device tegra_spi_slave_device3 = {
355         .name           = "spi_slave_tegra",
356         .id             = 2,
357         .resource       = spi_resource3,
358         .num_resources  = ARRAY_SIZE(spi_resource3),
359         .dev  = {
360                 .coherent_dma_mask      = 0xffffffff,
361         },
362 };
363
364 struct platform_device tegra_spi_slave_device4 = {
365         .name           = "spi_slave_tegra",
366         .id             = 3,
367         .resource       = spi_resource4,
368         .num_resources  = ARRAY_SIZE(spi_resource4),
369         .dev  = {
370                 .coherent_dma_mask      = 0xffffffff,
371         },
372 };
373 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
374 struct platform_device tegra_spi_slave_device5 = {
375         .name           = "spi_slave_tegra",
376         .id             = 4,
377         .resource       = spi_resource5,
378         .num_resources  = ARRAY_SIZE(spi_resource5),
379         .dev  = {
380                 .coherent_dma_mask      = 0xffffffff,
381         },
382 };
383
384 struct platform_device tegra_spi_slave_device6 = {
385         .name           = "spi_slave_tegra",
386         .id             = 5,
387         .resource       = spi_resource6,
388         .num_resources  = ARRAY_SIZE(spi_resource6),
389         .dev  = {
390                 .coherent_dma_mask      = 0xffffffff,
391         },
392 };
393 #endif
394
395 static struct resource resources_nor[] = {
396         [0] = {
397                 .start = INT_SNOR,
398                 .end = INT_SNOR,
399                 .flags = IORESOURCE_IRQ,
400         },
401         [1] = {
402                 /* Map SNOR Controller */
403                 .start = TEGRA_SNOR_BASE,
404                 .end = TEGRA_SNOR_BASE + TEGRA_SNOR_SIZE - 1,
405                 .flags = IORESOURCE_MEM,
406         },
407         [2] = {
408                 /* Map the size of flash */
409                 .start = TEGRA_NOR_FLASH_BASE,
410                 .end = TEGRA_NOR_FLASH_BASE + TEGRA_NOR_FLASH_SIZE - 1,
411                 .flags = IORESOURCE_MEM,
412         }
413 };
414
415 struct platform_device tegra_nor_device = {
416         .name = "tegra-nor",
417         .id = -1,
418         .num_resources = ARRAY_SIZE(resources_nor),
419         .resource = resources_nor,
420         .dev = {
421                 .coherent_dma_mask = 0xffffffff,
422         },
423 };
424
425 static struct resource sdhci_resource1[] = {
426         [0] = {
427                 .start  = INT_SDMMC1,
428                 .end    = INT_SDMMC1,
429                 .flags  = IORESOURCE_IRQ,
430         },
431         [1] = {
432                 .start  = TEGRA_SDMMC1_BASE,
433                 .end    = TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE-1,
434                 .flags  = IORESOURCE_MEM,
435         },
436 };
437
438 static struct resource sdhci_resource2[] = {
439         [0] = {
440                 .start  = INT_SDMMC2,
441                 .end    = INT_SDMMC2,
442                 .flags  = IORESOURCE_IRQ,
443         },
444         [1] = {
445                 .start  = TEGRA_SDMMC2_BASE,
446                 .end    = TEGRA_SDMMC2_BASE + TEGRA_SDMMC2_SIZE-1,
447                 .flags  = IORESOURCE_MEM,
448         },
449 };
450
451 static struct resource sdhci_resource3[] = {
452         [0] = {
453                 .start  = INT_SDMMC3,
454                 .end    = INT_SDMMC3,
455                 .flags  = IORESOURCE_IRQ,
456         },
457         [1] = {
458                 .start  = TEGRA_SDMMC3_BASE,
459                 .end    = TEGRA_SDMMC3_BASE + TEGRA_SDMMC3_SIZE-1,
460                 .flags  = IORESOURCE_MEM,
461         },
462 };
463
464 static struct resource sdhci_resource4[] = {
465         [0] = {
466                 .start  = INT_SDMMC4,
467                 .end    = INT_SDMMC4,
468                 .flags  = IORESOURCE_IRQ,
469         },
470         [1] = {
471                 .start  = TEGRA_SDMMC4_BASE,
472                 .end    = TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE-1,
473                 .flags  = IORESOURCE_MEM,
474         },
475 };
476
477 struct platform_device tegra_pci_device = {
478         .name           = "tegra-pcie",
479         .id             = 0,
480         .resource       = 0,
481         .num_resources  = 0,
482         .dev = {
483                 .platform_data = 0,
484         },
485 };
486
487 /* board files should fill in platform_data register the devices themselvs.
488  * See board-harmony.c for an example
489  */
490 struct platform_device tegra_sdhci_device1 = {
491         .name           = "sdhci-tegra",
492         .id             = 0,
493         .resource       = sdhci_resource1,
494         .num_resources  = ARRAY_SIZE(sdhci_resource1),
495 };
496
497 struct platform_device tegra_sdhci_device2 = {
498         .name           = "sdhci-tegra",
499         .id             = 1,
500         .resource       = sdhci_resource2,
501         .num_resources  = ARRAY_SIZE(sdhci_resource2),
502 };
503
504 struct platform_device tegra_sdhci_device3 = {
505         .name           = "sdhci-tegra",
506         .id             = 2,
507         .resource       = sdhci_resource3,
508         .num_resources  = ARRAY_SIZE(sdhci_resource3),
509 };
510
511 struct platform_device tegra_sdhci_device4 = {
512         .name           = "sdhci-tegra",
513         .id             = 3,
514         .resource       = sdhci_resource4,
515         .num_resources  = ARRAY_SIZE(sdhci_resource4),
516 };
517
518 static struct resource tegra_usb1_resources[] = {
519         [0] = {
520                 .start  = TEGRA_USB_BASE,
521                 .end    = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
522                 .flags  = IORESOURCE_MEM,
523         },
524         [1] = {
525                 .start  = INT_USB,
526                 .end    = INT_USB,
527                 .flags  = IORESOURCE_IRQ,
528         },
529 };
530
531 static struct resource tegra_usb2_resources[] = {
532         [0] = {
533                 .start  = TEGRA_USB2_BASE,
534                 .end    = TEGRA_USB2_BASE + TEGRA_USB2_SIZE - 1,
535                 .flags  = IORESOURCE_MEM,
536         },
537         [1] = {
538                 .start  = INT_USB2,
539                 .end    = INT_USB2,
540                 .flags  = IORESOURCE_IRQ,
541         },
542 };
543
544 static struct resource tegra_usb3_resources[] = {
545         [0] = {
546                 .start  = TEGRA_USB3_BASE,
547                 .end    = TEGRA_USB3_BASE + TEGRA_USB3_SIZE - 1,
548                 .flags  = IORESOURCE_MEM,
549         },
550         [1] = {
551                 .start  = INT_USB3,
552                 .end    = INT_USB3,
553                 .flags  = IORESOURCE_IRQ,
554         },
555 };
556
557 static struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
558         /* All existing boards use GPIO PV0 for phy reset */
559         .reset_gpio = TEGRA_GPIO_PV0,
560         .clk = "cdev2",
561 };
562
563 static struct tegra_ehci_platform_data tegra_ehci1_pdata = {
564         .operating_mode = TEGRA_USB_OTG,
565         .power_down_on_bus_suspend = 1,
566 };
567
568 static struct tegra_ehci_platform_data tegra_ehci2_pdata = {
569         .phy_config = &tegra_ehci2_ulpi_phy_config,
570         .operating_mode = TEGRA_USB_HOST,
571         .power_down_on_bus_suspend = 1,
572 };
573
574 static struct tegra_ehci_platform_data tegra_ehci3_pdata = {
575         .operating_mode = TEGRA_USB_HOST,
576         .power_down_on_bus_suspend = 1,
577 };
578
579 static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32);
580
581 struct platform_device tegra_ehci1_device = {
582         .name   = "tegra-ehci",
583         .id     = 0,
584         .dev    = {
585                 .dma_mask       = &tegra_ehci_dmamask,
586                 .coherent_dma_mask = DMA_BIT_MASK(32),
587                 .platform_data = &tegra_ehci1_pdata,
588         },
589         .resource = tegra_usb1_resources,
590         .num_resources = ARRAY_SIZE(tegra_usb1_resources),
591 };
592
593 struct platform_device tegra_ehci2_device = {
594         .name   = "tegra-ehci",
595         .id     = 1,
596         .dev    = {
597                 .dma_mask       = &tegra_ehci_dmamask,
598                 .coherent_dma_mask = DMA_BIT_MASK(32),
599                 .platform_data = &tegra_ehci2_pdata,
600         },
601         .resource = tegra_usb2_resources,
602         .num_resources = ARRAY_SIZE(tegra_usb2_resources),
603 };
604
605 struct platform_device tegra_ehci3_device = {
606         .name   = "tegra-ehci",
607         .id     = 2,
608         .dev    = {
609                 .dma_mask       = &tegra_ehci_dmamask,
610                 .coherent_dma_mask = DMA_BIT_MASK(32),
611                 .platform_data = &tegra_ehci3_pdata,
612         },
613         .resource = tegra_usb3_resources,
614         .num_resources = ARRAY_SIZE(tegra_usb3_resources),
615 };
616
617 static struct resource tegra_pmu_resources[] = {
618         [0] = {
619                 .start  = INT_CPU0_PMU_INTR,
620                 .end    = INT_CPU0_PMU_INTR,
621                 .flags  = IORESOURCE_IRQ,
622         },
623         [1] = {
624                 .start  = INT_CPU1_PMU_INTR,
625                 .end    = INT_CPU1_PMU_INTR,
626                 .flags  = IORESOURCE_IRQ,
627         },
628 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
629         [2] = {
630                 .start  = INT_CPU2_PMU_INTR,
631                 .end    = INT_CPU2_PMU_INTR,
632                 .flags  = IORESOURCE_IRQ,
633         },
634         [3] = {
635                 .start  = INT_CPU3_PMU_INTR,
636                 .end    = INT_CPU3_PMU_INTR,
637                 .flags  = IORESOURCE_IRQ,
638         },
639 #endif
640 };
641
642 struct platform_device tegra_pmu_device = {
643         .name           = "arm-pmu",
644         .id             = ARM_PMU_DEVICE_CPU,
645         .num_resources  = ARRAY_SIZE(tegra_pmu_resources),
646         .resource       = tegra_pmu_resources,
647 };
648
649 static struct resource tegra_uarta_resources[] = {
650         [0] = {
651                 .start  = TEGRA_UARTA_BASE,
652                 .end    = TEGRA_UARTA_BASE + TEGRA_UARTA_SIZE - 1,
653                 .flags  = IORESOURCE_MEM,
654         },
655         [1] = {
656                 .start  = INT_UARTA,
657                 .end    = INT_UARTA,
658                 .flags  = IORESOURCE_IRQ,
659         },
660 };
661
662 static struct resource tegra_uartb_resources[] = {
663         [0] = {
664                 .start  = TEGRA_UARTB_BASE,
665                 .end    = TEGRA_UARTB_BASE + TEGRA_UARTB_SIZE - 1,
666                 .flags  = IORESOURCE_MEM,
667         },
668         [1] = {
669                 .start  = INT_UARTB,
670                 .end    = INT_UARTB,
671                 .flags  = IORESOURCE_IRQ,
672         },
673 };
674
675 static struct resource tegra_uartc_resources[] = {
676         [0] = {
677                 .start  = TEGRA_UARTC_BASE,
678                 .end    = TEGRA_UARTC_BASE + TEGRA_UARTC_SIZE - 1,
679                 .flags  = IORESOURCE_MEM,
680         },
681         [1] = {
682                 .start  = INT_UARTC,
683                 .end    = INT_UARTC,
684                 .flags  = IORESOURCE_IRQ,
685         },
686 };
687
688 static struct resource tegra_uartd_resources[] = {
689         [0] = {
690                 .start  = TEGRA_UARTD_BASE,
691                 .end    = TEGRA_UARTD_BASE + TEGRA_UARTD_SIZE - 1,
692                 .flags  = IORESOURCE_MEM,
693         },
694         [1] = {
695                 .start  = INT_UARTD,
696                 .end    = INT_UARTD,
697                 .flags  = IORESOURCE_IRQ,
698         },
699 };
700
701 static struct resource tegra_uarte_resources[] = {
702         [0] = {
703                 .start  = TEGRA_UARTE_BASE,
704                 .end    = TEGRA_UARTE_BASE + TEGRA_UARTE_SIZE - 1,
705                 .flags  = IORESOURCE_MEM,
706         },
707         [1] = {
708                 .start  = INT_UARTE,
709                 .end    = INT_UARTE,
710                 .flags  = IORESOURCE_IRQ,
711         },
712 };
713
714 struct platform_device tegra_uarta_device = {
715         .name   = "tegra_uart",
716         .id     = 0,
717         .num_resources  = ARRAY_SIZE(tegra_uarta_resources),
718         .resource       = tegra_uarta_resources,
719         .dev    = {
720                 .coherent_dma_mask      = DMA_BIT_MASK(32),
721         },
722 };
723
724 struct platform_device tegra_uartb_device = {
725         .name   = "tegra_uart",
726         .id     = 1,
727         .num_resources  = ARRAY_SIZE(tegra_uartb_resources),
728         .resource       = tegra_uartb_resources,
729         .dev    = {
730                 .coherent_dma_mask      = DMA_BIT_MASK(32),
731         },
732 };
733
734 struct platform_device tegra_uartc_device = {
735         .name   = "tegra_uart",
736         .id     = 2,
737         .num_resources  = ARRAY_SIZE(tegra_uartc_resources),
738         .resource       = tegra_uartc_resources,
739         .dev    = {
740                 .coherent_dma_mask      = DMA_BIT_MASK(32),
741         },
742 };
743
744 struct platform_device tegra_uartd_device = {
745         .name   = "tegra_uart",
746         .id     = 3,
747         .num_resources  = ARRAY_SIZE(tegra_uartd_resources),
748         .resource       = tegra_uartd_resources,
749         .dev    = {
750                 .coherent_dma_mask      = DMA_BIT_MASK(32),
751         },
752 };
753
754 struct platform_device tegra_uarte_device = {
755         .name   = "tegra_uart",
756         .id     = 4,
757         .num_resources  = ARRAY_SIZE(tegra_uarte_resources),
758         .resource       = tegra_uarte_resources,
759         .dev    = {
760                 .coherent_dma_mask      = DMA_BIT_MASK(32),
761         },
762 };
763
764 static struct plat_serial8250_port debug_uarta_platform_data[] = {
765         {
766                 .membase        = IO_ADDRESS(TEGRA_UARTA_BASE),
767                 .mapbase        = TEGRA_UARTA_BASE,
768                 .irq            = INT_UARTA,
769                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
770                 .type           = PORT_TEGRA,
771                 .iotype         = UPIO_MEM,
772                 .regshift       = 2,
773                 .uartclk        = UART_SOURCE_RATE,
774         },
775         {
776                 .flags          = 0,
777         },
778 };
779
780 static struct plat_serial8250_port debug_uartb_platform_data[] = {
781         {
782                 .membase        = IO_ADDRESS(TEGRA_UARTB_BASE),
783                 .mapbase        = TEGRA_UARTB_BASE,
784                 .irq            = INT_UARTB,
785                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
786                 .type           = PORT_TEGRA,
787                 .iotype         = UPIO_MEM,
788                 .regshift       = 2,
789                 .uartclk        = UART_SOURCE_RATE,
790         },
791         {
792                 .flags          = 0,
793         },
794 };
795
796 static struct plat_serial8250_port debug_uartc_platform_data[] = {
797         {
798                 .membase        = IO_ADDRESS(TEGRA_UARTC_BASE),
799                 .mapbase        = TEGRA_UARTC_BASE,
800                 .irq            = INT_UARTC,
801                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
802                 .type           = PORT_TEGRA,
803                 .iotype         = UPIO_MEM,
804                 .regshift       = 2,
805                 .uartclk        = UART_SOURCE_RATE,
806         },
807         {
808                 .flags          = 0,
809         },
810 };
811
812 static struct plat_serial8250_port debug_uartd_platform_data[] = {
813         {
814                 .membase        = IO_ADDRESS(TEGRA_UARTD_BASE),
815                 .mapbase        = TEGRA_UARTD_BASE,
816                 .irq            = INT_UARTD,
817                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
818                 .type           = PORT_TEGRA,
819                 .iotype         = UPIO_MEM,
820                 .regshift       = 2,
821                 .uartclk        = UART_SOURCE_RATE,
822         },
823         {
824                 .flags          = 0,
825         },
826 };
827
828 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
829 static struct plat_serial8250_port debug_uarte_platform_data[] = {
830         {
831                 .membase        = IO_ADDRESS(TEGRA_UARTE_BASE),
832                 .mapbase        = TEGRA_UARTE_BASE,
833                 .irq            = INT_UARTE,
834                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
835                 .type           = PORT_TEGRA,
836                 .iotype         = UPIO_MEM,
837                 .regshift       = 2,
838                 .uartclk        = UART_SOURCE_RATE,
839         },
840         {
841                 .flags          = 0,
842         },
843 };
844 #endif
845
846 struct platform_device debug_uarta_device = {
847         .name = "serial8250",
848         .id = PLAT8250_DEV_PLATFORM,
849         .dev = {
850                 .platform_data = debug_uarta_platform_data,
851         },
852 };
853
854 struct platform_device debug_uartb_device = {
855         .name = "serial8250",
856         .id = PLAT8250_DEV_PLATFORM,
857         .dev = {
858                 .platform_data = debug_uartb_platform_data,
859         },
860 };
861
862 struct platform_device debug_uartc_device = {
863         .name = "serial8250",
864         .id = PLAT8250_DEV_PLATFORM,
865         .dev = {
866                 .platform_data = debug_uartc_platform_data,
867         },
868 };
869
870 struct platform_device debug_uartd_device = {
871         .name = "serial8250",
872         .id = PLAT8250_DEV_PLATFORM,
873         .dev = {
874                 .platform_data = debug_uartd_platform_data,
875         },
876 };
877
878 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
879 struct platform_device debug_uarte_device = {
880         .name = "serial8250",
881         .id = PLAT8250_DEV_PLATFORM,
882         .dev = {
883                 .platform_data = debug_uarte_platform_data,
884         },
885 };
886 #endif
887
888 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
889 static struct resource i2s_resource1[] = {
890         [0] = {
891                 .start  = INT_I2S1,
892                 .end    = INT_I2S1,
893                 .flags  = IORESOURCE_IRQ
894         },
895         [1] = {
896                 .start  = TEGRA_DMA_REQ_SEL_I2S_1,
897                 .end    = TEGRA_DMA_REQ_SEL_I2S_1,
898                 .flags  = IORESOURCE_DMA
899         },
900         [2] = {
901                 .start  = TEGRA_I2S1_BASE,
902                 .end    = TEGRA_I2S1_BASE + TEGRA_I2S1_SIZE - 1,
903                 .flags  = IORESOURCE_MEM
904         }
905 };
906
907 struct platform_device tegra_i2s_device1 = {
908         .name           = "tegra20-i2s",
909         .id             = 0,
910         .resource       = i2s_resource1,
911         .num_resources  = ARRAY_SIZE(i2s_resource1),
912 };
913
914 static struct resource i2s_resource2[] = {
915         [0] = {
916                 .start  = INT_I2S2,
917                 .end    = INT_I2S2,
918                 .flags  = IORESOURCE_IRQ
919         },
920         [1] = {
921                 .start  = TEGRA_DMA_REQ_SEL_I2S2_1,
922                 .end    = TEGRA_DMA_REQ_SEL_I2S2_1,
923                 .flags  = IORESOURCE_DMA
924         },
925         [2] = {
926                 .start  = TEGRA_I2S2_BASE,
927                 .end    = TEGRA_I2S2_BASE + TEGRA_I2S2_SIZE - 1,
928                 .flags  = IORESOURCE_MEM
929         }
930 };
931
932 struct platform_device tegra_i2s_device2 = {
933         .name           = "tegra20-i2s",
934         .id             = 1,
935         .resource       = i2s_resource2,
936         .num_resources  = ARRAY_SIZE(i2s_resource2),
937 };
938 #else
939 static struct resource i2s_resource0[] = {
940         [0] = {
941                 .start  = TEGRA_I2S0_BASE,
942                 .end    = TEGRA_I2S0_BASE + TEGRA_I2S0_SIZE - 1,
943                 .flags  = IORESOURCE_MEM
944         }
945 };
946
947 struct platform_device tegra_i2s_device0 = {
948         .name           = "tegra30-i2s",
949         .id             = 0,
950         .resource       = i2s_resource0,
951         .num_resources  = ARRAY_SIZE(i2s_resource0),
952 };
953
954 static struct resource i2s_resource1[] = {
955         [0] = {
956                 .start  = TEGRA_I2S1_BASE,
957                 .end    = TEGRA_I2S1_BASE + TEGRA_I2S1_SIZE - 1,
958                 .flags  = IORESOURCE_MEM
959         }
960 };
961
962 struct platform_device tegra_i2s_device1 = {
963         .name           = "tegra30-i2s",
964         .id             = 1,
965         .resource       = i2s_resource1,
966         .num_resources  = ARRAY_SIZE(i2s_resource1),
967 };
968
969 static struct resource i2s_resource2[] = {
970         [0] = {
971                 .start  = TEGRA_I2S2_BASE,
972                 .end    = TEGRA_I2S2_BASE + TEGRA_I2S2_SIZE - 1,
973                 .flags  = IORESOURCE_MEM
974         }
975 };
976
977 struct platform_device tegra_i2s_device2 = {
978         .name           = "tegra30-i2s",
979         .id             = 2,
980         .resource       = i2s_resource2,
981         .num_resources  = ARRAY_SIZE(i2s_resource2),
982 };
983
984 static struct resource i2s_resource3[] = {
985         [0] = {
986                 .start  = TEGRA_I2S3_BASE,
987                 .end    = TEGRA_I2S3_BASE + TEGRA_I2S3_SIZE - 1,
988                 .flags  = IORESOURCE_MEM
989         }
990 };
991
992 struct platform_device tegra_i2s_device3 = {
993         .name           = "tegra30-i2s",
994         .id             = 3,
995         .resource       = i2s_resource3,
996         .num_resources  = ARRAY_SIZE(i2s_resource3),
997 };
998
999 static struct resource i2s_resource4[] = {
1000         [0] = {
1001                 .start  = TEGRA_I2S4_BASE,
1002                 .end    = TEGRA_I2S4_BASE + TEGRA_I2S4_SIZE - 1,
1003                 .flags  = IORESOURCE_MEM
1004         }
1005 };
1006
1007 struct platform_device tegra_i2s_device4 = {
1008         .name           = "tegra30-i2s",
1009         .id             = 4,
1010         .resource       = i2s_resource4,
1011         .num_resources  = ARRAY_SIZE(i2s_resource4),
1012 };
1013 #endif
1014
1015 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1016 static struct resource spdif_resource[] = {
1017         [0] = {
1018                 .start  = INT_SPDIF,
1019                 .end    = INT_SPDIF,
1020                 .flags  = IORESOURCE_IRQ
1021         },
1022         [1] = {
1023                 .start  = TEGRA_DMA_REQ_SEL_SPD_I,
1024                 .end    = TEGRA_DMA_REQ_SEL_SPD_I,
1025                 .flags  = IORESOURCE_DMA
1026         },
1027         [2] = {
1028                 .start  = TEGRA_SPDIF_BASE,
1029                 .end    = TEGRA_SPDIF_BASE + TEGRA_SPDIF_SIZE - 1,
1030                 .flags  = IORESOURCE_MEM
1031         }
1032 };
1033
1034 struct platform_device tegra_spdif_device = {
1035         .name           = "tegra20-spdif",
1036         .id             = -1,
1037         .resource       = spdif_resource,
1038         .num_resources  = ARRAY_SIZE(spdif_resource),
1039 };
1040 #else
1041 static struct resource spdif_resource[] = {
1042         [0] = {
1043                 .start  = TEGRA_SPDIF_BASE,
1044                 .end    = TEGRA_SPDIF_BASE + TEGRA_SPDIF_SIZE - 1,
1045                 .flags  = IORESOURCE_MEM
1046         }
1047 };
1048
1049 struct platform_device tegra_spdif_device = {
1050         .name           = "tegra30-spdif",
1051         .id             = -1,
1052         .resource       = spdif_resource,
1053         .num_resources  = ARRAY_SIZE(spdif_resource),
1054 };
1055 #endif
1056
1057 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1058 static struct resource ahub_resource[] = {
1059         [0] = {
1060                 .start  = TEGRA_APBIF0_BASE,
1061                 .end    = TEGRA_APBIF3_BASE + TEGRA_APBIF3_SIZE - 1,
1062                 .flags  = IORESOURCE_MEM
1063         },
1064         [1] = {
1065                 .start  = TEGRA_AHUB_BASE,
1066                 .end    = TEGRA_AHUB_BASE + TEGRA_AHUB_SIZE - 1,
1067                 .flags  = IORESOURCE_MEM
1068         }
1069 };
1070
1071 struct platform_device tegra_ahub_device = {
1072         .name   = "tegra30-ahub",
1073         .id     = -1,
1074         .resource       = ahub_resource,
1075         .num_resources  = ARRAY_SIZE(ahub_resource),
1076 };
1077
1078 static struct resource dam_resource0[] = {
1079         [0] = {
1080                 .start = TEGRA_DAM0_BASE,
1081                 .end   = TEGRA_DAM0_BASE + TEGRA_DAM0_SIZE - 1,
1082                 .flags = IORESOURCE_MEM
1083         }
1084 };
1085
1086 struct platform_device tegra_dam_device0 = {
1087         .name = "tegra30-dam",
1088         .id = 0,
1089         .resource      = dam_resource0,
1090         .num_resources = ARRAY_SIZE(dam_resource0),
1091 };
1092
1093 static struct resource dam_resource1[] = {
1094         [0] = {
1095                 .start = TEGRA_DAM1_BASE,
1096                 .end   = TEGRA_DAM1_BASE + TEGRA_DAM1_SIZE - 1,
1097                 .flags = IORESOURCE_MEM
1098         }
1099 };
1100
1101 struct platform_device tegra_dam_device1 = {
1102         .name = "tegra30-dam",
1103         .id = 1,
1104         .resource      = dam_resource1,
1105         .num_resources = ARRAY_SIZE(dam_resource1),
1106 };
1107
1108 static struct resource dam_resource2[] = {
1109         [0] = {
1110                 .start = TEGRA_DAM2_BASE,
1111                 .end   = TEGRA_DAM2_BASE + TEGRA_DAM2_SIZE - 1,
1112                 .flags = IORESOURCE_MEM
1113         }
1114 };
1115
1116 struct platform_device tegra_dam_device2 = {
1117         .name = "tegra30-dam",
1118         .id = 2,
1119         .resource      = dam_resource2,
1120         .num_resources = ARRAY_SIZE(dam_resource2),
1121 };
1122
1123 static u64 tegra_hda_dma_mask = DMA_BIT_MASK(32);
1124 static struct resource hda_platform_resources[] = {
1125         [0] = {
1126                 .start  = TEGRA_HDA_BASE,
1127                 .end    = TEGRA_HDA_BASE + TEGRA_HDA_SIZE - 1,
1128                 .flags  = IORESOURCE_MEM
1129         },
1130         [1] = {
1131                 .start  = INT_HDA,
1132                 .end    = INT_HDA,
1133                 .flags  = IORESOURCE_IRQ
1134         },
1135 };
1136
1137 struct platform_device tegra_hda_device = {
1138         .name           = "tegra30-hda",
1139         .id             = -1,
1140         .dev = {
1141                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1142                 .dma_mask               = &tegra_hda_dma_mask,
1143         },
1144         .resource       = hda_platform_resources,
1145         .num_resources  = ARRAY_SIZE(hda_platform_resources),
1146 };
1147 #endif
1148
1149 struct platform_device spdif_dit_device = {
1150         .name = "spdif-dit",
1151         .id = 0,
1152 };
1153
1154 struct platform_device bluetooth_dit_device = {
1155         .name = "spdif-dit",
1156         .id = 1,
1157 };
1158
1159 struct platform_device baseband_dit_device = {
1160         .name = "spdif-dit",
1161         .id = 2,
1162 };
1163
1164 struct platform_device tegra_pcm_device = {
1165         .name = "tegra-pcm-audio",
1166         .id = -1,
1167 };
1168
1169 static struct resource w1_resources[] = {
1170         [0] = {
1171                 .start = INT_OWR,
1172                 .end   = INT_OWR,
1173                 .flags = IORESOURCE_IRQ
1174         },
1175         [1] = {
1176                 .start = TEGRA_OWR_BASE,
1177                 .end = TEGRA_OWR_BASE + TEGRA_OWR_SIZE - 1,
1178                 .flags = IORESOURCE_MEM
1179         }
1180 };
1181
1182 struct platform_device tegra_w1_device = {
1183         .name          = "tegra_w1",
1184         .id            = -1,
1185         .resource      = w1_resources,
1186         .num_resources = ARRAY_SIZE(w1_resources),
1187 };
1188
1189 static struct resource tegra_udc_resources[] = {
1190         [0] = {
1191                 .start  = TEGRA_USB_BASE,
1192                 .end    = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
1193                 .flags  = IORESOURCE_MEM,
1194         },
1195         [1] = {
1196                 .start  = INT_USB,
1197                 .end    = INT_USB,
1198                 .flags  = IORESOURCE_IRQ,
1199         },
1200 };
1201
1202 static u64 tegra_udc_dmamask = DMA_BIT_MASK(32);
1203
1204 static struct fsl_usb2_platform_data tegra_udc_pdata = {
1205         .operating_mode = FSL_USB2_DR_DEVICE,
1206         .phy_mode       = FSL_USB2_PHY_UTMI,
1207 };
1208
1209 struct platform_device tegra_udc_device = {
1210         .name   = "fsl-tegra-udc",
1211         .id     = -1,
1212         .dev    = {
1213                 .dma_mask       = &tegra_udc_dmamask,
1214                 .coherent_dma_mask = DMA_BIT_MASK(32),
1215                 .platform_data  = &tegra_udc_pdata,
1216         },
1217         .resource = tegra_udc_resources,
1218         .num_resources = ARRAY_SIZE(tegra_udc_resources),
1219 };
1220
1221 static struct resource tegra_otg_resources[] = {
1222         [0] = {
1223                 .start  = TEGRA_USB_BASE,
1224                 .end    = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
1225                 .flags  = IORESOURCE_MEM,
1226         },
1227         [1] = {
1228                 .start  = INT_USB,
1229                 .end    = INT_USB,
1230                 .flags  = IORESOURCE_IRQ,
1231         },
1232 };
1233
1234 struct platform_device tegra_otg_device = {
1235         .name           = "tegra-otg",
1236         .id             = -1,
1237         .resource       = tegra_otg_resources,
1238         .num_resources  = ARRAY_SIZE(tegra_otg_resources),
1239 };
1240
1241 #ifdef CONFIG_SATA_AHCI_TEGRA
1242 static u64 tegra_sata_dma_mask = DMA_BIT_MASK(32);
1243
1244 static struct resource tegra_sata_resources[] = {
1245         [0] = {
1246                 .start = TEGRA_SATA_BAR5_BASE,
1247                 .end = TEGRA_SATA_BAR5_BASE + TEGRA_SATA_BAR5_SIZE - 1,
1248                 .flags = IORESOURCE_MEM,
1249         },
1250         [1] = {
1251                 .start = TEGRA_SATA_CONFIG_BASE,
1252                 .end = TEGRA_SATA_CONFIG_BASE + TEGRA_SATA_CONFIG_SIZE - 1,
1253                 .flags = IORESOURCE_MEM,
1254         },
1255         [2] = {
1256                 .start = INT_SATA_CTL,
1257                 .end = INT_SATA_CTL,
1258                 .flags = IORESOURCE_IRQ,
1259         },
1260 };
1261
1262 struct platform_device tegra_sata_device = {
1263         .name   = "tegra-sata",
1264         .id     = 0,
1265         .dev    = {
1266                 .platform_data = 0,
1267                 .coherent_dma_mask = DMA_BIT_MASK(32),
1268                 .dma_mask = &tegra_sata_dma_mask,
1269         },
1270         .resource = tegra_sata_resources,
1271         .num_resources = ARRAY_SIZE(tegra_sata_resources),
1272 };
1273 #endif
1274
1275 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1276 static struct resource das_resource[] = {
1277         [0] = {
1278                 .start  = TEGRA_APB_MISC_DAS_BASE,
1279                 .end    = TEGRA_APB_MISC_DAS_BASE + TEGRA_APB_MISC_DAS_SIZE - 1,
1280                 .flags  = IORESOURCE_MEM
1281         }
1282 };
1283
1284 struct platform_device tegra_das_device = {
1285         .name           = "tegra20-das",
1286         .id             = -1,
1287         .resource       = das_resource,
1288         .num_resources  = ARRAY_SIZE(das_resource),
1289 };
1290 #endif
1291
1292 #if defined(CONFIG_TEGRA_IOVMM_GART)
1293 static struct resource tegra_gart_resources[] = {
1294         [0] = {
1295                 .name   = "mc",
1296                 .flags  = IORESOURCE_MEM,
1297                 .start  = TEGRA_MC_BASE,
1298                 .end    = TEGRA_MC_BASE + TEGRA_MC_SIZE - 1,
1299         },
1300         [1] = {
1301                 .name   = "gart",
1302                 .flags  = IORESOURCE_MEM,
1303                 .start  = TEGRA_GART_BASE,
1304                 .end    = TEGRA_GART_BASE + TEGRA_GART_SIZE - 1,
1305         }
1306 };
1307
1308 struct platform_device tegra_gart_device = {
1309         .name           = "tegra_gart",
1310         .id             = -1,
1311         .num_resources  = ARRAY_SIZE(tegra_gart_resources),
1312         .resource       = tegra_gart_resources
1313 };
1314 #endif
1315
1316 #if defined(CONFIG_TEGRA_IOVMM_SMMU) || defined(CONFIG_TEGRA_IOMMU_SMMU)
1317 static struct resource tegra_smmu_resources[] = {
1318         [0] = {
1319                 .name   = "mc",
1320                 .flags  = IORESOURCE_MEM,
1321                 .start  = TEGRA_MC_BASE,
1322                 .end    = TEGRA_MC_BASE + TEGRA_MC_SIZE - 1,
1323         },
1324         [1] = {
1325                 .name   = "ahbarb",
1326                 .flags  = IORESOURCE_MEM,
1327                 .start  = TEGRA_AHB_ARB_BASE,
1328                 .end    = TEGRA_AHB_ARB_BASE + TEGRA_AHB_ARB_SIZE - 1,
1329         }
1330 };
1331
1332 struct platform_device tegra_smmu_device = {
1333         .name           = "tegra_smmu",
1334         .id             = -1,
1335         .num_resources  = ARRAY_SIZE(tegra_smmu_resources),
1336         .resource       = tegra_smmu_resources
1337 };
1338
1339
1340 static struct tegra_smmu_window tegra_smmu[] = {
1341         [0] = {
1342                 .start  = TEGRA_SMMU_BASE,
1343                 .end    = TEGRA_SMMU_BASE + TEGRA_SMMU_SIZE - 1,
1344         },
1345 };
1346
1347 struct tegra_smmu_window *tegra_smmu_window(int wnum)
1348 {
1349         return &tegra_smmu[wnum];
1350 }
1351
1352 int tegra_smmu_window_count(void)
1353 {
1354         return ARRAY_SIZE(tegra_smmu);
1355 }
1356 #endif
1357
1358 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
1359 #define CLK_RESET_RST_SOURCE    0x0
1360 static struct resource tegra_wdt_resources[] = {
1361         [0] = {
1362                 .start  = TEGRA_CLK_RESET_BASE + CLK_RESET_RST_SOURCE,
1363                 .end    = TEGRA_CLK_RESET_BASE + CLK_RESET_RST_SOURCE + 4 - 1,
1364                 .flags  = IORESOURCE_MEM,
1365         },
1366         [1] = {
1367                 .start  = TEGRA_TMR1_BASE,
1368                 .end    = TEGRA_TMR1_BASE + TEGRA_TMR1_SIZE - 1,
1369                 .flags  = IORESOURCE_MEM,
1370         },
1371         [2] = {
1372                 .start  = INT_TMR1,
1373                 .end    = INT_TMR1,
1374                 .flags  = IORESOURCE_IRQ,
1375         },
1376 };
1377 #else
1378 static struct resource tegra_wdt_resources[] = {
1379         [0] = {
1380                 .start  = TEGRA_WDT0_BASE,
1381                 .end    = TEGRA_WDT0_BASE + TEGRA_WDT0_SIZE - 1,
1382                 .flags  = IORESOURCE_MEM,
1383         },
1384         [1] = {
1385                 .start  = TEGRA_TMR10_BASE,
1386                 .end    = TEGRA_TMR10_BASE + TEGRA_TMR10_SIZE - 1,
1387                 .flags  = IORESOURCE_MEM,
1388         },
1389         [2] = {
1390                 .start  = INT_WDT_CPU,
1391                 .end    = INT_WDT_CPU,
1392                 .flags  = IORESOURCE_IRQ,
1393         },
1394 };
1395 #endif
1396
1397 struct platform_device tegra_wdt_device = {
1398         .name           = "tegra_wdt",
1399         .id             = -1,
1400         .num_resources  = ARRAY_SIZE(tegra_wdt_resources),
1401         .resource       = tegra_wdt_resources,
1402 };
1403
1404 static struct resource tegra_pwfm0_resource = {
1405         .start  = TEGRA_PWFM0_BASE,
1406         .end    = TEGRA_PWFM0_BASE + TEGRA_PWFM0_SIZE - 1,
1407         .flags  = IORESOURCE_MEM,
1408 };
1409
1410 static struct resource tegra_pwfm1_resource = {
1411         .start  = TEGRA_PWFM1_BASE,
1412         .end    = TEGRA_PWFM1_BASE + TEGRA_PWFM1_SIZE - 1,
1413         .flags  = IORESOURCE_MEM,
1414 };
1415
1416 static struct resource tegra_pwfm2_resource = {
1417         .start  = TEGRA_PWFM2_BASE,
1418         .end    = TEGRA_PWFM2_BASE + TEGRA_PWFM2_SIZE - 1,
1419         .flags  = IORESOURCE_MEM,
1420 };
1421
1422 static struct resource tegra_pwfm3_resource = {
1423         .start  = TEGRA_PWFM3_BASE,
1424         .end    = TEGRA_PWFM3_BASE + TEGRA_PWFM3_SIZE - 1,
1425         .flags  = IORESOURCE_MEM,
1426 };
1427
1428 struct platform_device tegra_pwfm0_device = {
1429         .name           = "tegra_pwm",
1430         .id             = 0,
1431         .num_resources  = 1,
1432         .resource       = &tegra_pwfm0_resource,
1433 };
1434
1435 struct platform_device tegra_pwfm1_device = {
1436         .name           = "tegra_pwm",
1437         .id             = 1,
1438         .num_resources  = 1,
1439         .resource       = &tegra_pwfm1_resource,
1440 };
1441
1442 struct platform_device tegra_pwfm2_device = {
1443         .name           = "tegra_pwm",
1444         .id             = 2,
1445         .num_resources  = 1,
1446         .resource       = &tegra_pwfm2_resource,
1447 };
1448
1449 struct platform_device tegra_pwfm3_device = {
1450         .name           = "tegra_pwm",
1451         .id             = 3,
1452         .num_resources  = 1,
1453         .resource       = &tegra_pwfm3_resource,
1454 };
1455
1456 static struct resource tegra_grhost_resources[] = {
1457         {
1458                 .start = TEGRA_HOST1X_BASE,
1459                 .end = TEGRA_HOST1X_BASE + TEGRA_HOST1X_SIZE - 1,
1460                 .flags = IORESOURCE_MEM,
1461         },
1462         {
1463                 .start = TEGRA_DISPLAY_BASE,
1464                 .end = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE - 1,
1465                 .flags = IORESOURCE_MEM,
1466         },
1467         {
1468                 .start = TEGRA_DISPLAY2_BASE,
1469                 .end = TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1,
1470                 .flags = IORESOURCE_MEM,
1471         },
1472         {
1473                 .start = TEGRA_VI_BASE,
1474                 .end = TEGRA_VI_BASE + TEGRA_VI_SIZE - 1,
1475                 .flags = IORESOURCE_MEM,
1476         },
1477         {
1478                 .start = TEGRA_ISP_BASE,
1479                 .end = TEGRA_ISP_BASE + TEGRA_ISP_SIZE - 1,
1480                 .flags = IORESOURCE_MEM,
1481         },
1482         {
1483                 .start = TEGRA_MPE_BASE,
1484                 .end = TEGRA_MPE_BASE + TEGRA_MPE_SIZE - 1,
1485                 .flags = IORESOURCE_MEM,
1486         },
1487         {
1488                 .start = INT_SYNCPT_THRESH_BASE,
1489                 .end = INT_SYNCPT_THRESH_BASE + INT_SYNCPT_THRESH_NR - 1,
1490                 .flags = IORESOURCE_IRQ,
1491         },
1492         {
1493                 .start = INT_HOST1X_MPCORE_GENERAL,
1494                 .end = INT_HOST1X_MPCORE_GENERAL,
1495                 .flags = IORESOURCE_IRQ,
1496         },
1497 };
1498
1499 struct platform_device tegra_grhost_device = {
1500         .name = "tegra_grhost",
1501         .id = -1,
1502         .resource = tegra_grhost_resources,
1503         .num_resources = ARRAY_SIZE(tegra_grhost_resources),
1504 };
1505
1506 static struct tegra_avp_platform_data tegra_avp_pdata = {
1507 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1508         .emc_clk_rate = ULONG_MAX,
1509 #else
1510         .emc_clk_rate = 200000000,
1511 #endif
1512 };
1513
1514 struct resource tegra_nvavp_resources[] = {
1515         [0] = {
1516                 .start  = INT_SHR_SEM_INBOX_IBF,
1517                 .end    = INT_SHR_SEM_INBOX_IBF,
1518                 .flags  = IORESOURCE_IRQ,
1519                 .name   = "mbox_from_nvavp_pending",
1520         },
1521 };
1522
1523 struct nvhost_device nvavp_device = {
1524         .name           = "nvavp",
1525         .id             = -1,
1526         .resource       = tegra_nvavp_resources,
1527         .num_resources  = ARRAY_SIZE(tegra_nvavp_resources),
1528 };
1529
1530 static struct resource tegra_avp_resources[] = {
1531         [0] = {
1532                 .start  = INT_SHR_SEM_INBOX_IBF,
1533                 .end    = INT_SHR_SEM_INBOX_IBF,
1534                 .flags  = IORESOURCE_IRQ,
1535                 .name   = "mbox_from_avp_pending",
1536         },
1537 };
1538
1539 struct platform_device tegra_avp_device = {
1540         .name           = "tegra-avp",
1541         .id             = -1,
1542         .num_resources  = ARRAY_SIZE(tegra_avp_resources),
1543         .resource       = tegra_avp_resources,
1544         .dev  = {
1545                 .coherent_dma_mask      = 0xffffffffULL,
1546                 .platform_data          = &tegra_avp_pdata,
1547         },
1548 };
1549
1550 static struct resource tegra_aes_resources[] = {
1551         {
1552                 .start  = TEGRA_VDE_BASE,
1553                 .end    = TEGRA_VDE_BASE + TEGRA_VDE_SIZE - 1,
1554                 .flags  = IORESOURCE_MEM,
1555         },
1556         {
1557                 .start  = TEGRA_BSEA_BASE,
1558                 .end    = TEGRA_BSEA_BASE + TEGRA_BSEA_SIZE - 1,
1559                 .flags  = IORESOURCE_MEM,
1560         },
1561 };
1562
1563 static u64 tegra_aes_dma_mask = DMA_BIT_MASK(32);
1564
1565 struct platform_device tegra_aes_device = {
1566         .name           = "tegra-aes",
1567         .id             = -1,
1568         .resource       = tegra_aes_resources,
1569         .num_resources  = ARRAY_SIZE(tegra_aes_resources),
1570         .dev    = {
1571                 .dma_mask = &tegra_aes_dma_mask,
1572                 .coherent_dma_mask = DMA_BIT_MASK(32),
1573         },
1574 };
1575
1576 static struct resource tegra_kbc_resources[] = {
1577         [0] = {
1578                 .start = TEGRA_KBC_BASE,
1579                 .end   = TEGRA_KBC_BASE + TEGRA_KBC_SIZE - 1,
1580                 .flags = IORESOURCE_MEM,
1581         },
1582         [1] = {
1583                 .start = INT_KBC,
1584                 .end   = INT_KBC,
1585                 .flags = IORESOURCE_IRQ,
1586         },
1587 };
1588
1589 struct platform_device tegra_kbc_device = {
1590         .name = "tegra-kbc",
1591         .id = -1,
1592         .resource = tegra_kbc_resources,
1593         .num_resources = ARRAY_SIZE(tegra_kbc_resources),
1594         .dev = {
1595                 .platform_data = 0,
1596         },
1597 };
1598
1599 #if defined(CONFIG_ARCH_TEGRA_3x_SOC)
1600 static struct resource tegra_tsensor_resources[]= {
1601         {
1602                 .start  = TEGRA_TSENSOR_BASE,
1603                 .end    = TEGRA_TSENSOR_BASE + TEGRA_TSENSOR_SIZE - 1,
1604                 .flags  = IORESOURCE_MEM,
1605         },
1606         {
1607                 .start  = INT_TSENSOR,
1608                 .end    = INT_TSENSOR,
1609                 .flags  = IORESOURCE_IRQ,
1610         },
1611         {
1612                 .start  = TEGRA_PMC_BASE + 0x1B0,
1613                 /* 2 pmc registers mapped */
1614                 .end    = TEGRA_PMC_BASE + 0x1B0 + (2 * 4),
1615                 .flags  = IORESOURCE_MEM,
1616         },
1617 };
1618
1619 struct platform_device tegra_tsensor_device = {
1620         .name   = "tegra-tsensor",
1621         .id     = -1,
1622         .num_resources  = ARRAY_SIZE(tegra_tsensor_resources),
1623         .resource       = tegra_tsensor_resources,
1624         .dev = {
1625                 .platform_data = 0,
1626         },
1627 };
1628 #endif
1629
1630 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1631 static u64 tegra_se_dma_mask = DMA_BIT_MASK(32);
1632
1633 struct resource tegra_se_resources[] = {
1634         [0] = {
1635                 .start = TEGRA_SE_BASE,
1636                 .end = TEGRA_SE_BASE + TEGRA_SE_SIZE - 1,
1637                 .flags = IORESOURCE_MEM,
1638         },
1639         [1] = {
1640                 .start  = TEGRA_PMC_BASE,
1641                 .end    = TEGRA_PMC_BASE + SZ_256 - 1,
1642                 .flags  = IORESOURCE_MEM,
1643         },
1644         [2] = {
1645                 .start = INT_SE,
1646                 .end = INT_SE,
1647                 .flags = IORESOURCE_IRQ,
1648         },
1649 };
1650
1651 struct platform_device tegra_se_device = {
1652         .name = "tegra-se",
1653         .id = -1,
1654         .dev = {
1655                 .coherent_dma_mask = DMA_BIT_MASK(32),
1656                 .dma_mask = &tegra_se_dma_mask,
1657         },
1658         .resource = tegra_se_resources,
1659         .num_resources = ARRAY_SIZE(tegra_se_resources),
1660 };
1661 #endif
1662