ARM: tegra: Fix build break for T30
[linux-2.6.git] / arch / arm / mach-tegra / devices.c
1 /*
2  * Copyright (C) 2010,2011 Google, Inc.
3  *
4  * Author:
5  *      Colin Cross <ccross@android.com>
6  *      Erik Gilling <ccross@android.com>
7  *
8  * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
9  *
10  * This software is licensed under the terms of the GNU General Public
11  * License version 2, as published by the Free Software Foundation, and
12  * may be copied, distributed, and modified under those terms.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  */
20
21
22 #include <linux/resource.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/fsl_devices.h>
25 #include <linux/serial_8250.h>
26 #include <linux/i2c-tegra.h>
27 #include <linux/platform_data/tegra_usb.h>
28 #include <linux/tegra_avp.h>
29 #include <linux/nvhost.h>
30 #include <linux/clk.h>
31 #include <asm/pmu.h>
32 #include <mach/irqs.h>
33 #include <mach/iomap.h>
34 #include <mach/dma.h>
35 #include <mach/usb_phy.h>
36 #include <mach/tegra_smmu.h>
37
38 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
39 #include <asm/dma-iommu.h>
40 #endif
41
42 #include "gpio-names.h"
43 #include "devices.h"
44
45 static struct resource emc_resource[] = {
46         [0] = {
47                 .start  = TEGRA_EMC_BASE,
48                 .end    = TEGRA_EMC_BASE + TEGRA_EMC_SIZE-1,
49                 .flags  = IORESOURCE_MEM,
50         }
51 };
52
53 struct platform_device tegra_emc_device = {
54         .name           = "tegra-emc",
55         .id             = -1,
56         .resource       = emc_resource,
57         .num_resources  = ARRAY_SIZE(emc_resource),
58 };
59
60 static struct resource gpio_resource[] = {
61         [0] = {
62                 .start  = TEGRA_GPIO_BASE,
63                 .end    = TEGRA_GPIO_BASE + TEGRA_GPIO_SIZE-1,
64                 .flags  = IORESOURCE_MEM,
65         },
66         [1] = {
67                 .start  = INT_GPIO1,
68                 .end    = INT_GPIO1,
69                 .flags  = IORESOURCE_IRQ,
70         },
71         [2] = {
72                 .start  = INT_GPIO2,
73                 .end    = INT_GPIO2,
74                 .flags  = IORESOURCE_IRQ,
75         },
76         [3] = {
77                 .start  = INT_GPIO3,
78                 .end    = INT_GPIO3,
79                 .flags  = IORESOURCE_IRQ,
80         },
81         [4] = {
82                 .start  = INT_GPIO4,
83                 .end    = INT_GPIO4,
84                 .flags  = IORESOURCE_IRQ,
85         },
86         [5] = {
87                 .start  = INT_GPIO5,
88                 .end    = INT_GPIO5,
89                 .flags  = IORESOURCE_IRQ,
90         },
91         [6] = {
92                 .start  = INT_GPIO6,
93                 .end    = INT_GPIO6,
94                 .flags  = IORESOURCE_IRQ,
95         },
96         [7] = {
97                 .start  = INT_GPIO7,
98                 .end    = INT_GPIO7,
99                 .flags  = IORESOURCE_IRQ,
100         },
101 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
102         [8] = {
103                 .start  = INT_GPIO8,
104                 .end    = INT_GPIO8,
105                 .flags  = IORESOURCE_IRQ,
106         },
107 #endif
108 };
109
110 struct platform_device tegra_gpio_device = {
111         .name           = "tegra-gpio",
112         .id             = -1,
113         .resource       = gpio_resource,
114         .num_resources  = ARRAY_SIZE(gpio_resource),
115 };
116
117 static struct resource pinmux_resource[] = {
118 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
119         [0] = {
120                 /* Tri-state registers */
121                 .start  = TEGRA_APB_MISC_BASE + 0x14,
122                 .end    = TEGRA_APB_MISC_BASE + 0x20 + 3,
123                 .flags  = IORESOURCE_MEM,
124         },
125         [1] = {
126                 /* Mux registers */
127                 .start  = TEGRA_APB_MISC_BASE + 0x80,
128                 .end    = TEGRA_APB_MISC_BASE + 0x9c + 3,
129                 .flags  = IORESOURCE_MEM,
130         },
131         [2] = {
132                 /* Pull-up/down registers */
133                 .start  = TEGRA_APB_MISC_BASE + 0xa0,
134                 .end    = TEGRA_APB_MISC_BASE + 0xb0 + 3,
135                 .flags  = IORESOURCE_MEM,
136         },
137         [3] = {
138                 /* Pad control registers */
139                 .start  = TEGRA_APB_MISC_BASE + 0x868,
140                 .end    = TEGRA_APB_MISC_BASE + 0x90c + 3,
141                 .flags  = IORESOURCE_MEM,
142         },
143 #else
144         [0] = {
145                 /* Drive registers */
146                 .start  = TEGRA_APB_MISC_BASE + 0x868,
147                 .end    = TEGRA_APB_MISC_BASE + 0x938 + 3,
148                 .flags  = IORESOURCE_MEM,
149         },
150         [1] = {
151                 /* Mux registers */
152                 .start  = TEGRA_APB_MISC_BASE + 0x3000,
153                 .end    = TEGRA_APB_MISC_BASE + 0x33e0 + 3,
154                 .flags  = IORESOURCE_MEM,
155         },
156 #endif
157 };
158
159 struct platform_device tegra_pinmux_device = {
160 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
161         .name           = "tegra30-pinmux-ctlr",
162 #elif defined(CONFIG_ARCH_TEGRA_2x_SOC)
163         .name           = "tegra20-pinmux-ctlr",
164 #elif defined(CONFIG_ARCH_TEGRA_11x_SOC)
165         .name           = "tegra11x-pinmux",
166 #endif
167         .id             = -1,
168         .resource       = pinmux_resource,
169         .num_resources  = ARRAY_SIZE(pinmux_resource),
170 };
171
172 static struct resource i2c_resource1[] = {
173         [0] = {
174                 .start  = INT_I2C,
175                 .end    = INT_I2C,
176                 .flags  = IORESOURCE_IRQ,
177         },
178         [1] = {
179                 .start  = TEGRA_I2C_BASE,
180                 .end    = TEGRA_I2C_BASE + TEGRA_I2C_SIZE-1,
181                 .flags  = IORESOURCE_MEM,
182         },
183 };
184
185 static struct resource i2c_resource2[] = {
186         [0] = {
187                 .start  = INT_I2C2,
188                 .end    = INT_I2C2,
189                 .flags  = IORESOURCE_IRQ,
190         },
191         [1] = {
192                 .start  = TEGRA_I2C2_BASE,
193                 .end    = TEGRA_I2C2_BASE + TEGRA_I2C2_SIZE-1,
194                 .flags  = IORESOURCE_MEM,
195         },
196 };
197
198 static struct resource i2c_resource3[] = {
199         [0] = {
200                 .start  = INT_I2C3,
201                 .end    = INT_I2C3,
202                 .flags  = IORESOURCE_IRQ,
203         },
204         [1] = {
205                 .start  = TEGRA_I2C3_BASE,
206                 .end    = TEGRA_I2C3_BASE + TEGRA_I2C3_SIZE-1,
207                 .flags  = IORESOURCE_MEM,
208         },
209 };
210
211 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
212 static struct resource i2c_resource4[] = {
213         [0] = {
214                 .start  = INT_DVC,
215                 .end    = INT_DVC,
216                 .flags  = IORESOURCE_IRQ,
217         },
218         [1] = {
219                 .start  = TEGRA_DVC_BASE,
220                 .end    = TEGRA_DVC_BASE + TEGRA_DVC_SIZE-1,
221                 .flags  = IORESOURCE_MEM,
222         },
223 };
224
225 #else
226 static struct resource i2c_resource4[] = {
227         [0] = {
228                 .start  = INT_I2C4,
229                 .end    = INT_I2C4,
230                 .flags  = IORESOURCE_IRQ,
231         },
232         [1] = {
233                 .start  = TEGRA_I2C4_BASE,
234                 .end    = TEGRA_I2C4_BASE + TEGRA_I2C4_SIZE-1,
235                 .flags  = IORESOURCE_MEM,
236         },
237 };
238
239 static struct resource i2c_resource5[] = {
240         [0] = {
241                 .start  = INT_I2C5,
242                 .end    = INT_I2C5,
243                 .flags  = IORESOURCE_IRQ,
244         },
245         [1] = {
246                 .start  = TEGRA_I2C5_BASE,
247                 .end    = TEGRA_I2C5_BASE + TEGRA_I2C5_SIZE-1,
248                 .flags  = IORESOURCE_MEM,
249         },
250 };
251 #endif
252
253 static struct tegra_i2c_platform_data tegra_i2c1_platform_data = {
254         .bus_clk_rate   = { 400000 },
255 };
256
257 static struct tegra_i2c_platform_data tegra_i2c2_platform_data = {
258         .bus_clk_rate   = { 400000 },
259 };
260
261 static struct tegra_i2c_platform_data tegra_i2c3_platform_data = {
262         .bus_clk_rate   = { 400000 },
263 };
264
265 static struct tegra_i2c_platform_data tegra_dvc_platform_data = {
266         .bus_clk_rate   = { 400000 },
267 };
268
269 struct platform_device tegra_i2c_device1 = {
270         .name           = "tegra-i2c",
271         .id             = 0,
272         .resource       = i2c_resource1,
273         .num_resources  = ARRAY_SIZE(i2c_resource1),
274         .dev = {
275                 .platform_data = &tegra_i2c1_platform_data,
276         },
277 };
278
279 struct platform_device tegra_i2c_device2 = {
280         .name           = "tegra-i2c",
281         .id             = 1,
282         .resource       = i2c_resource2,
283         .num_resources  = ARRAY_SIZE(i2c_resource2),
284         .dev = {
285                 .platform_data = &tegra_i2c2_platform_data,
286         },
287 };
288
289 struct platform_device tegra_i2c_device3 = {
290         .name           = "tegra-i2c",
291         .id             = 2,
292         .resource       = i2c_resource3,
293         .num_resources  = ARRAY_SIZE(i2c_resource3),
294         .dev = {
295                 .platform_data = &tegra_i2c3_platform_data,
296         },
297 };
298
299 struct platform_device tegra_i2c_device4 = {
300         .name           = "tegra-i2c",
301         .id             = 3,
302         .resource       = i2c_resource4,
303         .num_resources  = ARRAY_SIZE(i2c_resource4),
304         .dev = {
305                 .platform_data = &tegra_dvc_platform_data,
306         },
307 };
308
309 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
310 struct platform_device tegra_i2c_device5 = {
311         .name           = "tegra-i2c",
312         .id             = 4,
313         .resource       = i2c_resource5,
314         .num_resources  = ARRAY_SIZE(i2c_resource5),
315         .dev = {
316                 .platform_data = 0,
317         },
318 };
319 #endif
320
321 struct platform_device tegra11_i2c_device1 = {
322         .name           = "tegra11-i2c",
323         .id             = 0,
324         .resource       = i2c_resource1,
325         .num_resources  = ARRAY_SIZE(i2c_resource1),
326         .dev = {
327                 .platform_data = 0,
328         },
329 };
330
331 struct platform_device tegra11_i2c_device2 = {
332         .name           = "tegra11-i2c",
333         .id             = 1,
334         .resource       = i2c_resource2,
335         .num_resources  = ARRAY_SIZE(i2c_resource2),
336         .dev = {
337                 .platform_data = 0,
338         },
339 };
340
341 struct platform_device tegra11_i2c_device3 = {
342         .name           = "tegra11-i2c",
343         .id             = 2,
344         .resource       = i2c_resource3,
345         .num_resources  = ARRAY_SIZE(i2c_resource3),
346         .dev = {
347                 .platform_data = 0,
348         },
349 };
350
351 struct platform_device tegra11_i2c_device4 = {
352         .name           = "tegra11-i2c",
353         .id             = 3,
354         .resource       = i2c_resource4,
355         .num_resources  = ARRAY_SIZE(i2c_resource4),
356         .dev = {
357                 .platform_data = 0,
358         },
359 };
360
361 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
362 struct platform_device tegra11_i2c_device5 = {
363         .name           = "tegra11-i2c",
364         .id             = 4,
365         .resource       = i2c_resource5,
366         .num_resources  = ARRAY_SIZE(i2c_resource5),
367         .dev = {
368                 .platform_data = 0,
369         },
370 };
371 #endif
372
373 static struct resource spi_resource1[] = {
374         [0] = {
375                 .start  = INT_SPI_1,
376                 .end    = INT_SPI_1,
377                 .flags  = IORESOURCE_IRQ,
378         },
379         [1] = {
380                 .start  = TEGRA_SPI1_BASE,
381                 .end    = TEGRA_SPI1_BASE + TEGRA_SPI1_SIZE-1,
382                 .flags  = IORESOURCE_MEM,
383         },
384 };
385
386 static struct resource spi_resource2[] = {
387         [0] = {
388                 .start  = INT_SPI_2,
389                 .end    = INT_SPI_2,
390                 .flags  = IORESOURCE_IRQ,
391         },
392         [1] = {
393                 .start  = TEGRA_SPI2_BASE,
394                 .end    = TEGRA_SPI2_BASE + TEGRA_SPI2_SIZE-1,
395                 .flags  = IORESOURCE_MEM,
396         },
397 };
398
399 static struct resource spi_resource3[] = {
400         [0] = {
401                 .start  = INT_SPI_3,
402                 .end    = INT_SPI_3,
403                 .flags  = IORESOURCE_IRQ,
404         },
405         [1] = {
406                 .start  = TEGRA_SPI3_BASE,
407                 .end    = TEGRA_SPI3_BASE + TEGRA_SPI3_SIZE-1,
408                 .flags  = IORESOURCE_MEM,
409         },
410 };
411
412 static struct resource spi_resource4[] = {
413         [0] = {
414                 .start  = INT_SPI_4,
415                 .end    = INT_SPI_4,
416                 .flags  = IORESOURCE_IRQ,
417         },
418         [1] = {
419                 .start  = TEGRA_SPI4_BASE,
420                 .end    = TEGRA_SPI4_BASE + TEGRA_SPI4_SIZE-1,
421                 .flags  = IORESOURCE_MEM,
422         },
423 };
424 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
425 static struct resource spi_resource5[] = {
426         [0] = {
427                 .start  = INT_SPI_5,
428                 .end    = INT_SPI_5,
429                 .flags  = IORESOURCE_IRQ,
430         },
431         [1] = {
432                 .start  = TEGRA_SPI5_BASE,
433                 .end    = TEGRA_SPI5_BASE + TEGRA_SPI5_SIZE-1,
434                 .flags  = IORESOURCE_MEM,
435         },
436 };
437
438 static struct resource spi_resource6[] = {
439         [0] = {
440                 .start  = INT_SPI_6,
441                 .end    = INT_SPI_6,
442                 .flags  = IORESOURCE_IRQ,
443         },
444         [1] = {
445                 .start  = TEGRA_SPI6_BASE,
446                 .end    = TEGRA_SPI6_BASE + TEGRA_SPI6_SIZE-1,
447                 .flags  = IORESOURCE_MEM,
448         },
449 };
450 #endif
451
452 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
453 static struct resource dtv_resource[] = {
454         [0] = {
455                 .start  = INT_DTV,
456                 .end    = INT_DTV,
457                 .flags  = IORESOURCE_IRQ,
458         },
459         [1] = {
460                 .start  = TEGRA_DTV_BASE,
461                 .end    = TEGRA_DTV_BASE + TEGRA_DTV_SIZE - 1,
462                 .flags  = IORESOURCE_MEM,
463         },
464         [2] = {
465                 .start  = TEGRA_DMA_REQ_SEL_DTV,
466                 .end    = TEGRA_DMA_REQ_SEL_DTV,
467                 .flags  = IORESOURCE_DMA
468         },
469 };
470 #endif
471
472
473 struct platform_device tegra_spi_device1 = {
474         .name           = "spi_tegra",
475         .id             = 0,
476         .resource       = spi_resource1,
477         .num_resources  = ARRAY_SIZE(spi_resource1),
478         .dev            = {
479                 .coherent_dma_mask      = 0xffffffff,
480         },
481 };
482
483 struct platform_device tegra_spi_device2 = {
484         .name           = "spi_tegra",
485         .id             = 1,
486         .resource       = spi_resource2,
487         .num_resources  = ARRAY_SIZE(spi_resource2),
488         .dev            = {
489                 .coherent_dma_mask      = 0xffffffff,
490         },
491 };
492
493 struct platform_device tegra_spi_device3 = {
494         .name           = "spi_tegra",
495         .id             = 2,
496         .resource       = spi_resource3,
497         .num_resources  = ARRAY_SIZE(spi_resource3),
498         .dev            = {
499                 .coherent_dma_mask      = 0xffffffff,
500         },
501 };
502
503 struct platform_device tegra_spi_device4 = {
504         .name           = "spi_tegra",
505         .id             = 3,
506         .resource       = spi_resource4,
507         .num_resources  = ARRAY_SIZE(spi_resource4),
508         .dev            = {
509                 .coherent_dma_mask      = 0xffffffff,
510         },
511 };
512 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
513 struct platform_device tegra_spi_device5 = {
514         .name           = "spi_tegra",
515         .id             = 4,
516         .resource       = spi_resource5,
517         .num_resources  = ARRAY_SIZE(spi_resource5),
518         .dev  = {
519                 .coherent_dma_mask      = 0xffffffff,
520         },
521 };
522
523 struct platform_device tegra_spi_device6 = {
524         .name           = "spi_tegra",
525         .id             = 5,
526         .resource       = spi_resource6,
527         .num_resources  = ARRAY_SIZE(spi_resource6),
528         .dev  = {
529                 .coherent_dma_mask      = 0xffffffff,
530         },
531 };
532 #endif
533
534 struct platform_device tegra11_spi_device1 = {
535         .name           = "tegra11-spi",
536         .id             = 0,
537         .resource       = spi_resource1,
538         .num_resources  = ARRAY_SIZE(spi_resource1),
539         .dev            = {
540                 .coherent_dma_mask      = 0xffffffff,
541         },
542 };
543
544 struct platform_device tegra11_spi_device2 = {
545         .name           = "tegra11-spi",
546         .id             = 1,
547         .resource       = spi_resource2,
548         .num_resources  = ARRAY_SIZE(spi_resource2),
549         .dev            = {
550                 .coherent_dma_mask      = 0xffffffff,
551         },
552 };
553
554 struct platform_device tegra11_spi_device3 = {
555         .name           = "tegra11-spi",
556         .id             = 2,
557         .resource       = spi_resource3,
558         .num_resources  = ARRAY_SIZE(spi_resource3),
559         .dev            = {
560                 .coherent_dma_mask      = 0xffffffff,
561         },
562 };
563
564 struct platform_device tegra11_spi_device4 = {
565         .name           = "tegra11-spi",
566         .id             = 3,
567         .resource       = spi_resource4,
568         .num_resources  = ARRAY_SIZE(spi_resource4),
569         .dev            = {
570                 .coherent_dma_mask      = 0xffffffff,
571         },
572 };
573
574 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
575 struct platform_device tegra11_spi_device5 = {
576         .name           = "tegra11-spi",
577         .id             = 4,
578         .resource       = spi_resource5,
579         .num_resources  = ARRAY_SIZE(spi_resource5),
580         .dev  = {
581                 .coherent_dma_mask      = 0xffffffff,
582         },
583 };
584
585 struct platform_device tegra11_spi_device6 = {
586         .name           = "tegra11-spi",
587         .id             = 5,
588         .resource       = spi_resource6,
589         .num_resources  = ARRAY_SIZE(spi_resource6),
590         .dev  = {
591                 .coherent_dma_mask      = 0xffffffff,
592         },
593 };
594 #endif
595
596 struct platform_device tegra_spi_slave_device1 = {
597         .name           = "spi_slave_tegra",
598         .id             = 0,
599         .resource       = spi_resource1,
600         .num_resources  = ARRAY_SIZE(spi_resource1),
601         .dev  = {
602                 .coherent_dma_mask      = 0xffffffff,
603         },
604 };
605
606 struct platform_device tegra_spi_slave_device2 = {
607         .name           = "spi_slave_tegra",
608         .id             = 1,
609         .resource       = spi_resource2,
610         .num_resources  = ARRAY_SIZE(spi_resource2),
611         .dev  = {
612                 .coherent_dma_mask      = 0xffffffff,
613         },
614 };
615
616 struct platform_device tegra_spi_slave_device3 = {
617         .name           = "spi_slave_tegra",
618         .id             = 2,
619         .resource       = spi_resource3,
620         .num_resources  = ARRAY_SIZE(spi_resource3),
621         .dev  = {
622                 .coherent_dma_mask      = 0xffffffff,
623         },
624 };
625
626 struct platform_device tegra_spi_slave_device4 = {
627         .name           = "spi_slave_tegra",
628         .id             = 3,
629         .resource       = spi_resource4,
630         .num_resources  = ARRAY_SIZE(spi_resource4),
631         .dev  = {
632                 .coherent_dma_mask      = 0xffffffff,
633         },
634 };
635 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
636 struct platform_device tegra_spi_slave_device5 = {
637         .name           = "spi_slave_tegra",
638         .id             = 4,
639         .resource       = spi_resource5,
640         .num_resources  = ARRAY_SIZE(spi_resource5),
641         .dev  = {
642                 .coherent_dma_mask      = 0xffffffff,
643         },
644 };
645
646 struct platform_device tegra_spi_slave_device6 = {
647         .name           = "spi_slave_tegra",
648         .id             = 5,
649         .resource       = spi_resource6,
650         .num_resources  = ARRAY_SIZE(spi_resource6),
651         .dev  = {
652                 .coherent_dma_mask      = 0xffffffff,
653         },
654 };
655 #endif
656
657 struct platform_device tegra11_spi_slave_device1 = {
658         .name           = "tegra11-spi-slave",
659         .id             = 0,
660         .resource       = spi_resource1,
661         .num_resources  = ARRAY_SIZE(spi_resource1),
662         .dev  = {
663                 .coherent_dma_mask      = 0xffffffff,
664         },
665 };
666
667 struct platform_device tegra11_spi_slave_device2 = {
668         .name           = "tegra11-spi-slave",
669         .id             = 1,
670         .resource       = spi_resource2,
671         .num_resources  = ARRAY_SIZE(spi_resource2),
672         .dev  = {
673                 .coherent_dma_mask      = 0xffffffff,
674         },
675 };
676
677 struct platform_device tegra11_spi_slave_device3 = {
678         .name           = "tegra11-spi-slave",
679         .id             = 2,
680         .resource       = spi_resource3,
681         .num_resources  = ARRAY_SIZE(spi_resource3),
682         .dev  = {
683                 .coherent_dma_mask      = 0xffffffff,
684         },
685 };
686
687 struct platform_device tegra11_spi_slave_device4 = {
688         .name           = "tegra11-spi-slave",
689         .id             = 3,
690         .resource       = spi_resource4,
691         .num_resources  = ARRAY_SIZE(spi_resource4),
692         .dev  = {
693                 .coherent_dma_mask      = 0xffffffff,
694         },
695 };
696 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
697 struct platform_device tegra11_spi_slave_device5 = {
698         .name           = "tegra11-spi-slave",
699         .id             = 4,
700         .resource       = spi_resource5,
701         .num_resources  = ARRAY_SIZE(spi_resource5),
702         .dev  = {
703                 .coherent_dma_mask      = 0xffffffff,
704         },
705 };
706
707 struct platform_device tegra11_spi_slave_device6 = {
708         .name           = "tegra11-spi-slave",
709         .id             = 5,
710         .resource       = spi_resource6,
711         .num_resources  = ARRAY_SIZE(spi_resource6),
712         .dev  = {
713                 .coherent_dma_mask      = 0xffffffff,
714         },
715 };
716 #endif
717
718 static struct resource resources_nor[] = {
719         [0] = {
720                 .start = INT_SNOR,
721                 .end = INT_SNOR,
722                 .flags = IORESOURCE_IRQ,
723         },
724         [1] = {
725                 /* Map SNOR Controller */
726                 .start = TEGRA_SNOR_BASE,
727                 .end = TEGRA_SNOR_BASE + TEGRA_SNOR_SIZE - 1,
728                 .flags = IORESOURCE_MEM,
729         },
730         [2] = {
731                 /* Map the size of flash */
732                 .start = TEGRA_NOR_FLASH_BASE,
733                 .end = TEGRA_NOR_FLASH_BASE + TEGRA_NOR_FLASH_SIZE - 1,
734                 .flags = IORESOURCE_MEM,
735         }
736 };
737
738 struct platform_device tegra_nor_device = {
739         .name = "tegra-nor",
740         .id = -1,
741         .num_resources = ARRAY_SIZE(resources_nor),
742         .resource = resources_nor,
743         .dev = {
744                 .coherent_dma_mask = 0xffffffff,
745         },
746 };
747
748 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
749 struct platform_device tegra_dtv_device = {
750         .name           = "tegra_dtv",
751         .id             = -1,
752         .resource       = dtv_resource,
753         .num_resources  = ARRAY_SIZE(dtv_resource),
754         .dev = {
755                 .init_name = "dtv",
756                 .coherent_dma_mask = 0xffffffff,
757         },
758 };
759 #endif
760
761 static struct resource sdhci_resource1[] = {
762         [0] = {
763                 .start  = INT_SDMMC1,
764                 .end    = INT_SDMMC1,
765                 .flags  = IORESOURCE_IRQ,
766         },
767         [1] = {
768                 .start  = TEGRA_SDMMC1_BASE,
769                 .end    = TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE-1,
770                 .flags  = IORESOURCE_MEM,
771         },
772 };
773
774 static struct resource sdhci_resource2[] = {
775         [0] = {
776                 .start  = INT_SDMMC2,
777                 .end    = INT_SDMMC2,
778                 .flags  = IORESOURCE_IRQ,
779         },
780         [1] = {
781                 .start  = TEGRA_SDMMC2_BASE,
782                 .end    = TEGRA_SDMMC2_BASE + TEGRA_SDMMC2_SIZE-1,
783                 .flags  = IORESOURCE_MEM,
784         },
785 };
786
787 static struct resource sdhci_resource3[] = {
788         [0] = {
789                 .start  = INT_SDMMC3,
790                 .end    = INT_SDMMC3,
791                 .flags  = IORESOURCE_IRQ,
792         },
793         [1] = {
794                 .start  = TEGRA_SDMMC3_BASE,
795                 .end    = TEGRA_SDMMC3_BASE + TEGRA_SDMMC3_SIZE-1,
796                 .flags  = IORESOURCE_MEM,
797         },
798 };
799
800 static struct resource sdhci_resource4[] = {
801         [0] = {
802                 .start  = INT_SDMMC4,
803                 .end    = INT_SDMMC4,
804                 .flags  = IORESOURCE_IRQ,
805         },
806         [1] = {
807                 .start  = TEGRA_SDMMC4_BASE,
808                 .end    = TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE-1,
809                 .flags  = IORESOURCE_MEM,
810         },
811 };
812
813 struct platform_device tegra_pci_device = {
814         .name           = "tegra-pcie",
815         .id             = 0,
816         .resource       = 0,
817         .num_resources  = 0,
818         .dev = {
819                 .platform_data = 0,
820         },
821 };
822
823 /* board files should fill in platform_data register the devices themselvs.
824  * See board-harmony.c for an example
825  */
826 struct platform_device tegra_sdhci_device1 = {
827         .name           = "sdhci-tegra",
828         .id             = 0,
829         .resource       = sdhci_resource1,
830         .num_resources  = ARRAY_SIZE(sdhci_resource1),
831 };
832
833 struct platform_device tegra_sdhci_device2 = {
834         .name           = "sdhci-tegra",
835         .id             = 1,
836         .resource       = sdhci_resource2,
837         .num_resources  = ARRAY_SIZE(sdhci_resource2),
838 };
839
840 struct platform_device tegra_sdhci_device3 = {
841         .name           = "sdhci-tegra",
842         .id             = 2,
843         .resource       = sdhci_resource3,
844         .num_resources  = ARRAY_SIZE(sdhci_resource3),
845 };
846
847 struct platform_device tegra_sdhci_device4 = {
848         .name           = "sdhci-tegra",
849         .id             = 3,
850         .resource       = sdhci_resource4,
851         .num_resources  = ARRAY_SIZE(sdhci_resource4),
852 };
853
854 static struct resource tegra_usb1_resources[] = {
855         [0] = {
856                 .start  = TEGRA_USB_BASE,
857                 .end    = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
858                 .flags  = IORESOURCE_MEM,
859         },
860         [1] = {
861                 .start  = INT_USB,
862                 .end    = INT_USB,
863                 .flags  = IORESOURCE_IRQ,
864         },
865 };
866
867 static struct resource tegra_usb2_resources[] = {
868         [0] = {
869                 .start  = TEGRA_USB2_BASE,
870                 .end    = TEGRA_USB2_BASE + TEGRA_USB2_SIZE - 1,
871                 .flags  = IORESOURCE_MEM,
872         },
873         [1] = {
874                 .start  = INT_USB2,
875                 .end    = INT_USB2,
876                 .flags  = IORESOURCE_IRQ,
877         },
878 };
879
880 static struct resource tegra_usb3_resources[] = {
881         [0] = {
882                 .start  = TEGRA_USB3_BASE,
883                 .end    = TEGRA_USB3_BASE + TEGRA_USB3_SIZE - 1,
884                 .flags  = IORESOURCE_MEM,
885         },
886         [1] = {
887                 .start  = INT_USB3,
888                 .end    = INT_USB3,
889                 .flags  = IORESOURCE_IRQ,
890         },
891 };
892
893 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
894 static struct resource tegra_xusb_resources[] = {
895         [0] = {
896                 .start  = TEGRA_XUSB_HOST_BASE,
897                 .end    = TEGRA_XUSB_HOST_BASE + TEGRA_XUSB_HOST_SIZE - 1,
898                 .flags  = IORESOURCE_MEM,
899         },
900         [1] = {
901                 .start  = INT_USB3_HOST_INT,
902                 .end    = INT_USB3_HOST_INT,
903                 .flags  = IORESOURCE_IRQ,
904         },
905         [2] = {
906                 .start  = INT_USB3_NOT_SMI,
907                 .end    = INT_USB3_NOT_SMI,
908                 .flags  = IORESOURCE_IRQ,
909         },
910         [3] = {
911                 .start  = INT_XUSB_PADCTL,
912                 .end    = INT_XUSB_PADCTL,
913                 .flags  = IORESOURCE_IRQ,
914         },
915 };
916
917 static u64 tegra_xusb_dmamask = DMA_BIT_MASK(64);
918
919 struct platform_device tegra_xhci_device = {
920         .name = "tegra-xhci",
921         .id = -1,
922         .dev = {
923                 .dma_mask = &tegra_xusb_dmamask,
924                 .coherent_dma_mask = DMA_BIT_MASK(64),
925         },
926         .resource = tegra_xusb_resources,
927         .num_resources = ARRAY_SIZE(tegra_xusb_resources),
928 };
929 #endif
930
931 static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32);
932
933 struct platform_device tegra_ehci1_device = {
934         .name   = "tegra-ehci",
935         .id     = 0,
936         .dev    = {
937                 .dma_mask       = &tegra_ehci_dmamask,
938                 .coherent_dma_mask = DMA_BIT_MASK(32),
939         },
940         .resource = tegra_usb1_resources,
941         .num_resources = ARRAY_SIZE(tegra_usb1_resources),
942 };
943
944 struct platform_device tegra_ehci2_device = {
945         .name   = "tegra-ehci",
946         .id     = 1,
947         .dev    = {
948                 .dma_mask       = &tegra_ehci_dmamask,
949                 .coherent_dma_mask = DMA_BIT_MASK(32),
950         },
951         .resource = tegra_usb2_resources,
952         .num_resources = ARRAY_SIZE(tegra_usb2_resources),
953 };
954
955 struct platform_device tegra_ehci3_device = {
956         .name   = "tegra-ehci",
957         .id     = 2,
958         .dev    = {
959                 .dma_mask       = &tegra_ehci_dmamask,
960                 .coherent_dma_mask = DMA_BIT_MASK(32),
961         },
962         .resource = tegra_usb3_resources,
963         .num_resources = ARRAY_SIZE(tegra_usb3_resources),
964 };
965
966 static struct resource tegra_pmu_resources[] = {
967         [0] = {
968                 .start  = INT_CPU0_PMU_INTR,
969                 .end    = INT_CPU0_PMU_INTR,
970                 .flags  = IORESOURCE_IRQ,
971         },
972         [1] = {
973                 .start  = INT_CPU1_PMU_INTR,
974                 .end    = INT_CPU1_PMU_INTR,
975                 .flags  = IORESOURCE_IRQ,
976         },
977 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
978         [2] = {
979                 .start  = INT_CPU2_PMU_INTR,
980                 .end    = INT_CPU2_PMU_INTR,
981                 .flags  = IORESOURCE_IRQ,
982         },
983         [3] = {
984                 .start  = INT_CPU3_PMU_INTR,
985                 .end    = INT_CPU3_PMU_INTR,
986                 .flags  = IORESOURCE_IRQ,
987         },
988 #endif
989 };
990
991 struct platform_device tegra_pmu_device = {
992         .name           = "arm-pmu",
993         .id             = ARM_PMU_DEVICE_CPU,
994         .num_resources  = ARRAY_SIZE(tegra_pmu_resources),
995         .resource       = tegra_pmu_resources,
996 };
997
998 static struct resource tegra_uarta_resources[] = {
999         [0] = {
1000                 .start  = TEGRA_UARTA_BASE,
1001                 .end    = TEGRA_UARTA_BASE + TEGRA_UARTA_SIZE - 1,
1002                 .flags  = IORESOURCE_MEM,
1003         },
1004         [1] = {
1005                 .start  = INT_UARTA,
1006                 .end    = INT_UARTA,
1007                 .flags  = IORESOURCE_IRQ,
1008         },
1009 };
1010
1011 static struct resource tegra_uartb_resources[] = {
1012         [0] = {
1013                 .start  = TEGRA_UARTB_BASE,
1014                 .end    = TEGRA_UARTB_BASE + TEGRA_UARTB_SIZE - 1,
1015                 .flags  = IORESOURCE_MEM,
1016         },
1017         [1] = {
1018                 .start  = INT_UARTB,
1019                 .end    = INT_UARTB,
1020                 .flags  = IORESOURCE_IRQ,
1021         },
1022 };
1023
1024 static struct resource tegra_uartc_resources[] = {
1025         [0] = {
1026                 .start  = TEGRA_UARTC_BASE,
1027                 .end    = TEGRA_UARTC_BASE + TEGRA_UARTC_SIZE - 1,
1028                 .flags  = IORESOURCE_MEM,
1029         },
1030         [1] = {
1031                 .start  = INT_UARTC,
1032                 .end    = INT_UARTC,
1033                 .flags  = IORESOURCE_IRQ,
1034         },
1035 };
1036
1037 static struct resource tegra_uartd_resources[] = {
1038         [0] = {
1039                 .start  = TEGRA_UARTD_BASE,
1040                 .end    = TEGRA_UARTD_BASE + TEGRA_UARTD_SIZE - 1,
1041                 .flags  = IORESOURCE_MEM,
1042         },
1043         [1] = {
1044                 .start  = INT_UARTD,
1045                 .end    = INT_UARTD,
1046                 .flags  = IORESOURCE_IRQ,
1047         },
1048 };
1049
1050 static struct resource tegra_uarte_resources[] = {
1051         [0] = {
1052                 .start  = TEGRA_UARTE_BASE,
1053                 .end    = TEGRA_UARTE_BASE + TEGRA_UARTE_SIZE - 1,
1054                 .flags  = IORESOURCE_MEM,
1055         },
1056         [1] = {
1057                 .start  = INT_UARTE,
1058                 .end    = INT_UARTE,
1059                 .flags  = IORESOURCE_IRQ,
1060         },
1061 };
1062
1063 struct platform_device tegra_uarta_device = {
1064         .name   = "tegra_uart",
1065         .id     = 0,
1066         .num_resources  = ARRAY_SIZE(tegra_uarta_resources),
1067         .resource       = tegra_uarta_resources,
1068         .dev    = {
1069                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1070         },
1071 };
1072
1073 struct platform_device tegra_uartb_device = {
1074         .name   = "tegra_uart",
1075         .id     = 1,
1076         .num_resources  = ARRAY_SIZE(tegra_uartb_resources),
1077         .resource       = tegra_uartb_resources,
1078         .dev    = {
1079                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1080         },
1081 };
1082
1083 struct platform_device tegra_uartc_device = {
1084         .name   = "tegra_uart",
1085         .id     = 2,
1086         .num_resources  = ARRAY_SIZE(tegra_uartc_resources),
1087         .resource       = tegra_uartc_resources,
1088         .dev    = {
1089                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1090         },
1091 };
1092
1093 struct platform_device tegra_uartd_device = {
1094         .name   = "tegra_uart",
1095         .id     = 3,
1096         .num_resources  = ARRAY_SIZE(tegra_uartd_resources),
1097         .resource       = tegra_uartd_resources,
1098         .dev    = {
1099                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1100         },
1101 };
1102
1103 struct platform_device tegra_uarte_device = {
1104         .name   = "tegra_uart",
1105         .id     = 4,
1106         .num_resources  = ARRAY_SIZE(tegra_uarte_resources),
1107         .resource       = tegra_uarte_resources,
1108         .dev    = {
1109                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1110         },
1111 };
1112
1113 static struct plat_serial8250_port debug_uarta_platform_data[] = {
1114         {
1115                 .membase        = IO_ADDRESS(TEGRA_UARTA_BASE),
1116                 .mapbase        = TEGRA_UARTA_BASE,
1117                 .irq            = INT_UARTA,
1118                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
1119                 .type           = PORT_TEGRA,
1120                 .iotype         = UPIO_MEM,
1121                 .regshift       = 2,
1122         },
1123         {
1124                 .flags          = 0,
1125         },
1126 };
1127
1128 static struct plat_serial8250_port debug_uartb_platform_data[] = {
1129         {
1130                 .membase        = IO_ADDRESS(TEGRA_UARTB_BASE),
1131                 .mapbase        = TEGRA_UARTB_BASE,
1132                 .irq            = INT_UARTB,
1133                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
1134                 .type           = PORT_TEGRA,
1135                 .iotype         = UPIO_MEM,
1136                 .regshift       = 2,
1137         },
1138         {
1139                 .flags          = 0,
1140         },
1141 };
1142
1143 static struct plat_serial8250_port debug_uartc_platform_data[] = {
1144         {
1145                 .membase        = IO_ADDRESS(TEGRA_UARTC_BASE),
1146                 .mapbase        = TEGRA_UARTC_BASE,
1147                 .irq            = INT_UARTC,
1148                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
1149                 .type           = PORT_TEGRA,
1150                 .iotype         = UPIO_MEM,
1151                 .regshift       = 2,
1152         },
1153         {
1154                 .flags          = 0,
1155         },
1156 };
1157
1158 static struct plat_serial8250_port debug_uartd_platform_data[] = {
1159         {
1160                 .membase        = IO_ADDRESS(TEGRA_UARTD_BASE),
1161                 .mapbase        = TEGRA_UARTD_BASE,
1162                 .irq            = INT_UARTD,
1163                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
1164                 .type           = PORT_TEGRA,
1165                 .iotype         = UPIO_MEM,
1166                 .regshift       = 2,
1167         },
1168         {
1169                 .flags          = 0,
1170         },
1171 };
1172
1173 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1174 static struct plat_serial8250_port debug_uarte_platform_data[] = {
1175         {
1176                 .membase        = IO_ADDRESS(TEGRA_UARTE_BASE),
1177                 .mapbase        = TEGRA_UARTE_BASE,
1178                 .irq            = INT_UARTE,
1179                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
1180                 .type           = PORT_TEGRA,
1181                 .iotype         = UPIO_MEM,
1182                 .regshift       = 2,
1183         },
1184         {
1185                 .flags          = 0,
1186         },
1187 };
1188 #endif
1189
1190 struct platform_device debug_uarta_device = {
1191         .name = "serial8250",
1192         .id = PLAT8250_DEV_PLATFORM,
1193         .dev = {
1194                 .platform_data = debug_uarta_platform_data,
1195         },
1196 };
1197
1198 struct platform_device debug_uartb_device = {
1199         .name = "serial8250",
1200         .id = PLAT8250_DEV_PLATFORM,
1201         .dev = {
1202                 .platform_data = debug_uartb_platform_data,
1203         },
1204 };
1205
1206 struct platform_device debug_uartc_device = {
1207         .name = "serial8250",
1208         .id = PLAT8250_DEV_PLATFORM,
1209         .dev = {
1210                 .platform_data = debug_uartc_platform_data,
1211         },
1212 };
1213
1214 struct platform_device debug_uartd_device = {
1215         .name = "serial8250",
1216         .id = PLAT8250_DEV_PLATFORM,
1217         .dev = {
1218                 .platform_data = debug_uartd_platform_data,
1219         },
1220 };
1221
1222 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1223 struct platform_device debug_uarte_device = {
1224         .name = "serial8250",
1225         .id = PLAT8250_DEV_PLATFORM,
1226         .dev = {
1227                 .platform_data = debug_uarte_platform_data,
1228         },
1229 };
1230 #endif
1231
1232 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1233 static struct resource i2s_resource1[] = {
1234         [0] = {
1235                 .start  = INT_I2S1,
1236                 .end    = INT_I2S1,
1237                 .flags  = IORESOURCE_IRQ
1238         },
1239         [1] = {
1240                 .start  = TEGRA_DMA_REQ_SEL_I2S_1,
1241                 .end    = TEGRA_DMA_REQ_SEL_I2S_1,
1242                 .flags  = IORESOURCE_DMA
1243         },
1244         [2] = {
1245                 .start  = TEGRA_I2S1_BASE,
1246                 .end    = TEGRA_I2S1_BASE + TEGRA_I2S1_SIZE - 1,
1247                 .flags  = IORESOURCE_MEM
1248         }
1249 };
1250
1251 struct platform_device tegra_i2s_device1 = {
1252         .name           = "tegra20-i2s",
1253         .id             = 0,
1254         .resource       = i2s_resource1,
1255         .num_resources  = ARRAY_SIZE(i2s_resource1),
1256 };
1257
1258 static struct resource i2s_resource2[] = {
1259         [0] = {
1260                 .start  = INT_I2S2,
1261                 .end    = INT_I2S2,
1262                 .flags  = IORESOURCE_IRQ
1263         },
1264         [1] = {
1265                 .start  = TEGRA_DMA_REQ_SEL_I2S2_1,
1266                 .end    = TEGRA_DMA_REQ_SEL_I2S2_1,
1267                 .flags  = IORESOURCE_DMA
1268         },
1269         [2] = {
1270                 .start  = TEGRA_I2S2_BASE,
1271                 .end    = TEGRA_I2S2_BASE + TEGRA_I2S2_SIZE - 1,
1272                 .flags  = IORESOURCE_MEM
1273         }
1274 };
1275
1276 struct platform_device tegra_i2s_device2 = {
1277         .name           = "tegra20-i2s",
1278         .id             = 1,
1279         .resource       = i2s_resource2,
1280         .num_resources  = ARRAY_SIZE(i2s_resource2),
1281 };
1282 #else
1283 static struct resource i2s_resource0[] = {
1284         [0] = {
1285                 .start  = TEGRA_I2S0_BASE,
1286                 .end    = TEGRA_I2S0_BASE + TEGRA_I2S0_SIZE - 1,
1287                 .flags  = IORESOURCE_MEM
1288         }
1289 };
1290
1291 struct platform_device tegra_i2s_device0 = {
1292         .name           = "tegra30-i2s",
1293         .id             = 0,
1294         .resource       = i2s_resource0,
1295         .num_resources  = ARRAY_SIZE(i2s_resource0),
1296 };
1297
1298 static struct resource i2s_resource1[] = {
1299         [0] = {
1300                 .start  = TEGRA_I2S1_BASE,
1301                 .end    = TEGRA_I2S1_BASE + TEGRA_I2S1_SIZE - 1,
1302                 .flags  = IORESOURCE_MEM
1303         }
1304 };
1305
1306 struct platform_device tegra_i2s_device1 = {
1307         .name           = "tegra30-i2s",
1308         .id             = 1,
1309         .resource       = i2s_resource1,
1310         .num_resources  = ARRAY_SIZE(i2s_resource1),
1311 };
1312
1313 static struct resource i2s_resource2[] = {
1314         [0] = {
1315                 .start  = TEGRA_I2S2_BASE,
1316                 .end    = TEGRA_I2S2_BASE + TEGRA_I2S2_SIZE - 1,
1317                 .flags  = IORESOURCE_MEM
1318         }
1319 };
1320
1321 struct platform_device tegra_i2s_device2 = {
1322         .name           = "tegra30-i2s",
1323         .id             = 2,
1324         .resource       = i2s_resource2,
1325         .num_resources  = ARRAY_SIZE(i2s_resource2),
1326 };
1327
1328 static struct resource i2s_resource3[] = {
1329         [0] = {
1330                 .start  = TEGRA_I2S3_BASE,
1331                 .end    = TEGRA_I2S3_BASE + TEGRA_I2S3_SIZE - 1,
1332                 .flags  = IORESOURCE_MEM
1333         }
1334 };
1335
1336 struct platform_device tegra_i2s_device3 = {
1337         .name           = "tegra30-i2s",
1338         .id             = 3,
1339         .resource       = i2s_resource3,
1340         .num_resources  = ARRAY_SIZE(i2s_resource3),
1341 };
1342
1343 static struct resource i2s_resource4[] = {
1344         [0] = {
1345                 .start  = TEGRA_I2S4_BASE,
1346                 .end    = TEGRA_I2S4_BASE + TEGRA_I2S4_SIZE - 1,
1347                 .flags  = IORESOURCE_MEM
1348         }
1349 };
1350
1351 struct platform_device tegra_i2s_device4 = {
1352         .name           = "tegra30-i2s",
1353         .id             = 4,
1354         .resource       = i2s_resource4,
1355         .num_resources  = ARRAY_SIZE(i2s_resource4),
1356 };
1357 #endif
1358
1359 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1360 static struct resource spdif_resource[] = {
1361         [0] = {
1362                 .start  = INT_SPDIF,
1363                 .end    = INT_SPDIF,
1364                 .flags  = IORESOURCE_IRQ
1365         },
1366         [1] = {
1367                 .start  = TEGRA_DMA_REQ_SEL_SPD_I,
1368                 .end    = TEGRA_DMA_REQ_SEL_SPD_I,
1369                 .flags  = IORESOURCE_DMA
1370         },
1371         [2] = {
1372                 .start  = TEGRA_SPDIF_BASE,
1373                 .end    = TEGRA_SPDIF_BASE + TEGRA_SPDIF_SIZE - 1,
1374                 .flags  = IORESOURCE_MEM
1375         }
1376 };
1377
1378 struct platform_device tegra_spdif_device = {
1379         .name           = "tegra20-spdif",
1380         .id             = -1,
1381         .resource       = spdif_resource,
1382         .num_resources  = ARRAY_SIZE(spdif_resource),
1383 };
1384 #else
1385 static struct resource spdif_resource[] = {
1386         [0] = {
1387                 .start  = TEGRA_SPDIF_BASE,
1388                 .end    = TEGRA_SPDIF_BASE + TEGRA_SPDIF_SIZE - 1,
1389                 .flags  = IORESOURCE_MEM
1390         }
1391 };
1392
1393 struct platform_device tegra_spdif_device = {
1394         .name           = "tegra30-spdif",
1395         .id             = -1,
1396         .resource       = spdif_resource,
1397         .num_resources  = ARRAY_SIZE(spdif_resource),
1398 };
1399 #endif
1400
1401 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1402 static struct resource ahub_resource[] = {
1403         [0] = {
1404                 .start  = TEGRA_APBIF0_BASE,
1405                 .end    = TEGRA_APBIF3_BASE + TEGRA_APBIF3_SIZE - 1,
1406                 .flags  = IORESOURCE_MEM
1407         },
1408         [1] = {
1409                 .start  = TEGRA_AHUB_BASE,
1410                 .end    = TEGRA_AHUB_BASE + TEGRA_AHUB_SIZE - 1,
1411                 .flags  = IORESOURCE_MEM
1412         }
1413 };
1414
1415 struct platform_device tegra_ahub_device = {
1416         .name   = "tegra30-ahub",
1417         .id     = -1,
1418         .resource       = ahub_resource,
1419         .num_resources  = ARRAY_SIZE(ahub_resource),
1420 };
1421
1422 static struct resource dam_resource0[] = {
1423         [0] = {
1424                 .start = TEGRA_DAM0_BASE,
1425                 .end   = TEGRA_DAM0_BASE + TEGRA_DAM0_SIZE - 1,
1426                 .flags = IORESOURCE_MEM
1427         }
1428 };
1429
1430 struct platform_device tegra_dam_device0 = {
1431         .name = "tegra30-dam",
1432         .id = 0,
1433         .resource      = dam_resource0,
1434         .num_resources = ARRAY_SIZE(dam_resource0),
1435 };
1436
1437 static struct resource dam_resource1[] = {
1438         [0] = {
1439                 .start = TEGRA_DAM1_BASE,
1440                 .end   = TEGRA_DAM1_BASE + TEGRA_DAM1_SIZE - 1,
1441                 .flags = IORESOURCE_MEM
1442         }
1443 };
1444
1445 struct platform_device tegra_dam_device1 = {
1446         .name = "tegra30-dam",
1447         .id = 1,
1448         .resource      = dam_resource1,
1449         .num_resources = ARRAY_SIZE(dam_resource1),
1450 };
1451
1452 static struct resource dam_resource2[] = {
1453         [0] = {
1454                 .start = TEGRA_DAM2_BASE,
1455                 .end   = TEGRA_DAM2_BASE + TEGRA_DAM2_SIZE - 1,
1456                 .flags = IORESOURCE_MEM
1457         }
1458 };
1459
1460 struct platform_device tegra_dam_device2 = {
1461         .name = "tegra30-dam",
1462         .id = 2,
1463         .resource      = dam_resource2,
1464         .num_resources = ARRAY_SIZE(dam_resource2),
1465 };
1466
1467 static u64 tegra_hda_dma_mask = DMA_BIT_MASK(32);
1468 static struct resource hda_platform_resources[] = {
1469         [0] = {
1470                 .start  = TEGRA_HDA_BASE,
1471                 .end    = TEGRA_HDA_BASE + TEGRA_HDA_SIZE - 1,
1472                 .flags  = IORESOURCE_MEM
1473         },
1474         [1] = {
1475                 .start  = INT_HDA,
1476                 .end    = INT_HDA,
1477                 .flags  = IORESOURCE_IRQ
1478         },
1479 };
1480
1481 struct platform_device tegra_hda_device = {
1482         .name           = "tegra30-hda",
1483         .id             = -1,
1484         .dev = {
1485                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1486                 .dma_mask               = &tegra_hda_dma_mask,
1487         },
1488         .resource       = hda_platform_resources,
1489         .num_resources  = ARRAY_SIZE(hda_platform_resources),
1490 };
1491 #endif
1492
1493 struct platform_device spdif_dit_device = {
1494         .name = "spdif-dit",
1495         .id = 0,
1496 };
1497
1498 struct platform_device bluetooth_dit_device = {
1499         .name = "spdif-dit",
1500         .id = 1,
1501 };
1502
1503 struct platform_device baseband_dit_device = {
1504         .name = "spdif-dit",
1505         .id = 2,
1506 };
1507
1508 struct platform_device tegra_pcm_device = {
1509         .name = "tegra-pcm-audio",
1510         .id = -1,
1511 };
1512
1513 struct platform_device tegra_tdm_pcm_device = {
1514         .name = "tegra-tdm-pcm-audio",
1515         .id = -1,
1516 };
1517
1518 static struct resource w1_resources[] = {
1519         [0] = {
1520                 .start = INT_OWR,
1521                 .end   = INT_OWR,
1522                 .flags = IORESOURCE_IRQ
1523         },
1524         [1] = {
1525                 .start = TEGRA_OWR_BASE,
1526                 .end = TEGRA_OWR_BASE + TEGRA_OWR_SIZE - 1,
1527                 .flags = IORESOURCE_MEM
1528         }
1529 };
1530
1531 struct platform_device tegra_w1_device = {
1532         .name          = "tegra_w1",
1533         .id            = -1,
1534         .resource      = w1_resources,
1535         .num_resources = ARRAY_SIZE(w1_resources),
1536 };
1537
1538 static struct resource tegra_udc_resources[] = {
1539         [0] = {
1540                 .start  = TEGRA_USB_BASE,
1541                 .end    = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
1542                 .flags  = IORESOURCE_MEM,
1543         },
1544         [1] = {
1545                 .start  = INT_USB,
1546                 .end    = INT_USB,
1547                 .flags  = IORESOURCE_IRQ,
1548         },
1549 };
1550
1551 static u64 tegra_udc_dmamask = DMA_BIT_MASK(32);
1552
1553 struct platform_device tegra_udc_device = {
1554         .name   = "tegra-udc",
1555         .id     = 0,
1556         .dev    = {
1557                 .dma_mask       = &tegra_udc_dmamask,
1558                 .coherent_dma_mask = DMA_BIT_MASK(32),
1559         },
1560         .resource = tegra_udc_resources,
1561         .num_resources = ARRAY_SIZE(tegra_udc_resources),
1562 };
1563
1564 static struct resource tegra_otg_resources[] = {
1565         [0] = {
1566                 .start  = TEGRA_USB_BASE,
1567                 .end    = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
1568                 .flags  = IORESOURCE_MEM,
1569         },
1570         [1] = {
1571                 .start  = INT_USB,
1572                 .end    = INT_USB,
1573                 .flags  = IORESOURCE_IRQ,
1574         },
1575 };
1576
1577 struct platform_device tegra_otg_device = {
1578         .name           = "tegra-otg",
1579         .id             = -1,
1580         .resource       = tegra_otg_resources,
1581         .num_resources  = ARRAY_SIZE(tegra_otg_resources),
1582 };
1583
1584 #ifdef CONFIG_SATA_AHCI_TEGRA
1585 static u64 tegra_sata_dma_mask = DMA_BIT_MASK(32);
1586
1587 static struct resource tegra_sata_resources[] = {
1588         [0] = {
1589                 .start = TEGRA_SATA_BAR5_BASE,
1590                 .end = TEGRA_SATA_BAR5_BASE + TEGRA_SATA_BAR5_SIZE - 1,
1591                 .flags = IORESOURCE_MEM,
1592         },
1593         [1] = {
1594                 .start = TEGRA_SATA_CONFIG_BASE,
1595                 .end = TEGRA_SATA_CONFIG_BASE + TEGRA_SATA_CONFIG_SIZE - 1,
1596                 .flags = IORESOURCE_MEM,
1597         },
1598         [2] = {
1599                 .start = INT_SATA_CTL,
1600                 .end = INT_SATA_CTL,
1601                 .flags = IORESOURCE_IRQ,
1602         },
1603 };
1604
1605 struct platform_device tegra_sata_device = {
1606         .name   = "tegra-sata",
1607         .id     = 0,
1608         .dev    = {
1609                 .platform_data = 0,
1610                 .coherent_dma_mask = DMA_BIT_MASK(32),
1611                 .dma_mask = &tegra_sata_dma_mask,
1612         },
1613         .resource = tegra_sata_resources,
1614         .num_resources = ARRAY_SIZE(tegra_sata_resources),
1615 };
1616 #endif
1617
1618 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1619 static struct resource das_resource[] = {
1620         [0] = {
1621                 .start  = TEGRA_APB_MISC_DAS_BASE,
1622                 .end    = TEGRA_APB_MISC_DAS_BASE + TEGRA_APB_MISC_DAS_SIZE - 1,
1623                 .flags  = IORESOURCE_MEM
1624         }
1625 };
1626
1627 struct platform_device tegra_das_device = {
1628         .name           = "tegra20-das",
1629         .id             = -1,
1630         .resource       = das_resource,
1631         .num_resources  = ARRAY_SIZE(das_resource),
1632 };
1633 #endif
1634
1635 #if defined(CONFIG_TEGRA_IOVMM_GART) || defined(CONFIG_TEGRA_IOMMU_GART)
1636 static struct resource tegra_gart_resources[] = {
1637         [0] = {
1638                 .name   = "mc",
1639                 .flags  = IORESOURCE_MEM,
1640                 .start  = TEGRA_MC_BASE,
1641                 .end    = TEGRA_MC_BASE + TEGRA_MC_SIZE - 1,
1642         },
1643         [1] = {
1644                 .name   = "gart",
1645                 .flags  = IORESOURCE_MEM,
1646                 .start  = TEGRA_GART_BASE,
1647                 .end    = TEGRA_GART_BASE + TEGRA_GART_SIZE - 1,
1648         }
1649 };
1650
1651 struct platform_device tegra_gart_device = {
1652         .name           = "tegra_gart",
1653         .id             = -1,
1654         .num_resources  = ARRAY_SIZE(tegra_gart_resources),
1655         .resource       = tegra_gart_resources
1656 };
1657 #endif
1658
1659 #if defined(CONFIG_TEGRA_IOVMM_SMMU) || defined(CONFIG_TEGRA_IOMMU_SMMU)
1660 static struct resource tegra_smmu_resources[] = {
1661         {
1662                 .name   = "mc",
1663                 .flags  = IORESOURCE_MEM,
1664                 .start  = TEGRA_MC_BASE,
1665                 .end    = TEGRA_MC_BASE + TEGRA_MC_SIZE - 1,
1666         },
1667         {
1668                 .name   = "ahbarb",
1669                 .flags  = IORESOURCE_MEM,
1670                 .start  = TEGRA_AHB_ARB_BASE,
1671                 .end    = TEGRA_AHB_ARB_BASE + TEGRA_AHB_ARB_SIZE - 1,
1672         },
1673 };
1674
1675 struct platform_device tegra_smmu_device = {
1676         .name           = "tegra_smmu",
1677         .id             = -1,
1678         .num_resources  = ARRAY_SIZE(tegra_smmu_resources),
1679         .resource       = tegra_smmu_resources
1680 };
1681
1682 static struct resource tegra_smmu[] = {
1683         [0] = {
1684                 .start  = TEGRA_SMMU_BASE,
1685                 .end    = TEGRA_SMMU_BASE + TEGRA_SMMU_SIZE - 1,
1686         },
1687 };
1688
1689 struct resource *tegra_smmu_window(int wnum)
1690 {
1691         return &tegra_smmu[wnum];
1692 }
1693
1694 int tegra_smmu_window_count(void)
1695 {
1696         return ARRAY_SIZE(tegra_smmu);
1697 }
1698
1699 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
1700 static void tegra_smmu_map_init(struct platform_device *pdev)
1701 {
1702         struct dma_iommu_mapping *map;
1703
1704         map = arm_iommu_create_mapping(&platform_bus_type,
1705                                        TEGRA_IOMMU_BASE, TEGRA_IOMMU_SIZE, 0);
1706         if (IS_ERR(map))
1707                 dev_err(&pdev->dev, "Failed create IOVA map %08x-%08x\n",
1708                         TEGRA_IOMMU_BASE,
1709                         TEGRA_IOMMU_BASE + TEGRA_IOMMU_SIZE - 1);
1710 }
1711 #else
1712 static inline void tegra_smmu_map_init(struct platform_device *pdev)
1713 {
1714 }
1715 #endif
1716
1717 void tegra_smmu_init(void)
1718 {
1719         platform_device_register(&tegra_smmu_device);
1720         tegra_smmu_map_init(&tegra_smmu_device);
1721 }
1722 #endif
1723
1724 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
1725 #define CLK_RESET_RST_SOURCE    0x0
1726 static struct resource tegra_wdt_resources[] = {
1727         [0] = {
1728                 .start  = TEGRA_CLK_RESET_BASE + CLK_RESET_RST_SOURCE,
1729                 .end    = TEGRA_CLK_RESET_BASE + CLK_RESET_RST_SOURCE + 4 - 1,
1730                 .flags  = IORESOURCE_MEM,
1731         },
1732         [1] = {
1733                 .start  = TEGRA_TMR1_BASE,
1734                 .end    = TEGRA_TMR1_BASE + TEGRA_TMR1_SIZE - 1,
1735                 .flags  = IORESOURCE_MEM,
1736         },
1737         [2] = {
1738                 .start  = INT_TMR1,
1739                 .end    = INT_TMR1,
1740                 .flags  = IORESOURCE_IRQ,
1741         },
1742 };
1743
1744 struct platform_device tegra_wdt_device = {
1745         .name           = "tegra_wdt",
1746         .id             = -1,
1747         .num_resources  = ARRAY_SIZE(tegra_wdt_resources),
1748         .resource       = tegra_wdt_resources,
1749 };
1750 #else
1751 static struct resource tegra_wdt0_resources[] = {
1752         [0] = {
1753                 .start  = TEGRA_WDT0_BASE,
1754                 .end    = TEGRA_WDT0_BASE + TEGRA_WDT0_SIZE - 1,
1755                 .flags  = IORESOURCE_MEM,
1756         },
1757         [1] = {
1758                 .start  = TEGRA_TMR7_BASE,
1759                 .end    = TEGRA_TMR7_BASE + TEGRA_TMR7_SIZE - 1,
1760                 .flags  = IORESOURCE_MEM,
1761         },
1762         [2] = {
1763                 .start  = INT_WDT_CPU,
1764                 .end    = INT_WDT_CPU,
1765                 .flags  = IORESOURCE_IRQ,
1766         },
1767 #ifdef CONFIG_TEGRA_FIQ_DEBUGGER
1768         [3] = {
1769                 .start  = TEGRA_QUATERNARY_ICTLR_BASE,
1770                 .end    = TEGRA_QUATERNARY_ICTLR_BASE + \
1771                                 TEGRA_QUATERNARY_ICTLR_SIZE -1,
1772                 .flags  = IORESOURCE_MEM,
1773         },
1774 #endif
1775 };
1776
1777 static struct resource tegra_wdt1_resources[] = {
1778         [0] = {
1779                 .start  = TEGRA_WDT1_BASE,
1780                 .end    = TEGRA_WDT1_BASE + TEGRA_WDT1_SIZE - 1,
1781                 .flags  = IORESOURCE_MEM,
1782         },
1783         [1] = {
1784                 .start  = TEGRA_TMR8_BASE,
1785                 .end    = TEGRA_TMR8_BASE + TEGRA_TMR8_SIZE - 1,
1786                 .flags  = IORESOURCE_MEM,
1787         },
1788 };
1789
1790 static struct resource tegra_wdt2_resources[] = {
1791         [0] = {
1792                 .start  = TEGRA_WDT2_BASE,
1793                 .end    = TEGRA_WDT2_BASE + TEGRA_WDT2_SIZE - 1,
1794                 .flags  = IORESOURCE_MEM,
1795         },
1796         [1] = {
1797                 .start  = TEGRA_TMR9_BASE,
1798                 .end    = TEGRA_TMR9_BASE + TEGRA_TMR9_SIZE - 1,
1799                 .flags  = IORESOURCE_MEM,
1800         },
1801 };
1802
1803 struct platform_device tegra_wdt0_device = {
1804         .name           = "tegra_wdt",
1805         .id             = 0,
1806         .num_resources  = ARRAY_SIZE(tegra_wdt0_resources),
1807         .resource       = tegra_wdt0_resources,
1808 };
1809
1810 struct platform_device tegra_wdt1_device = {
1811         .name           = "tegra_wdt",
1812         .id             = 1,
1813         .num_resources  = ARRAY_SIZE(tegra_wdt1_resources),
1814         .resource       = tegra_wdt1_resources,
1815 };
1816
1817 struct platform_device tegra_wdt2_device = {
1818         .name           = "tegra_wdt",
1819         .id             = 2,
1820         .num_resources  = ARRAY_SIZE(tegra_wdt2_resources),
1821         .resource       = tegra_wdt2_resources,
1822 };
1823 #endif
1824
1825 static struct resource tegra_pwfm0_resource = {
1826         .start  = TEGRA_PWFM0_BASE,
1827         .end    = TEGRA_PWFM0_BASE + TEGRA_PWFM0_SIZE - 1,
1828         .flags  = IORESOURCE_MEM,
1829 };
1830
1831 static struct resource tegra_pwfm1_resource = {
1832         .start  = TEGRA_PWFM1_BASE,
1833         .end    = TEGRA_PWFM1_BASE + TEGRA_PWFM1_SIZE - 1,
1834         .flags  = IORESOURCE_MEM,
1835 };
1836
1837 static struct resource tegra_pwfm2_resource = {
1838         .start  = TEGRA_PWFM2_BASE,
1839         .end    = TEGRA_PWFM2_BASE + TEGRA_PWFM2_SIZE - 1,
1840         .flags  = IORESOURCE_MEM,
1841 };
1842
1843 static struct resource tegra_pwfm3_resource = {
1844         .start  = TEGRA_PWFM3_BASE,
1845         .end    = TEGRA_PWFM3_BASE + TEGRA_PWFM3_SIZE - 1,
1846         .flags  = IORESOURCE_MEM,
1847 };
1848
1849 struct platform_device tegra_pwfm0_device = {
1850         .name           = "tegra_pwm",
1851         .id             = 0,
1852         .num_resources  = 1,
1853         .resource       = &tegra_pwfm0_resource,
1854 };
1855
1856 struct platform_device tegra_pwfm1_device = {
1857         .name           = "tegra_pwm",
1858         .id             = 1,
1859         .num_resources  = 1,
1860         .resource       = &tegra_pwfm1_resource,
1861 };
1862
1863 struct platform_device tegra_pwfm2_device = {
1864         .name           = "tegra_pwm",
1865         .id             = 2,
1866         .num_resources  = 1,
1867         .resource       = &tegra_pwfm2_resource,
1868 };
1869
1870 struct platform_device tegra_pwfm3_device = {
1871         .name           = "tegra_pwm",
1872         .id             = 3,
1873         .num_resources  = 1,
1874         .resource       = &tegra_pwfm3_resource,
1875 };
1876
1877 static struct tegra_avp_platform_data tegra_avp_pdata = {
1878 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1879         .emc_clk_rate = ULONG_MAX,
1880 #else
1881         .emc_clk_rate = 200000000,
1882 #endif
1883 };
1884
1885 struct resource tegra_nvavp_resources[] = {
1886         [0] = {
1887                 .start  = INT_SHR_SEM_INBOX_IBF,
1888                 .end    = INT_SHR_SEM_INBOX_IBF,
1889                 .flags  = IORESOURCE_IRQ,
1890                 .name   = "mbox_from_nvavp_pending",
1891         },
1892 };
1893
1894 struct nvhost_device nvavp_device = {
1895         .name           = "nvavp",
1896         .id             = -1,
1897         .resource       = tegra_nvavp_resources,
1898         .num_resources  = ARRAY_SIZE(tegra_nvavp_resources),
1899 };
1900
1901 static struct resource tegra_avp_resources[] = {
1902         [0] = {
1903                 .start  = INT_SHR_SEM_INBOX_IBF,
1904                 .end    = INT_SHR_SEM_INBOX_IBF,
1905                 .flags  = IORESOURCE_IRQ,
1906                 .name   = "mbox_from_avp_pending",
1907         },
1908 };
1909
1910 struct platform_device tegra_avp_device = {
1911         .name           = "tegra-avp",
1912         .id             = -1,
1913         .num_resources  = ARRAY_SIZE(tegra_avp_resources),
1914         .resource       = tegra_avp_resources,
1915         .dev  = {
1916                 .coherent_dma_mask      = 0xffffffffULL,
1917                 .platform_data          = &tegra_avp_pdata,
1918         },
1919 };
1920
1921 static struct resource tegra_aes_resources[] = {
1922         {
1923                 .start  = TEGRA_VDE_BASE,
1924                 .end    = TEGRA_VDE_BASE + TEGRA_VDE_SIZE - 1,
1925                 .flags  = IORESOURCE_MEM,
1926         },
1927         {
1928                 .start  = TEGRA_BSEA_BASE,
1929                 .end    = TEGRA_BSEA_BASE + TEGRA_BSEA_SIZE - 1,
1930                 .flags  = IORESOURCE_MEM,
1931         },
1932         {
1933                 .start  = INT_VDE_BSE_V,
1934                 .end    = INT_VDE_BSE_V,
1935                 .flags  = IORESOURCE_IRQ,
1936         },
1937         {
1938                 .start  = INT_VDE_BSE_A,
1939                 .end    = INT_VDE_BSE_A,
1940                 .flags  = IORESOURCE_IRQ,
1941         },
1942 };
1943
1944 static u64 tegra_aes_dma_mask = DMA_BIT_MASK(32);
1945
1946 struct platform_device tegra_aes_device = {
1947         .name           = "tegra-aes",
1948         .id             = -1,
1949         .resource       = tegra_aes_resources,
1950         .num_resources  = ARRAY_SIZE(tegra_aes_resources),
1951         .dev    = {
1952                 .dma_mask = &tegra_aes_dma_mask,
1953                 .coherent_dma_mask = DMA_BIT_MASK(32),
1954         },
1955 };
1956
1957 static struct resource tegra_kbc_resources[] = {
1958         [0] = {
1959                 .start = TEGRA_KBC_BASE,
1960                 .end   = TEGRA_KBC_BASE + TEGRA_KBC_SIZE - 1,
1961                 .flags = IORESOURCE_MEM,
1962         },
1963         [1] = {
1964                 .start = INT_KBC,
1965                 .end   = INT_KBC,
1966                 .flags = IORESOURCE_IRQ,
1967         },
1968 };
1969
1970 struct platform_device tegra_kbc_device = {
1971         .name = "tegra-kbc",
1972         .id = -1,
1973         .resource = tegra_kbc_resources,
1974         .num_resources = ARRAY_SIZE(tegra_kbc_resources),
1975         .dev = {
1976                 .platform_data = 0,
1977         },
1978 };
1979
1980 #if defined(CONFIG_TEGRA_SKIN_THROTTLE)
1981 struct platform_device tegra_skin_therm_est_device = {
1982         .name   = "therm_est",
1983         .id     = -1,
1984         .num_resources  = 0,
1985         .dev = {
1986                 .platform_data = 0,
1987         },
1988 };
1989 #endif
1990
1991 #if defined(CONFIG_ARCH_TEGRA_3x_SOC)
1992 static struct resource tegra_tsensor_resources[]= {
1993         {
1994                 .start  = TEGRA_TSENSOR_BASE,
1995                 .end    = TEGRA_TSENSOR_BASE + TEGRA_TSENSOR_SIZE - 1,
1996                 .flags  = IORESOURCE_MEM,
1997         },
1998         {
1999                 .start  = INT_TSENSOR,
2000                 .end    = INT_TSENSOR,
2001                 .flags  = IORESOURCE_IRQ,
2002         },
2003         {
2004                 .start  = TEGRA_PMC_BASE + 0x1B0,
2005                 /* 2 pmc registers mapped */
2006                 .end    = TEGRA_PMC_BASE + 0x1B0 + (2 * 4),
2007                 .flags  = IORESOURCE_MEM,
2008         },
2009 };
2010
2011 struct platform_device tegra_tsensor_device = {
2012         .name   = "tegra-tsensor",
2013         .id     = -1,
2014         .num_resources  = ARRAY_SIZE(tegra_tsensor_resources),
2015         .resource       = tegra_tsensor_resources,
2016         .dev = {
2017                 .platform_data = 0,
2018         },
2019 };
2020 #endif
2021
2022 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
2023 static u64 tegra_se_dma_mask = DMA_BIT_MASK(32);
2024
2025 struct resource tegra_se_resources[] = {
2026         [0] = {
2027                 .start = TEGRA_SE_BASE,
2028                 .end = TEGRA_SE_BASE + TEGRA_SE_SIZE - 1,
2029                 .flags = IORESOURCE_MEM,
2030         },
2031         [1] = {
2032                 .start  = TEGRA_PMC_BASE,
2033                 .end    = TEGRA_PMC_BASE + SZ_256 - 1,
2034                 .flags  = IORESOURCE_MEM,
2035         },
2036         [2] = {
2037                 .start = INT_SE,
2038                 .end = INT_SE,
2039                 .flags = IORESOURCE_IRQ,
2040         },
2041 };
2042
2043 struct platform_device tegra_se_device = {
2044         .name = "tegra-se",
2045         .id = -1,
2046         .dev = {
2047                 .coherent_dma_mask = DMA_BIT_MASK(32),
2048                 .dma_mask = &tegra_se_dma_mask,
2049         },
2050         .resource = tegra_se_resources,
2051         .num_resources = ARRAY_SIZE(tegra_se_resources),
2052 };
2053
2054 struct platform_device tegra11_se_device = {
2055         .name = "tegra11-se",
2056         .id = -1,
2057         .dev = {
2058                 .coherent_dma_mask = DMA_BIT_MASK(32),
2059                 .dma_mask = &tegra_se_dma_mask,
2060         },
2061         .resource = tegra_se_resources,
2062         .num_resources = ARRAY_SIZE(tegra_se_resources),
2063 };
2064 #endif
2065
2066 static struct resource tegra_disp1_resources[] = {
2067         {
2068                 .name   = "irq",
2069                 .start  = INT_DISPLAY_GENERAL,
2070                 .end    = INT_DISPLAY_GENERAL,
2071                 .flags  = IORESOURCE_IRQ,
2072         },
2073         {
2074                 .name   = "regs",
2075                 .start  = TEGRA_DISPLAY_BASE,
2076                 .end    = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE-1,
2077                 .flags  = IORESOURCE_MEM,
2078         },
2079         {
2080                 .name   = "fbmem",
2081                 .start  = 0,
2082                 .end    = 0,
2083                 .flags  = IORESOURCE_MEM,
2084         },
2085         {
2086                 .name   = "dsi_regs",
2087                 .start  = TEGRA_DSI_BASE,
2088                 .end    = TEGRA_DSI_BASE + TEGRA_DSI_SIZE - 1,
2089                 .flags  = IORESOURCE_MEM,
2090         },
2091 };
2092
2093 struct nvhost_device tegra_disp1_device = {
2094         .name           = "tegradc",
2095         .id             = 0,
2096         .resource       = tegra_disp1_resources,
2097         .num_resources  = ARRAY_SIZE(tegra_disp1_resources),
2098 };
2099
2100 static struct resource tegra_disp2_resources[] = {
2101         {
2102                 .name   = "irq",
2103                 .start  = INT_DISPLAY_B_GENERAL,
2104                 .end    = INT_DISPLAY_B_GENERAL,
2105                 .flags  = IORESOURCE_IRQ,
2106         },
2107         {
2108                 .name   = "regs",
2109                 .start  = TEGRA_DISPLAY2_BASE,
2110                 .end    = TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1,
2111                 .flags  = IORESOURCE_MEM,
2112         },
2113         {
2114                 .name   = "fbmem",
2115                 .flags  = IORESOURCE_MEM,
2116                 .start  = 0,
2117                 .end    = 0,
2118         },
2119         {
2120                 .name   = "hdmi_regs",
2121                 .start  = TEGRA_HDMI_BASE,
2122                 .end    = TEGRA_HDMI_BASE + TEGRA_HDMI_SIZE - 1,
2123                 .flags  = IORESOURCE_MEM,
2124         },
2125 };
2126
2127 struct nvhost_device tegra_disp2_device = {
2128         .name           = "tegradc",
2129         .id             = 1,
2130         .resource       = tegra_disp2_resources,
2131         .num_resources  = ARRAY_SIZE(tegra_disp2_resources),
2132         .dev = {
2133                 .platform_data = 0,
2134         },
2135 };
2136
2137 struct platform_device tegra_nvmap_device = {
2138         .name   = "tegra-nvmap",
2139         .id     = -1,
2140 };
2141
2142 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2143 static struct resource tegra_cec_resources[] = {
2144         [0] = {
2145                 .start = TEGRA_CEC_BASE,
2146                 .end = TEGRA_CEC_BASE + TEGRA_CEC_SIZE - 1,
2147                 .flags = IORESOURCE_MEM,
2148         },
2149         [1] = {
2150                 .start = INT_CEC,
2151                 .end = INT_CEC,
2152                 .flags = IORESOURCE_IRQ,
2153         },
2154 };
2155
2156 struct platform_device tegra_cec_device = {
2157         .name = "tegra_cec",
2158         .id   = -1,
2159         .resource = tegra_cec_resources,
2160         .num_resources = ARRAY_SIZE(tegra_cec_resources),
2161 };
2162 #endif
2163
2164 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
2165 static struct resource cl_dvfs_resource[] = {
2166         [0] = {
2167                 .start  = TEGRA_CL_DVFS_BASE,
2168                 .end    = TEGRA_CL_DVFS_BASE + TEGRA_CL_DVFS_SIZE-1,
2169                 .flags  = IORESOURCE_MEM,
2170         }
2171 };
2172
2173 struct platform_device tegra_cl_dvfs_device = {
2174         .name           = "tegra_cl_dvfs",
2175         .id             = -1,
2176         .resource       = cl_dvfs_resource,
2177         .num_resources  = ARRAY_SIZE(cl_dvfs_resource),
2178 };
2179 #endif
2180
2181 void __init tegra_init_debug_uart_rate(void)
2182 {
2183         unsigned int uartclk;
2184         struct clk *debug_uart_parent = clk_get_sys(NULL, "pll_p");
2185
2186         BUG_ON(IS_ERR(debug_uart_parent));
2187         uartclk = clk_get_rate(debug_uart_parent);
2188
2189         debug_uarta_platform_data[0].uartclk = uartclk;
2190         debug_uartb_platform_data[0].uartclk = uartclk;
2191         debug_uartc_platform_data[0].uartclk = uartclk;
2192         debug_uartd_platform_data[0].uartclk = uartclk;
2193 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
2194         debug_uarte_platform_data[0].uartclk = uartclk;
2195 #endif
2196 }