ARM: IOMMU: Tegra20: Add iommu_ops for GART driver
[linux-2.6.git] / arch / arm / mach-tegra / devices.c
1 /*
2  * Copyright (C) 2010,2011 Google, Inc.
3  *
4  * Author:
5  *      Colin Cross <ccross@android.com>
6  *      Erik Gilling <ccross@android.com>
7  *
8  * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
9  *
10  * This software is licensed under the terms of the GNU General Public
11  * License version 2, as published by the Free Software Foundation, and
12  * may be copied, distributed, and modified under those terms.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  */
20
21
22 #include <linux/resource.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/fsl_devices.h>
25 #include <linux/serial_8250.h>
26 #include <linux/i2c-tegra.h>
27 #include <linux/platform_data/tegra_usb.h>
28 #include <linux/tegra_avp.h>
29 #include <linux/nvhost.h>
30 #include <asm/pmu.h>
31 #include <mach/irqs.h>
32 #include <mach/iomap.h>
33 #include <mach/dma.h>
34 #include <mach/usb_phy.h>
35 #include <mach/tegra_smmu.h>
36
37 #include "gpio-names.h"
38 #include "devices.h"
39
40 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
41 #define UART_SOURCE_RATE 408000000
42 #else
43 #define UART_SOURCE_RATE 216000000
44 #endif
45
46 static struct resource i2c_resource1[] = {
47         [0] = {
48                 .start  = INT_I2C,
49                 .end    = INT_I2C,
50                 .flags  = IORESOURCE_IRQ,
51         },
52         [1] = {
53                 .start  = TEGRA_I2C_BASE,
54                 .end    = TEGRA_I2C_BASE + TEGRA_I2C_SIZE-1,
55                 .flags  = IORESOURCE_MEM,
56         },
57 };
58
59 static struct resource i2c_resource2[] = {
60         [0] = {
61                 .start  = INT_I2C2,
62                 .end    = INT_I2C2,
63                 .flags  = IORESOURCE_IRQ,
64         },
65         [1] = {
66                 .start  = TEGRA_I2C2_BASE,
67                 .end    = TEGRA_I2C2_BASE + TEGRA_I2C2_SIZE-1,
68                 .flags  = IORESOURCE_MEM,
69         },
70 };
71
72 static struct resource i2c_resource3[] = {
73         [0] = {
74                 .start  = INT_I2C3,
75                 .end    = INT_I2C3,
76                 .flags  = IORESOURCE_IRQ,
77         },
78         [1] = {
79                 .start  = TEGRA_I2C3_BASE,
80                 .end    = TEGRA_I2C3_BASE + TEGRA_I2C3_SIZE-1,
81                 .flags  = IORESOURCE_MEM,
82         },
83 };
84
85 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
86 static struct resource i2c_resource4[] = {
87         [0] = {
88                 .start  = INT_DVC,
89                 .end    = INT_DVC,
90                 .flags  = IORESOURCE_IRQ,
91         },
92         [1] = {
93                 .start  = TEGRA_DVC_BASE,
94                 .end    = TEGRA_DVC_BASE + TEGRA_DVC_SIZE-1,
95                 .flags  = IORESOURCE_MEM,
96         },
97 };
98
99 #else
100 static struct resource i2c_resource4[] = {
101         [0] = {
102                 .start  = INT_I2C4,
103                 .end    = INT_I2C4,
104                 .flags  = IORESOURCE_IRQ,
105         },
106         [1] = {
107                 .start  = TEGRA_I2C4_BASE,
108                 .end    = TEGRA_I2C4_BASE + TEGRA_I2C4_SIZE-1,
109                 .flags  = IORESOURCE_MEM,
110         },
111 };
112
113 static struct resource i2c_resource5[] = {
114         [0] = {
115                 .start  = INT_I2C5,
116                 .end    = INT_I2C5,
117                 .flags  = IORESOURCE_IRQ,
118         },
119         [1] = {
120                 .start  = TEGRA_I2C5_BASE,
121                 .end    = TEGRA_I2C5_BASE + TEGRA_I2C5_SIZE-1,
122                 .flags  = IORESOURCE_MEM,
123         },
124 };
125 #endif
126
127 static struct tegra_i2c_platform_data tegra_i2c1_platform_data = {
128         .bus_clk_rate   = { 400000 },
129 };
130
131 static struct tegra_i2c_platform_data tegra_i2c2_platform_data = {
132         .bus_clk_rate   = { 400000 },
133 };
134
135 static struct tegra_i2c_platform_data tegra_i2c3_platform_data = {
136         .bus_clk_rate   = { 400000 },
137 };
138
139 static struct tegra_i2c_platform_data tegra_dvc_platform_data = {
140         .bus_clk_rate   = { 400000 },
141 };
142
143 struct platform_device tegra_i2c_device1 = {
144         .name           = "tegra-i2c",
145         .id             = 0,
146         .resource       = i2c_resource1,
147         .num_resources  = ARRAY_SIZE(i2c_resource1),
148         .dev = {
149                 .platform_data = &tegra_i2c1_platform_data,
150         },
151 };
152
153 struct platform_device tegra_i2c_device2 = {
154         .name           = "tegra-i2c",
155         .id             = 1,
156         .resource       = i2c_resource2,
157         .num_resources  = ARRAY_SIZE(i2c_resource2),
158         .dev = {
159                 .platform_data = &tegra_i2c2_platform_data,
160         },
161 };
162
163 struct platform_device tegra_i2c_device3 = {
164         .name           = "tegra-i2c",
165         .id             = 2,
166         .resource       = i2c_resource3,
167         .num_resources  = ARRAY_SIZE(i2c_resource3),
168         .dev = {
169                 .platform_data = &tegra_i2c3_platform_data,
170         },
171 };
172
173 struct platform_device tegra_i2c_device4 = {
174         .name           = "tegra-i2c",
175         .id             = 3,
176         .resource       = i2c_resource4,
177         .num_resources  = ARRAY_SIZE(i2c_resource4),
178         .dev = {
179                 .platform_data = &tegra_dvc_platform_data,
180         },
181 };
182
183 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
184 struct platform_device tegra_i2c_device5 = {
185         .name           = "tegra-i2c",
186         .id             = 4,
187         .resource       = i2c_resource5,
188         .num_resources  = ARRAY_SIZE(i2c_resource5),
189         .dev = {
190                 .platform_data = 0,
191         },
192 };
193 #endif
194
195 static struct resource spi_resource1[] = {
196         [0] = {
197                 .start  = INT_SPI_1,
198                 .end    = INT_SPI_1,
199                 .flags  = IORESOURCE_IRQ,
200         },
201         [1] = {
202                 .start  = TEGRA_SPI1_BASE,
203                 .end    = TEGRA_SPI1_BASE + TEGRA_SPI1_SIZE-1,
204                 .flags  = IORESOURCE_MEM,
205         },
206 };
207
208 static struct resource spi_resource2[] = {
209         [0] = {
210                 .start  = INT_SPI_2,
211                 .end    = INT_SPI_2,
212                 .flags  = IORESOURCE_IRQ,
213         },
214         [1] = {
215                 .start  = TEGRA_SPI2_BASE,
216                 .end    = TEGRA_SPI2_BASE + TEGRA_SPI2_SIZE-1,
217                 .flags  = IORESOURCE_MEM,
218         },
219 };
220
221 static struct resource spi_resource3[] = {
222         [0] = {
223                 .start  = INT_SPI_3,
224                 .end    = INT_SPI_3,
225                 .flags  = IORESOURCE_IRQ,
226         },
227         [1] = {
228                 .start  = TEGRA_SPI3_BASE,
229                 .end    = TEGRA_SPI3_BASE + TEGRA_SPI3_SIZE-1,
230                 .flags  = IORESOURCE_MEM,
231         },
232 };
233
234 static struct resource spi_resource4[] = {
235         [0] = {
236                 .start  = INT_SPI_4,
237                 .end    = INT_SPI_4,
238                 .flags  = IORESOURCE_IRQ,
239         },
240         [1] = {
241                 .start  = TEGRA_SPI4_BASE,
242                 .end    = TEGRA_SPI4_BASE + TEGRA_SPI4_SIZE-1,
243                 .flags  = IORESOURCE_MEM,
244         },
245 };
246 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
247 static struct resource spi_resource5[] = {
248         [0] = {
249                 .start  = INT_SPI_5,
250                 .end    = INT_SPI_5,
251                 .flags  = IORESOURCE_IRQ,
252         },
253         [1] = {
254                 .start  = TEGRA_SPI5_BASE,
255                 .end    = TEGRA_SPI5_BASE + TEGRA_SPI5_SIZE-1,
256                 .flags  = IORESOURCE_MEM,
257         },
258 };
259
260 static struct resource spi_resource6[] = {
261         [0] = {
262                 .start  = INT_SPI_6,
263                 .end    = INT_SPI_6,
264                 .flags  = IORESOURCE_IRQ,
265         },
266         [1] = {
267                 .start  = TEGRA_SPI6_BASE,
268                 .end    = TEGRA_SPI6_BASE + TEGRA_SPI6_SIZE-1,
269                 .flags  = IORESOURCE_MEM,
270         },
271 };
272 #endif
273
274 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
275 static struct resource dtv_resource[] = {
276         [0] = {
277                 .start  = INT_DTV,
278                 .end    = INT_DTV,
279                 .flags  = IORESOURCE_IRQ,
280         },
281         [1] = {
282                 .start  = TEGRA_DTV_BASE,
283                 .end    = TEGRA_DTV_BASE + TEGRA_DTV_SIZE - 1,
284                 .flags  = IORESOURCE_MEM,
285         },
286         [2] = {
287                 .start  = TEGRA_DMA_REQ_SEL_DTV,
288                 .end    = TEGRA_DMA_REQ_SEL_DTV,
289                 .flags  = IORESOURCE_DMA
290         },
291 };
292 #endif
293
294
295 struct platform_device tegra_spi_device1 = {
296         .name           = "spi_tegra",
297         .id             = 0,
298         .resource       = spi_resource1,
299         .num_resources  = ARRAY_SIZE(spi_resource1),
300         .dev            = {
301                 .coherent_dma_mask      = 0xffffffff,
302         },
303 };
304
305 struct platform_device tegra_spi_device2 = {
306         .name           = "spi_tegra",
307         .id             = 1,
308         .resource       = spi_resource2,
309         .num_resources  = ARRAY_SIZE(spi_resource2),
310         .dev            = {
311                 .coherent_dma_mask      = 0xffffffff,
312         },
313 };
314
315 struct platform_device tegra_spi_device3 = {
316         .name           = "spi_tegra",
317         .id             = 2,
318         .resource       = spi_resource3,
319         .num_resources  = ARRAY_SIZE(spi_resource3),
320         .dev            = {
321                 .coherent_dma_mask      = 0xffffffff,
322         },
323 };
324
325 struct platform_device tegra_spi_device4 = {
326         .name           = "spi_tegra",
327         .id             = 3,
328         .resource       = spi_resource4,
329         .num_resources  = ARRAY_SIZE(spi_resource4),
330         .dev            = {
331                 .coherent_dma_mask      = 0xffffffff,
332         },
333 };
334 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
335 struct platform_device tegra_spi_device5 = {
336         .name           = "spi_tegra",
337         .id             = 4,
338         .resource       = spi_resource5,
339         .num_resources  = ARRAY_SIZE(spi_resource5),
340         .dev  = {
341                 .coherent_dma_mask      = 0xffffffff,
342         },
343 };
344
345 struct platform_device tegra_spi_device6 = {
346         .name           = "spi_tegra",
347         .id             = 5,
348         .resource       = spi_resource6,
349         .num_resources  = ARRAY_SIZE(spi_resource6),
350         .dev  = {
351                 .coherent_dma_mask      = 0xffffffff,
352         },
353 };
354 #endif
355
356 struct platform_device tegra_spi_slave_device1 = {
357         .name           = "spi_slave_tegra",
358         .id             = 0,
359         .resource       = spi_resource1,
360         .num_resources  = ARRAY_SIZE(spi_resource1),
361         .dev  = {
362                 .coherent_dma_mask      = 0xffffffff,
363         },
364 };
365
366 struct platform_device tegra_spi_slave_device2 = {
367         .name           = "spi_slave_tegra",
368         .id             = 1,
369         .resource       = spi_resource2,
370         .num_resources  = ARRAY_SIZE(spi_resource2),
371         .dev  = {
372                 .coherent_dma_mask      = 0xffffffff,
373         },
374 };
375
376 struct platform_device tegra_spi_slave_device3 = {
377         .name           = "spi_slave_tegra",
378         .id             = 2,
379         .resource       = spi_resource3,
380         .num_resources  = ARRAY_SIZE(spi_resource3),
381         .dev  = {
382                 .coherent_dma_mask      = 0xffffffff,
383         },
384 };
385
386 struct platform_device tegra_spi_slave_device4 = {
387         .name           = "spi_slave_tegra",
388         .id             = 3,
389         .resource       = spi_resource4,
390         .num_resources  = ARRAY_SIZE(spi_resource4),
391         .dev  = {
392                 .coherent_dma_mask      = 0xffffffff,
393         },
394 };
395 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
396 struct platform_device tegra_spi_slave_device5 = {
397         .name           = "spi_slave_tegra",
398         .id             = 4,
399         .resource       = spi_resource5,
400         .num_resources  = ARRAY_SIZE(spi_resource5),
401         .dev  = {
402                 .coherent_dma_mask      = 0xffffffff,
403         },
404 };
405
406 struct platform_device tegra_spi_slave_device6 = {
407         .name           = "spi_slave_tegra",
408         .id             = 5,
409         .resource       = spi_resource6,
410         .num_resources  = ARRAY_SIZE(spi_resource6),
411         .dev  = {
412                 .coherent_dma_mask      = 0xffffffff,
413         },
414 };
415 #endif
416
417 static struct resource resources_nor[] = {
418         [0] = {
419                 .start = INT_SNOR,
420                 .end = INT_SNOR,
421                 .flags = IORESOURCE_IRQ,
422         },
423         [1] = {
424                 /* Map SNOR Controller */
425                 .start = TEGRA_SNOR_BASE,
426                 .end = TEGRA_SNOR_BASE + TEGRA_SNOR_SIZE - 1,
427                 .flags = IORESOURCE_MEM,
428         },
429         [2] = {
430                 /* Map the size of flash */
431                 .start = TEGRA_NOR_FLASH_BASE,
432                 .end = TEGRA_NOR_FLASH_BASE + TEGRA_NOR_FLASH_SIZE - 1,
433                 .flags = IORESOURCE_MEM,
434         }
435 };
436
437 struct platform_device tegra_nor_device = {
438         .name = "tegra-nor",
439         .id = -1,
440         .num_resources = ARRAY_SIZE(resources_nor),
441         .resource = resources_nor,
442         .dev = {
443                 .coherent_dma_mask = 0xffffffff,
444         },
445 };
446
447 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
448 struct platform_device tegra_dtv_device = {
449         .name           = "tegra_dtv",
450         .id             = -1,
451         .resource       = dtv_resource,
452         .num_resources  = ARRAY_SIZE(dtv_resource),
453         .dev = {
454                 .init_name = "dtv",
455                 .coherent_dma_mask = 0xffffffff,
456         },
457 };
458 #endif
459
460 static struct resource sdhci_resource1[] = {
461         [0] = {
462                 .start  = INT_SDMMC1,
463                 .end    = INT_SDMMC1,
464                 .flags  = IORESOURCE_IRQ,
465         },
466         [1] = {
467                 .start  = TEGRA_SDMMC1_BASE,
468                 .end    = TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE-1,
469                 .flags  = IORESOURCE_MEM,
470         },
471 };
472
473 static struct resource sdhci_resource2[] = {
474         [0] = {
475                 .start  = INT_SDMMC2,
476                 .end    = INT_SDMMC2,
477                 .flags  = IORESOURCE_IRQ,
478         },
479         [1] = {
480                 .start  = TEGRA_SDMMC2_BASE,
481                 .end    = TEGRA_SDMMC2_BASE + TEGRA_SDMMC2_SIZE-1,
482                 .flags  = IORESOURCE_MEM,
483         },
484 };
485
486 static struct resource sdhci_resource3[] = {
487         [0] = {
488                 .start  = INT_SDMMC3,
489                 .end    = INT_SDMMC3,
490                 .flags  = IORESOURCE_IRQ,
491         },
492         [1] = {
493                 .start  = TEGRA_SDMMC3_BASE,
494                 .end    = TEGRA_SDMMC3_BASE + TEGRA_SDMMC3_SIZE-1,
495                 .flags  = IORESOURCE_MEM,
496         },
497 };
498
499 static struct resource sdhci_resource4[] = {
500         [0] = {
501                 .start  = INT_SDMMC4,
502                 .end    = INT_SDMMC4,
503                 .flags  = IORESOURCE_IRQ,
504         },
505         [1] = {
506                 .start  = TEGRA_SDMMC4_BASE,
507                 .end    = TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE-1,
508                 .flags  = IORESOURCE_MEM,
509         },
510 };
511
512 struct platform_device tegra_pci_device = {
513         .name           = "tegra-pcie",
514         .id             = 0,
515         .resource       = 0,
516         .num_resources  = 0,
517         .dev = {
518                 .platform_data = 0,
519         },
520 };
521
522 /* board files should fill in platform_data register the devices themselvs.
523  * See board-harmony.c for an example
524  */
525 struct platform_device tegra_sdhci_device1 = {
526         .name           = "sdhci-tegra",
527         .id             = 0,
528         .resource       = sdhci_resource1,
529         .num_resources  = ARRAY_SIZE(sdhci_resource1),
530 };
531
532 struct platform_device tegra_sdhci_device2 = {
533         .name           = "sdhci-tegra",
534         .id             = 1,
535         .resource       = sdhci_resource2,
536         .num_resources  = ARRAY_SIZE(sdhci_resource2),
537 };
538
539 struct platform_device tegra_sdhci_device3 = {
540         .name           = "sdhci-tegra",
541         .id             = 2,
542         .resource       = sdhci_resource3,
543         .num_resources  = ARRAY_SIZE(sdhci_resource3),
544 };
545
546 struct platform_device tegra_sdhci_device4 = {
547         .name           = "sdhci-tegra",
548         .id             = 3,
549         .resource       = sdhci_resource4,
550         .num_resources  = ARRAY_SIZE(sdhci_resource4),
551 };
552
553 static struct resource tegra_usb1_resources[] = {
554         [0] = {
555                 .start  = TEGRA_USB_BASE,
556                 .end    = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
557                 .flags  = IORESOURCE_MEM,
558         },
559         [1] = {
560                 .start  = INT_USB,
561                 .end    = INT_USB,
562                 .flags  = IORESOURCE_IRQ,
563         },
564 };
565
566 static struct resource tegra_usb2_resources[] = {
567         [0] = {
568                 .start  = TEGRA_USB2_BASE,
569                 .end    = TEGRA_USB2_BASE + TEGRA_USB2_SIZE - 1,
570                 .flags  = IORESOURCE_MEM,
571         },
572         [1] = {
573                 .start  = INT_USB2,
574                 .end    = INT_USB2,
575                 .flags  = IORESOURCE_IRQ,
576         },
577 };
578
579 static struct resource tegra_usb3_resources[] = {
580         [0] = {
581                 .start  = TEGRA_USB3_BASE,
582                 .end    = TEGRA_USB3_BASE + TEGRA_USB3_SIZE - 1,
583                 .flags  = IORESOURCE_MEM,
584         },
585         [1] = {
586                 .start  = INT_USB3,
587                 .end    = INT_USB3,
588                 .flags  = IORESOURCE_IRQ,
589         },
590 };
591
592 static struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
593         /* All existing boards use GPIO PV0 for phy reset */
594         .reset_gpio = TEGRA_GPIO_PV0,
595         .clk = "cdev2",
596 };
597
598 static struct tegra_ehci_platform_data tegra_ehci1_pdata = {
599         .operating_mode = TEGRA_USB_OTG,
600         .power_down_on_bus_suspend = 1,
601 };
602
603 static struct tegra_ehci_platform_data tegra_ehci2_pdata = {
604         .phy_config = &tegra_ehci2_ulpi_phy_config,
605         .operating_mode = TEGRA_USB_HOST,
606         .power_down_on_bus_suspend = 1,
607 };
608
609 static struct tegra_ehci_platform_data tegra_ehci3_pdata = {
610         .operating_mode = TEGRA_USB_HOST,
611         .power_down_on_bus_suspend = 1,
612 };
613
614 static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32);
615
616 struct platform_device tegra_ehci1_device = {
617         .name   = "tegra-ehci",
618         .id     = 0,
619         .dev    = {
620                 .dma_mask       = &tegra_ehci_dmamask,
621                 .coherent_dma_mask = DMA_BIT_MASK(32),
622                 .platform_data = &tegra_ehci1_pdata,
623         },
624         .resource = tegra_usb1_resources,
625         .num_resources = ARRAY_SIZE(tegra_usb1_resources),
626 };
627
628 struct platform_device tegra_ehci2_device = {
629         .name   = "tegra-ehci",
630         .id     = 1,
631         .dev    = {
632                 .dma_mask       = &tegra_ehci_dmamask,
633                 .coherent_dma_mask = DMA_BIT_MASK(32),
634                 .platform_data = &tegra_ehci2_pdata,
635         },
636         .resource = tegra_usb2_resources,
637         .num_resources = ARRAY_SIZE(tegra_usb2_resources),
638 };
639
640 struct platform_device tegra_ehci3_device = {
641         .name   = "tegra-ehci",
642         .id     = 2,
643         .dev    = {
644                 .dma_mask       = &tegra_ehci_dmamask,
645                 .coherent_dma_mask = DMA_BIT_MASK(32),
646                 .platform_data = &tegra_ehci3_pdata,
647         },
648         .resource = tegra_usb3_resources,
649         .num_resources = ARRAY_SIZE(tegra_usb3_resources),
650 };
651
652 static struct resource tegra_pmu_resources[] = {
653         [0] = {
654                 .start  = INT_CPU0_PMU_INTR,
655                 .end    = INT_CPU0_PMU_INTR,
656                 .flags  = IORESOURCE_IRQ,
657         },
658         [1] = {
659                 .start  = INT_CPU1_PMU_INTR,
660                 .end    = INT_CPU1_PMU_INTR,
661                 .flags  = IORESOURCE_IRQ,
662         },
663 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
664         [2] = {
665                 .start  = INT_CPU2_PMU_INTR,
666                 .end    = INT_CPU2_PMU_INTR,
667                 .flags  = IORESOURCE_IRQ,
668         },
669         [3] = {
670                 .start  = INT_CPU3_PMU_INTR,
671                 .end    = INT_CPU3_PMU_INTR,
672                 .flags  = IORESOURCE_IRQ,
673         },
674 #endif
675 };
676
677 struct platform_device tegra_pmu_device = {
678         .name           = "arm-pmu",
679         .id             = ARM_PMU_DEVICE_CPU,
680         .num_resources  = ARRAY_SIZE(tegra_pmu_resources),
681         .resource       = tegra_pmu_resources,
682 };
683
684 static struct resource tegra_uarta_resources[] = {
685         [0] = {
686                 .start  = TEGRA_UARTA_BASE,
687                 .end    = TEGRA_UARTA_BASE + TEGRA_UARTA_SIZE - 1,
688                 .flags  = IORESOURCE_MEM,
689         },
690         [1] = {
691                 .start  = INT_UARTA,
692                 .end    = INT_UARTA,
693                 .flags  = IORESOURCE_IRQ,
694         },
695 };
696
697 static struct resource tegra_uartb_resources[] = {
698         [0] = {
699                 .start  = TEGRA_UARTB_BASE,
700                 .end    = TEGRA_UARTB_BASE + TEGRA_UARTB_SIZE - 1,
701                 .flags  = IORESOURCE_MEM,
702         },
703         [1] = {
704                 .start  = INT_UARTB,
705                 .end    = INT_UARTB,
706                 .flags  = IORESOURCE_IRQ,
707         },
708 };
709
710 static struct resource tegra_uartc_resources[] = {
711         [0] = {
712                 .start  = TEGRA_UARTC_BASE,
713                 .end    = TEGRA_UARTC_BASE + TEGRA_UARTC_SIZE - 1,
714                 .flags  = IORESOURCE_MEM,
715         },
716         [1] = {
717                 .start  = INT_UARTC,
718                 .end    = INT_UARTC,
719                 .flags  = IORESOURCE_IRQ,
720         },
721 };
722
723 static struct resource tegra_uartd_resources[] = {
724         [0] = {
725                 .start  = TEGRA_UARTD_BASE,
726                 .end    = TEGRA_UARTD_BASE + TEGRA_UARTD_SIZE - 1,
727                 .flags  = IORESOURCE_MEM,
728         },
729         [1] = {
730                 .start  = INT_UARTD,
731                 .end    = INT_UARTD,
732                 .flags  = IORESOURCE_IRQ,
733         },
734 };
735
736 static struct resource tegra_uarte_resources[] = {
737         [0] = {
738                 .start  = TEGRA_UARTE_BASE,
739                 .end    = TEGRA_UARTE_BASE + TEGRA_UARTE_SIZE - 1,
740                 .flags  = IORESOURCE_MEM,
741         },
742         [1] = {
743                 .start  = INT_UARTE,
744                 .end    = INT_UARTE,
745                 .flags  = IORESOURCE_IRQ,
746         },
747 };
748
749 struct platform_device tegra_uarta_device = {
750         .name   = "tegra_uart",
751         .id     = 0,
752         .num_resources  = ARRAY_SIZE(tegra_uarta_resources),
753         .resource       = tegra_uarta_resources,
754         .dev    = {
755                 .coherent_dma_mask      = DMA_BIT_MASK(32),
756         },
757 };
758
759 struct platform_device tegra_uartb_device = {
760         .name   = "tegra_uart",
761         .id     = 1,
762         .num_resources  = ARRAY_SIZE(tegra_uartb_resources),
763         .resource       = tegra_uartb_resources,
764         .dev    = {
765                 .coherent_dma_mask      = DMA_BIT_MASK(32),
766         },
767 };
768
769 struct platform_device tegra_uartc_device = {
770         .name   = "tegra_uart",
771         .id     = 2,
772         .num_resources  = ARRAY_SIZE(tegra_uartc_resources),
773         .resource       = tegra_uartc_resources,
774         .dev    = {
775                 .coherent_dma_mask      = DMA_BIT_MASK(32),
776         },
777 };
778
779 struct platform_device tegra_uartd_device = {
780         .name   = "tegra_uart",
781         .id     = 3,
782         .num_resources  = ARRAY_SIZE(tegra_uartd_resources),
783         .resource       = tegra_uartd_resources,
784         .dev    = {
785                 .coherent_dma_mask      = DMA_BIT_MASK(32),
786         },
787 };
788
789 struct platform_device tegra_uarte_device = {
790         .name   = "tegra_uart",
791         .id     = 4,
792         .num_resources  = ARRAY_SIZE(tegra_uarte_resources),
793         .resource       = tegra_uarte_resources,
794         .dev    = {
795                 .coherent_dma_mask      = DMA_BIT_MASK(32),
796         },
797 };
798
799 static struct plat_serial8250_port debug_uarta_platform_data[] = {
800         {
801                 .membase        = IO_ADDRESS(TEGRA_UARTA_BASE),
802                 .mapbase        = TEGRA_UARTA_BASE,
803                 .irq            = INT_UARTA,
804                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
805                 .type           = PORT_TEGRA,
806                 .iotype         = UPIO_MEM,
807                 .regshift       = 2,
808                 .uartclk        = UART_SOURCE_RATE,
809         },
810         {
811                 .flags          = 0,
812         },
813 };
814
815 static struct plat_serial8250_port debug_uartb_platform_data[] = {
816         {
817                 .membase        = IO_ADDRESS(TEGRA_UARTB_BASE),
818                 .mapbase        = TEGRA_UARTB_BASE,
819                 .irq            = INT_UARTB,
820                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
821                 .type           = PORT_TEGRA,
822                 .iotype         = UPIO_MEM,
823                 .regshift       = 2,
824                 .uartclk        = UART_SOURCE_RATE,
825         },
826         {
827                 .flags          = 0,
828         },
829 };
830
831 static struct plat_serial8250_port debug_uartc_platform_data[] = {
832         {
833                 .membase        = IO_ADDRESS(TEGRA_UARTC_BASE),
834                 .mapbase        = TEGRA_UARTC_BASE,
835                 .irq            = INT_UARTC,
836                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
837                 .type           = PORT_TEGRA,
838                 .iotype         = UPIO_MEM,
839                 .regshift       = 2,
840                 .uartclk        = UART_SOURCE_RATE,
841         },
842         {
843                 .flags          = 0,
844         },
845 };
846
847 static struct plat_serial8250_port debug_uartd_platform_data[] = {
848         {
849                 .membase        = IO_ADDRESS(TEGRA_UARTD_BASE),
850                 .mapbase        = TEGRA_UARTD_BASE,
851                 .irq            = INT_UARTD,
852                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
853                 .type           = PORT_TEGRA,
854                 .iotype         = UPIO_MEM,
855                 .regshift       = 2,
856                 .uartclk        = UART_SOURCE_RATE,
857         },
858         {
859                 .flags          = 0,
860         },
861 };
862
863 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
864 static struct plat_serial8250_port debug_uarte_platform_data[] = {
865         {
866                 .membase        = IO_ADDRESS(TEGRA_UARTE_BASE),
867                 .mapbase        = TEGRA_UARTE_BASE,
868                 .irq            = INT_UARTE,
869                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
870                 .type           = PORT_TEGRA,
871                 .iotype         = UPIO_MEM,
872                 .regshift       = 2,
873                 .uartclk        = UART_SOURCE_RATE,
874         },
875         {
876                 .flags          = 0,
877         },
878 };
879 #endif
880
881 struct platform_device debug_uarta_device = {
882         .name = "serial8250",
883         .id = PLAT8250_DEV_PLATFORM,
884         .dev = {
885                 .platform_data = debug_uarta_platform_data,
886         },
887 };
888
889 struct platform_device debug_uartb_device = {
890         .name = "serial8250",
891         .id = PLAT8250_DEV_PLATFORM,
892         .dev = {
893                 .platform_data = debug_uartb_platform_data,
894         },
895 };
896
897 struct platform_device debug_uartc_device = {
898         .name = "serial8250",
899         .id = PLAT8250_DEV_PLATFORM,
900         .dev = {
901                 .platform_data = debug_uartc_platform_data,
902         },
903 };
904
905 struct platform_device debug_uartd_device = {
906         .name = "serial8250",
907         .id = PLAT8250_DEV_PLATFORM,
908         .dev = {
909                 .platform_data = debug_uartd_platform_data,
910         },
911 };
912
913 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
914 struct platform_device debug_uarte_device = {
915         .name = "serial8250",
916         .id = PLAT8250_DEV_PLATFORM,
917         .dev = {
918                 .platform_data = debug_uarte_platform_data,
919         },
920 };
921 #endif
922
923 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
924 static struct resource i2s_resource1[] = {
925         [0] = {
926                 .start  = INT_I2S1,
927                 .end    = INT_I2S1,
928                 .flags  = IORESOURCE_IRQ
929         },
930         [1] = {
931                 .start  = TEGRA_DMA_REQ_SEL_I2S_1,
932                 .end    = TEGRA_DMA_REQ_SEL_I2S_1,
933                 .flags  = IORESOURCE_DMA
934         },
935         [2] = {
936                 .start  = TEGRA_I2S1_BASE,
937                 .end    = TEGRA_I2S1_BASE + TEGRA_I2S1_SIZE - 1,
938                 .flags  = IORESOURCE_MEM
939         }
940 };
941
942 struct platform_device tegra_i2s_device1 = {
943         .name           = "tegra20-i2s",
944         .id             = 0,
945         .resource       = i2s_resource1,
946         .num_resources  = ARRAY_SIZE(i2s_resource1),
947 };
948
949 static struct resource i2s_resource2[] = {
950         [0] = {
951                 .start  = INT_I2S2,
952                 .end    = INT_I2S2,
953                 .flags  = IORESOURCE_IRQ
954         },
955         [1] = {
956                 .start  = TEGRA_DMA_REQ_SEL_I2S2_1,
957                 .end    = TEGRA_DMA_REQ_SEL_I2S2_1,
958                 .flags  = IORESOURCE_DMA
959         },
960         [2] = {
961                 .start  = TEGRA_I2S2_BASE,
962                 .end    = TEGRA_I2S2_BASE + TEGRA_I2S2_SIZE - 1,
963                 .flags  = IORESOURCE_MEM
964         }
965 };
966
967 struct platform_device tegra_i2s_device2 = {
968         .name           = "tegra20-i2s",
969         .id             = 1,
970         .resource       = i2s_resource2,
971         .num_resources  = ARRAY_SIZE(i2s_resource2),
972 };
973 #else
974 static struct resource i2s_resource0[] = {
975         [0] = {
976                 .start  = TEGRA_I2S0_BASE,
977                 .end    = TEGRA_I2S0_BASE + TEGRA_I2S0_SIZE - 1,
978                 .flags  = IORESOURCE_MEM
979         }
980 };
981
982 struct platform_device tegra_i2s_device0 = {
983         .name           = "tegra30-i2s",
984         .id             = 0,
985         .resource       = i2s_resource0,
986         .num_resources  = ARRAY_SIZE(i2s_resource0),
987 };
988
989 static struct resource i2s_resource1[] = {
990         [0] = {
991                 .start  = TEGRA_I2S1_BASE,
992                 .end    = TEGRA_I2S1_BASE + TEGRA_I2S1_SIZE - 1,
993                 .flags  = IORESOURCE_MEM
994         }
995 };
996
997 struct platform_device tegra_i2s_device1 = {
998         .name           = "tegra30-i2s",
999         .id             = 1,
1000         .resource       = i2s_resource1,
1001         .num_resources  = ARRAY_SIZE(i2s_resource1),
1002 };
1003
1004 static struct resource i2s_resource2[] = {
1005         [0] = {
1006                 .start  = TEGRA_I2S2_BASE,
1007                 .end    = TEGRA_I2S2_BASE + TEGRA_I2S2_SIZE - 1,
1008                 .flags  = IORESOURCE_MEM
1009         }
1010 };
1011
1012 struct platform_device tegra_i2s_device2 = {
1013         .name           = "tegra30-i2s",
1014         .id             = 2,
1015         .resource       = i2s_resource2,
1016         .num_resources  = ARRAY_SIZE(i2s_resource2),
1017 };
1018
1019 static struct resource i2s_resource3[] = {
1020         [0] = {
1021                 .start  = TEGRA_I2S3_BASE,
1022                 .end    = TEGRA_I2S3_BASE + TEGRA_I2S3_SIZE - 1,
1023                 .flags  = IORESOURCE_MEM
1024         }
1025 };
1026
1027 struct platform_device tegra_i2s_device3 = {
1028         .name           = "tegra30-i2s",
1029         .id             = 3,
1030         .resource       = i2s_resource3,
1031         .num_resources  = ARRAY_SIZE(i2s_resource3),
1032 };
1033
1034 static struct resource i2s_resource4[] = {
1035         [0] = {
1036                 .start  = TEGRA_I2S4_BASE,
1037                 .end    = TEGRA_I2S4_BASE + TEGRA_I2S4_SIZE - 1,
1038                 .flags  = IORESOURCE_MEM
1039         }
1040 };
1041
1042 struct platform_device tegra_i2s_device4 = {
1043         .name           = "tegra30-i2s",
1044         .id             = 4,
1045         .resource       = i2s_resource4,
1046         .num_resources  = ARRAY_SIZE(i2s_resource4),
1047 };
1048 #endif
1049
1050 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1051 static struct resource spdif_resource[] = {
1052         [0] = {
1053                 .start  = INT_SPDIF,
1054                 .end    = INT_SPDIF,
1055                 .flags  = IORESOURCE_IRQ
1056         },
1057         [1] = {
1058                 .start  = TEGRA_DMA_REQ_SEL_SPD_I,
1059                 .end    = TEGRA_DMA_REQ_SEL_SPD_I,
1060                 .flags  = IORESOURCE_DMA
1061         },
1062         [2] = {
1063                 .start  = TEGRA_SPDIF_BASE,
1064                 .end    = TEGRA_SPDIF_BASE + TEGRA_SPDIF_SIZE - 1,
1065                 .flags  = IORESOURCE_MEM
1066         }
1067 };
1068
1069 struct platform_device tegra_spdif_device = {
1070         .name           = "tegra20-spdif",
1071         .id             = -1,
1072         .resource       = spdif_resource,
1073         .num_resources  = ARRAY_SIZE(spdif_resource),
1074 };
1075 #else
1076 static struct resource spdif_resource[] = {
1077         [0] = {
1078                 .start  = TEGRA_SPDIF_BASE,
1079                 .end    = TEGRA_SPDIF_BASE + TEGRA_SPDIF_SIZE - 1,
1080                 .flags  = IORESOURCE_MEM
1081         }
1082 };
1083
1084 struct platform_device tegra_spdif_device = {
1085         .name           = "tegra30-spdif",
1086         .id             = -1,
1087         .resource       = spdif_resource,
1088         .num_resources  = ARRAY_SIZE(spdif_resource),
1089 };
1090 #endif
1091
1092 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1093 static struct resource ahub_resource[] = {
1094         [0] = {
1095                 .start  = TEGRA_APBIF0_BASE,
1096                 .end    = TEGRA_APBIF3_BASE + TEGRA_APBIF3_SIZE - 1,
1097                 .flags  = IORESOURCE_MEM
1098         },
1099         [1] = {
1100                 .start  = TEGRA_AHUB_BASE,
1101                 .end    = TEGRA_AHUB_BASE + TEGRA_AHUB_SIZE - 1,
1102                 .flags  = IORESOURCE_MEM
1103         }
1104 };
1105
1106 struct platform_device tegra_ahub_device = {
1107         .name   = "tegra30-ahub",
1108         .id     = -1,
1109         .resource       = ahub_resource,
1110         .num_resources  = ARRAY_SIZE(ahub_resource),
1111 };
1112
1113 static struct resource dam_resource0[] = {
1114         [0] = {
1115                 .start = TEGRA_DAM0_BASE,
1116                 .end   = TEGRA_DAM0_BASE + TEGRA_DAM0_SIZE - 1,
1117                 .flags = IORESOURCE_MEM
1118         }
1119 };
1120
1121 struct platform_device tegra_dam_device0 = {
1122         .name = "tegra30-dam",
1123         .id = 0,
1124         .resource      = dam_resource0,
1125         .num_resources = ARRAY_SIZE(dam_resource0),
1126 };
1127
1128 static struct resource dam_resource1[] = {
1129         [0] = {
1130                 .start = TEGRA_DAM1_BASE,
1131                 .end   = TEGRA_DAM1_BASE + TEGRA_DAM1_SIZE - 1,
1132                 .flags = IORESOURCE_MEM
1133         }
1134 };
1135
1136 struct platform_device tegra_dam_device1 = {
1137         .name = "tegra30-dam",
1138         .id = 1,
1139         .resource      = dam_resource1,
1140         .num_resources = ARRAY_SIZE(dam_resource1),
1141 };
1142
1143 static struct resource dam_resource2[] = {
1144         [0] = {
1145                 .start = TEGRA_DAM2_BASE,
1146                 .end   = TEGRA_DAM2_BASE + TEGRA_DAM2_SIZE - 1,
1147                 .flags = IORESOURCE_MEM
1148         }
1149 };
1150
1151 struct platform_device tegra_dam_device2 = {
1152         .name = "tegra30-dam",
1153         .id = 2,
1154         .resource      = dam_resource2,
1155         .num_resources = ARRAY_SIZE(dam_resource2),
1156 };
1157
1158 static u64 tegra_hda_dma_mask = DMA_BIT_MASK(32);
1159 static struct resource hda_platform_resources[] = {
1160         [0] = {
1161                 .start  = TEGRA_HDA_BASE,
1162                 .end    = TEGRA_HDA_BASE + TEGRA_HDA_SIZE - 1,
1163                 .flags  = IORESOURCE_MEM
1164         },
1165         [1] = {
1166                 .start  = INT_HDA,
1167                 .end    = INT_HDA,
1168                 .flags  = IORESOURCE_IRQ
1169         },
1170 };
1171
1172 struct platform_device tegra_hda_device = {
1173         .name           = "tegra30-hda",
1174         .id             = -1,
1175         .dev = {
1176                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1177                 .dma_mask               = &tegra_hda_dma_mask,
1178         },
1179         .resource       = hda_platform_resources,
1180         .num_resources  = ARRAY_SIZE(hda_platform_resources),
1181 };
1182 #endif
1183
1184 struct platform_device spdif_dit_device = {
1185         .name = "spdif-dit",
1186         .id = 0,
1187 };
1188
1189 struct platform_device bluetooth_dit_device = {
1190         .name = "spdif-dit",
1191         .id = 1,
1192 };
1193
1194 struct platform_device baseband_dit_device = {
1195         .name = "spdif-dit",
1196         .id = 2,
1197 };
1198
1199 struct platform_device tegra_pcm_device = {
1200         .name = "tegra-pcm-audio",
1201         .id = -1,
1202 };
1203
1204 static struct resource w1_resources[] = {
1205         [0] = {
1206                 .start = INT_OWR,
1207                 .end   = INT_OWR,
1208                 .flags = IORESOURCE_IRQ
1209         },
1210         [1] = {
1211                 .start = TEGRA_OWR_BASE,
1212                 .end = TEGRA_OWR_BASE + TEGRA_OWR_SIZE - 1,
1213                 .flags = IORESOURCE_MEM
1214         }
1215 };
1216
1217 struct platform_device tegra_w1_device = {
1218         .name          = "tegra_w1",
1219         .id            = -1,
1220         .resource      = w1_resources,
1221         .num_resources = ARRAY_SIZE(w1_resources),
1222 };
1223
1224 static struct resource tegra_udc_resources[] = {
1225         [0] = {
1226                 .start  = TEGRA_USB_BASE,
1227                 .end    = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
1228                 .flags  = IORESOURCE_MEM,
1229         },
1230         [1] = {
1231                 .start  = INT_USB,
1232                 .end    = INT_USB,
1233                 .flags  = IORESOURCE_IRQ,
1234         },
1235 };
1236
1237 static u64 tegra_udc_dmamask = DMA_BIT_MASK(32);
1238
1239 static struct fsl_usb2_platform_data tegra_udc_pdata = {
1240         .operating_mode = FSL_USB2_DR_DEVICE,
1241         .phy_mode       = FSL_USB2_PHY_UTMI,
1242 };
1243
1244 struct platform_device tegra_udc_device = {
1245         .name   = "fsl-tegra-udc",
1246         .id     = -1,
1247         .dev    = {
1248                 .dma_mask       = &tegra_udc_dmamask,
1249                 .coherent_dma_mask = DMA_BIT_MASK(32),
1250                 .platform_data  = &tegra_udc_pdata,
1251         },
1252         .resource = tegra_udc_resources,
1253         .num_resources = ARRAY_SIZE(tegra_udc_resources),
1254 };
1255
1256 static struct resource tegra_otg_resources[] = {
1257         [0] = {
1258                 .start  = TEGRA_USB_BASE,
1259                 .end    = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
1260                 .flags  = IORESOURCE_MEM,
1261         },
1262         [1] = {
1263                 .start  = INT_USB,
1264                 .end    = INT_USB,
1265                 .flags  = IORESOURCE_IRQ,
1266         },
1267 };
1268
1269 struct platform_device tegra_otg_device = {
1270         .name           = "tegra-otg",
1271         .id             = -1,
1272         .resource       = tegra_otg_resources,
1273         .num_resources  = ARRAY_SIZE(tegra_otg_resources),
1274 };
1275
1276 #ifdef CONFIG_SATA_AHCI_TEGRA
1277 static u64 tegra_sata_dma_mask = DMA_BIT_MASK(32);
1278
1279 static struct resource tegra_sata_resources[] = {
1280         [0] = {
1281                 .start = TEGRA_SATA_BAR5_BASE,
1282                 .end = TEGRA_SATA_BAR5_BASE + TEGRA_SATA_BAR5_SIZE - 1,
1283                 .flags = IORESOURCE_MEM,
1284         },
1285         [1] = {
1286                 .start = TEGRA_SATA_CONFIG_BASE,
1287                 .end = TEGRA_SATA_CONFIG_BASE + TEGRA_SATA_CONFIG_SIZE - 1,
1288                 .flags = IORESOURCE_MEM,
1289         },
1290         [2] = {
1291                 .start = INT_SATA_CTL,
1292                 .end = INT_SATA_CTL,
1293                 .flags = IORESOURCE_IRQ,
1294         },
1295 };
1296
1297 struct platform_device tegra_sata_device = {
1298         .name   = "tegra-sata",
1299         .id     = 0,
1300         .dev    = {
1301                 .platform_data = 0,
1302                 .coherent_dma_mask = DMA_BIT_MASK(32),
1303                 .dma_mask = &tegra_sata_dma_mask,
1304         },
1305         .resource = tegra_sata_resources,
1306         .num_resources = ARRAY_SIZE(tegra_sata_resources),
1307 };
1308 #endif
1309
1310 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1311 static struct resource das_resource[] = {
1312         [0] = {
1313                 .start  = TEGRA_APB_MISC_DAS_BASE,
1314                 .end    = TEGRA_APB_MISC_DAS_BASE + TEGRA_APB_MISC_DAS_SIZE - 1,
1315                 .flags  = IORESOURCE_MEM
1316         }
1317 };
1318
1319 struct platform_device tegra_das_device = {
1320         .name           = "tegra20-das",
1321         .id             = -1,
1322         .resource       = das_resource,
1323         .num_resources  = ARRAY_SIZE(das_resource),
1324 };
1325 #endif
1326
1327 #if defined(CONFIG_TEGRA_IOVMM_GART) || defined(CONFIG_TEGRA_IOMMU_GART)
1328 static struct resource tegra_gart_resources[] = {
1329         [0] = {
1330                 .name   = "mc",
1331                 .flags  = IORESOURCE_MEM,
1332                 .start  = TEGRA_MC_BASE,
1333                 .end    = TEGRA_MC_BASE + TEGRA_MC_SIZE - 1,
1334         },
1335         [1] = {
1336                 .name   = "gart",
1337                 .flags  = IORESOURCE_MEM,
1338                 .start  = TEGRA_GART_BASE,
1339                 .end    = TEGRA_GART_BASE + TEGRA_GART_SIZE - 1,
1340         }
1341 };
1342
1343 struct platform_device tegra_gart_device = {
1344         .name           = "tegra_gart",
1345         .id             = -1,
1346         .num_resources  = ARRAY_SIZE(tegra_gart_resources),
1347         .resource       = tegra_gart_resources
1348 };
1349 #endif
1350
1351 #if defined(CONFIG_TEGRA_IOVMM_SMMU) || defined(CONFIG_TEGRA_IOMMU_SMMU)
1352 static struct resource tegra_smmu_resources[] = {
1353         [0] = {
1354                 .name   = "mc",
1355                 .flags  = IORESOURCE_MEM,
1356                 .start  = TEGRA_MC_BASE,
1357                 .end    = TEGRA_MC_BASE + TEGRA_MC_SIZE - 1,
1358         },
1359         [1] = {
1360                 .name   = "ahbarb",
1361                 .flags  = IORESOURCE_MEM,
1362                 .start  = TEGRA_AHB_ARB_BASE,
1363                 .end    = TEGRA_AHB_ARB_BASE + TEGRA_AHB_ARB_SIZE - 1,
1364         }
1365 };
1366
1367 struct platform_device tegra_smmu_device = {
1368         .name           = "tegra_smmu",
1369         .id             = -1,
1370         .num_resources  = ARRAY_SIZE(tegra_smmu_resources),
1371         .resource       = tegra_smmu_resources
1372 };
1373
1374
1375 static struct tegra_smmu_window tegra_smmu[] = {
1376         [0] = {
1377                 .start  = TEGRA_SMMU_BASE,
1378                 .end    = TEGRA_SMMU_BASE + TEGRA_SMMU_SIZE - 1,
1379         },
1380 };
1381
1382 struct tegra_smmu_window *tegra_smmu_window(int wnum)
1383 {
1384         return &tegra_smmu[wnum];
1385 }
1386
1387 int tegra_smmu_window_count(void)
1388 {
1389         return ARRAY_SIZE(tegra_smmu);
1390 }
1391 #endif
1392
1393 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
1394 #define CLK_RESET_RST_SOURCE    0x0
1395 static struct resource tegra_wdt_resources[] = {
1396         [0] = {
1397                 .start  = TEGRA_CLK_RESET_BASE + CLK_RESET_RST_SOURCE,
1398                 .end    = TEGRA_CLK_RESET_BASE + CLK_RESET_RST_SOURCE + 4 - 1,
1399                 .flags  = IORESOURCE_MEM,
1400         },
1401         [1] = {
1402                 .start  = TEGRA_TMR1_BASE,
1403                 .end    = TEGRA_TMR1_BASE + TEGRA_TMR1_SIZE - 1,
1404                 .flags  = IORESOURCE_MEM,
1405         },
1406         [2] = {
1407                 .start  = INT_TMR1,
1408                 .end    = INT_TMR1,
1409                 .flags  = IORESOURCE_IRQ,
1410         },
1411 };
1412 #else
1413 static struct resource tegra_wdt_resources[] = {
1414         [0] = {
1415                 .start  = TEGRA_WDT0_BASE,
1416                 .end    = TEGRA_WDT0_BASE + TEGRA_WDT0_SIZE - 1,
1417                 .flags  = IORESOURCE_MEM,
1418         },
1419         [1] = {
1420                 .start  = TEGRA_TMR10_BASE,
1421                 .end    = TEGRA_TMR10_BASE + TEGRA_TMR10_SIZE - 1,
1422                 .flags  = IORESOURCE_MEM,
1423         },
1424         [2] = {
1425                 .start  = INT_WDT_CPU,
1426                 .end    = INT_WDT_CPU,
1427                 .flags  = IORESOURCE_IRQ,
1428         },
1429 };
1430 #endif
1431
1432 struct platform_device tegra_wdt_device = {
1433         .name           = "tegra_wdt",
1434         .id             = -1,
1435         .num_resources  = ARRAY_SIZE(tegra_wdt_resources),
1436         .resource       = tegra_wdt_resources,
1437 };
1438
1439 static struct resource tegra_pwfm0_resource = {
1440         .start  = TEGRA_PWFM0_BASE,
1441         .end    = TEGRA_PWFM0_BASE + TEGRA_PWFM0_SIZE - 1,
1442         .flags  = IORESOURCE_MEM,
1443 };
1444
1445 static struct resource tegra_pwfm1_resource = {
1446         .start  = TEGRA_PWFM1_BASE,
1447         .end    = TEGRA_PWFM1_BASE + TEGRA_PWFM1_SIZE - 1,
1448         .flags  = IORESOURCE_MEM,
1449 };
1450
1451 static struct resource tegra_pwfm2_resource = {
1452         .start  = TEGRA_PWFM2_BASE,
1453         .end    = TEGRA_PWFM2_BASE + TEGRA_PWFM2_SIZE - 1,
1454         .flags  = IORESOURCE_MEM,
1455 };
1456
1457 static struct resource tegra_pwfm3_resource = {
1458         .start  = TEGRA_PWFM3_BASE,
1459         .end    = TEGRA_PWFM3_BASE + TEGRA_PWFM3_SIZE - 1,
1460         .flags  = IORESOURCE_MEM,
1461 };
1462
1463 struct platform_device tegra_pwfm0_device = {
1464         .name           = "tegra_pwm",
1465         .id             = 0,
1466         .num_resources  = 1,
1467         .resource       = &tegra_pwfm0_resource,
1468 };
1469
1470 struct platform_device tegra_pwfm1_device = {
1471         .name           = "tegra_pwm",
1472         .id             = 1,
1473         .num_resources  = 1,
1474         .resource       = &tegra_pwfm1_resource,
1475 };
1476
1477 struct platform_device tegra_pwfm2_device = {
1478         .name           = "tegra_pwm",
1479         .id             = 2,
1480         .num_resources  = 1,
1481         .resource       = &tegra_pwfm2_resource,
1482 };
1483
1484 struct platform_device tegra_pwfm3_device = {
1485         .name           = "tegra_pwm",
1486         .id             = 3,
1487         .num_resources  = 1,
1488         .resource       = &tegra_pwfm3_resource,
1489 };
1490
1491 static struct resource tegra_grhost_resources[] = {
1492         {
1493                 .start = TEGRA_HOST1X_BASE,
1494                 .end = TEGRA_HOST1X_BASE + TEGRA_HOST1X_SIZE - 1,
1495                 .flags = IORESOURCE_MEM,
1496         },
1497         {
1498                 .start = TEGRA_DISPLAY_BASE,
1499                 .end = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE - 1,
1500                 .flags = IORESOURCE_MEM,
1501         },
1502         {
1503                 .start = TEGRA_DISPLAY2_BASE,
1504                 .end = TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1,
1505                 .flags = IORESOURCE_MEM,
1506         },
1507         {
1508                 .start = TEGRA_VI_BASE,
1509                 .end = TEGRA_VI_BASE + TEGRA_VI_SIZE - 1,
1510                 .flags = IORESOURCE_MEM,
1511         },
1512         {
1513                 .start = TEGRA_ISP_BASE,
1514                 .end = TEGRA_ISP_BASE + TEGRA_ISP_SIZE - 1,
1515                 .flags = IORESOURCE_MEM,
1516         },
1517         {
1518                 .start = TEGRA_MPE_BASE,
1519                 .end = TEGRA_MPE_BASE + TEGRA_MPE_SIZE - 1,
1520                 .flags = IORESOURCE_MEM,
1521         },
1522         {
1523                 .start = INT_SYNCPT_THRESH_BASE,
1524                 .end = INT_SYNCPT_THRESH_BASE + INT_SYNCPT_THRESH_NR - 1,
1525                 .flags = IORESOURCE_IRQ,
1526         },
1527         {
1528                 .start = INT_HOST1X_MPCORE_GENERAL,
1529                 .end = INT_HOST1X_MPCORE_GENERAL,
1530                 .flags = IORESOURCE_IRQ,
1531         },
1532 };
1533
1534 struct platform_device tegra_grhost_device = {
1535         .name = "tegra_grhost",
1536         .id = -1,
1537         .resource = tegra_grhost_resources,
1538         .num_resources = ARRAY_SIZE(tegra_grhost_resources),
1539 };
1540
1541 static struct tegra_avp_platform_data tegra_avp_pdata = {
1542 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1543         .emc_clk_rate = ULONG_MAX,
1544 #else
1545         .emc_clk_rate = 200000000,
1546 #endif
1547 };
1548
1549 struct resource tegra_nvavp_resources[] = {
1550         [0] = {
1551                 .start  = INT_SHR_SEM_INBOX_IBF,
1552                 .end    = INT_SHR_SEM_INBOX_IBF,
1553                 .flags  = IORESOURCE_IRQ,
1554                 .name   = "mbox_from_nvavp_pending",
1555         },
1556 };
1557
1558 struct nvhost_device nvavp_device = {
1559         .name           = "nvavp",
1560         .id             = -1,
1561         .resource       = tegra_nvavp_resources,
1562         .num_resources  = ARRAY_SIZE(tegra_nvavp_resources),
1563 };
1564
1565 static struct resource tegra_avp_resources[] = {
1566         [0] = {
1567                 .start  = INT_SHR_SEM_INBOX_IBF,
1568                 .end    = INT_SHR_SEM_INBOX_IBF,
1569                 .flags  = IORESOURCE_IRQ,
1570                 .name   = "mbox_from_avp_pending",
1571         },
1572 };
1573
1574 struct platform_device tegra_avp_device = {
1575         .name           = "tegra-avp",
1576         .id             = -1,
1577         .num_resources  = ARRAY_SIZE(tegra_avp_resources),
1578         .resource       = tegra_avp_resources,
1579         .dev  = {
1580                 .coherent_dma_mask      = 0xffffffffULL,
1581                 .platform_data          = &tegra_avp_pdata,
1582         },
1583 };
1584
1585 static struct resource tegra_aes_resources[] = {
1586         {
1587                 .start  = TEGRA_VDE_BASE,
1588                 .end    = TEGRA_VDE_BASE + TEGRA_VDE_SIZE - 1,
1589                 .flags  = IORESOURCE_MEM,
1590         },
1591         {
1592                 .start  = TEGRA_BSEA_BASE,
1593                 .end    = TEGRA_BSEA_BASE + TEGRA_BSEA_SIZE - 1,
1594                 .flags  = IORESOURCE_MEM,
1595         },
1596 };
1597
1598 static u64 tegra_aes_dma_mask = DMA_BIT_MASK(32);
1599
1600 struct platform_device tegra_aes_device = {
1601         .name           = "tegra-aes",
1602         .id             = -1,
1603         .resource       = tegra_aes_resources,
1604         .num_resources  = ARRAY_SIZE(tegra_aes_resources),
1605         .dev    = {
1606                 .dma_mask = &tegra_aes_dma_mask,
1607                 .coherent_dma_mask = DMA_BIT_MASK(32),
1608         },
1609 };
1610
1611 static struct resource tegra_kbc_resources[] = {
1612         [0] = {
1613                 .start = TEGRA_KBC_BASE,
1614                 .end   = TEGRA_KBC_BASE + TEGRA_KBC_SIZE - 1,
1615                 .flags = IORESOURCE_MEM,
1616         },
1617         [1] = {
1618                 .start = INT_KBC,
1619                 .end   = INT_KBC,
1620                 .flags = IORESOURCE_IRQ,
1621         },
1622 };
1623
1624 struct platform_device tegra_kbc_device = {
1625         .name = "tegra-kbc",
1626         .id = -1,
1627         .resource = tegra_kbc_resources,
1628         .num_resources = ARRAY_SIZE(tegra_kbc_resources),
1629         .dev = {
1630                 .platform_data = 0,
1631         },
1632 };
1633
1634 #if defined(CONFIG_ARCH_TEGRA_3x_SOC)
1635 static struct resource tegra_tsensor_resources[]= {
1636         {
1637                 .start  = TEGRA_TSENSOR_BASE,
1638                 .end    = TEGRA_TSENSOR_BASE + TEGRA_TSENSOR_SIZE - 1,
1639                 .flags  = IORESOURCE_MEM,
1640         },
1641         {
1642                 .start  = INT_TSENSOR,
1643                 .end    = INT_TSENSOR,
1644                 .flags  = IORESOURCE_IRQ,
1645         },
1646         {
1647                 .start  = TEGRA_PMC_BASE + 0x1B0,
1648                 /* 2 pmc registers mapped */
1649                 .end    = TEGRA_PMC_BASE + 0x1B0 + (2 * 4),
1650                 .flags  = IORESOURCE_MEM,
1651         },
1652 };
1653
1654 struct platform_device tegra_tsensor_device = {
1655         .name   = "tegra-tsensor",
1656         .id     = -1,
1657         .num_resources  = ARRAY_SIZE(tegra_tsensor_resources),
1658         .resource       = tegra_tsensor_resources,
1659         .dev = {
1660                 .platform_data = 0,
1661         },
1662 };
1663 #endif
1664
1665 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1666 static u64 tegra_se_dma_mask = DMA_BIT_MASK(32);
1667
1668 struct resource tegra_se_resources[] = {
1669         [0] = {
1670                 .start = TEGRA_SE_BASE,
1671                 .end = TEGRA_SE_BASE + TEGRA_SE_SIZE - 1,
1672                 .flags = IORESOURCE_MEM,
1673         },
1674         [1] = {
1675                 .start  = TEGRA_PMC_BASE,
1676                 .end    = TEGRA_PMC_BASE + SZ_256 - 1,
1677                 .flags  = IORESOURCE_MEM,
1678         },
1679         [2] = {
1680                 .start = INT_SE,
1681                 .end = INT_SE,
1682                 .flags = IORESOURCE_IRQ,
1683         },
1684 };
1685
1686 struct platform_device tegra_se_device = {
1687         .name = "tegra-se",
1688         .id = -1,
1689         .dev = {
1690                 .coherent_dma_mask = DMA_BIT_MASK(32),
1691                 .dma_mask = &tegra_se_dma_mask,
1692         },
1693         .resource = tegra_se_resources,
1694         .num_resources = ARRAY_SIZE(tegra_se_resources),
1695 };
1696 #endif
1697
1698 static struct resource tegra_disp1_resources[] = {
1699         {
1700                 .name   = "irq",
1701                 .start  = INT_DISPLAY_GENERAL,
1702                 .end    = INT_DISPLAY_GENERAL,
1703                 .flags  = IORESOURCE_IRQ,
1704         },
1705         {
1706                 .name   = "regs",
1707                 .start  = TEGRA_DISPLAY_BASE,
1708                 .end    = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE-1,
1709                 .flags  = IORESOURCE_MEM,
1710         },
1711         {
1712                 .name   = "fbmem",
1713                 .start  = 0,
1714                 .end    = 0,
1715                 .flags  = IORESOURCE_MEM,
1716         },
1717         {
1718                 .name   = "dsi_regs",
1719                 .start  = TEGRA_DSI_BASE,
1720                 .end    = TEGRA_DSI_BASE + TEGRA_DSI_SIZE - 1,
1721                 .flags  = IORESOURCE_MEM,
1722         },
1723 };
1724
1725 struct nvhost_device tegra_disp1_device = {
1726         .name           = "tegradc",
1727         .id             = 0,
1728         .resource       = tegra_disp1_resources,
1729         .num_resources  = ARRAY_SIZE(tegra_disp1_resources),
1730 };
1731
1732 struct platform_device tegra_nvmap_device = {
1733         .name   = "tegra-nvmap",
1734         .id     = -1,
1735 };