rtc: tps80031: register as mfd sub device
[linux-2.6.git] / arch / arm / mach-tegra / cpuidle-t2.c
1 /*
2  * arch/arm/mach-tegra/cpuidle-t2.c
3  *
4  * CPU idle driver for Tegra2 CPUs
5  *
6  * Copyright (c) 2010-2011, NVIDIA Corporation.
7  * Copyright (c) 2011 Google, Inc.
8  * Author: Colin Cross <ccross@android.com>
9  *         Gary King <gking@nvidia.com>
10  *
11  * This program is free software; you can redistribute it and/or modify
12  * it under the terms of the GNU General Public License as published by
13  * the Free Software Foundation; either version 2 of the License, or
14  * (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful, but WITHOUT
17  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19  * more details.
20  *
21  * You should have received a copy of the GNU General Public License along
22  * with this program; if not, write to the Free Software Foundation, Inc.,
23  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
24  */
25
26 #include <linux/kernel.h>
27 #include <linux/cpu.h>
28 #include <linux/cpuidle.h>
29 #include <linux/debugfs.h>
30 #include <linux/delay.h>
31 #include <linux/init.h>
32 #include <linux/interrupt.h>
33 #include <linux/irq.h>
34 #include <linux/io.h>
35 #include <linux/sched.h>
36 #include <linux/seq_file.h>
37 #include <linux/slab.h>
38 #include <linux/smp.h>
39 #include <linux/suspend.h>
40 #include <linux/tick.h>
41
42 #include <asm/cpu_pm.h>
43
44 #include <mach/iomap.h>
45 #include <mach/irqs.h>
46
47 #include "cpuidle.h"
48 #include "gic.h"
49 #include "pm.h"
50 #include "sleep.h"
51 #include "timer.h"
52 #include "dvfs.h"
53
54 static struct {
55         unsigned int cpu_ready_count[2];
56         unsigned long long cpu_wants_lp2_time[2];
57         unsigned long long in_lp2_time;
58         unsigned int both_idle_count;
59         unsigned int tear_down_count;
60         unsigned int lp2_count;
61         unsigned int lp2_completed_count;
62         unsigned int lp2_count_bin[32];
63         unsigned int lp2_completed_count_bin[32];
64         unsigned int lp2_int_count[NR_IRQS];
65         unsigned int last_lp2_int_count[NR_IRQS];
66 } idle_stats;
67
68 static inline unsigned int time_to_bin(unsigned int time)
69 {
70         return fls(time);
71 }
72
73 #ifdef CONFIG_SMP
74
75 #define CLK_RST_CONTROLLER_CLK_CPU_CMPLX        0x4C
76 #define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR    0x344
77
78 static void __iomem *clk_rst = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
79 static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
80 static s64 tegra_cpu1_wake_by_time = LLONG_MAX;
81
82 static int tegra2_reset_sleeping_cpu(int cpu)
83 {
84         int ret = 0;
85
86         BUG_ON(cpu == 0);
87         BUG_ON(cpu == smp_processor_id());
88         tegra_pen_lock();
89
90         if (readl(pmc + PMC_SCRATCH41) == CPU_RESETTABLE)
91                 tegra2_cpu_reset(cpu);
92         else
93                 ret = -EINVAL;
94
95         tegra_pen_unlock();
96
97         return ret;
98 }
99
100 static void tegra2_wake_reset_cpu(int cpu)
101 {
102         u32 reg;
103
104         BUG_ON(cpu == 0);
105         BUG_ON(cpu == smp_processor_id());
106
107         tegra_pen_lock();
108
109         tegra2_cpu_clear_resettable();
110
111         /* enable cpu clock on cpu */
112         reg = readl(clk_rst + 0x4c);
113         writel(reg & ~(1 << (8 + cpu)),
114                clk_rst + CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
115
116         /* take the CPU out of reset */
117         reg = 0x1111 << cpu;
118         writel(reg, clk_rst +
119                CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
120
121         /* unhalt the cpu */
122         flowctrl_writel(0, FLOW_CTRL_HALT_CPU(1));
123
124         tegra_pen_unlock();
125 }
126
127 static int tegra2_reset_other_cpus(int cpu)
128 {
129         int i;
130         int ret = 0;
131
132         BUG_ON(cpu != 0);
133
134         for_each_online_cpu(i) {
135                 if (i != cpu) {
136                         if (tegra2_reset_sleeping_cpu(i)) {
137                                 ret = -EBUSY;
138                                 break;
139                         }
140                 }
141         }
142
143         if (ret) {
144                 for_each_online_cpu(i) {
145                         if (i != cpu)
146                                 tegra2_wake_reset_cpu(i);
147                 }
148                 return ret;
149         }
150
151         return 0;
152 }
153 #else
154 static void tegra2_wake_reset_cpu(int cpu)
155 {
156 }
157
158 static int tegra2_reset_other_cpus(int cpu)
159 {
160         return 0;
161 }
162 #endif
163
164 bool tegra2_lp2_is_allowed(struct cpuidle_device *dev,
165                         struct cpuidle_state *state)
166 {
167         s64 request = ktime_to_us(tick_nohz_get_sleep_length());
168
169         if (request < state->target_residency) {
170                 /* Not enough time left to enter LP2 */
171                 return false;
172         }
173
174         return true;
175 }
176
177 static inline void tegra2_lp3_fall_back(struct cpuidle_device *dev)
178 {
179         /* Not enough time left to enter LP2 */
180         tegra_cpu_wfi();
181
182         /* fall back here from LP2 path - tell cpuidle governor */
183         dev->last_state = &dev->states[0];
184 }
185
186 static int tegra2_idle_lp2_cpu_0(struct cpuidle_device *dev,
187                            struct cpuidle_state *state, s64 request)
188 {
189         ktime_t entry_time;
190         ktime_t exit_time;
191         s64 wake_time;
192         bool sleep_completed = false;
193         int bin;
194         int i;
195
196         while (tegra2_cpu_is_resettable_soon())
197                 cpu_relax();
198
199         if (tegra2_reset_other_cpus(dev->cpu))
200                 return 0;
201
202         idle_stats.both_idle_count++;
203
204         if (request < state->target_residency) {
205                 tegra2_lp3_fall_back(dev);
206                 return -EBUSY;
207         }
208
209         /* LP2 entry time */
210         entry_time = ktime_get();
211
212         /* LP2 initial targeted wake time */
213         wake_time = ktime_to_us(entry_time) + request;
214
215         /* CPU0 must wake up before CPU1. */
216         smp_rmb();
217         wake_time = min_t(s64, wake_time, tegra_cpu1_wake_by_time);
218
219         /* LP2 actual targeted wake time */
220         request = wake_time - ktime_to_us(entry_time);
221         BUG_ON(wake_time < 0LL);
222
223         idle_stats.tear_down_count++;
224         entry_time = ktime_get();
225         tegra_dvfs_rail_off(tegra_cpu_rail, entry_time);
226
227         if (request > state->target_residency) {
228                 s64 sleep_time = request - tegra_lp2_exit_latency;
229
230                 bin = time_to_bin((u32)request / 1000);
231                 idle_stats.lp2_count++;
232                 idle_stats.lp2_count_bin[bin]++;
233
234                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
235
236                 if (tegra_idle_lp2_last(sleep_time, 0) == 0)
237                         sleep_completed = true;
238                 else {
239                         int irq = tegra_gic_pending_interrupt();
240                         idle_stats.lp2_int_count[irq]++;
241                 }
242
243                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
244         }
245
246         for_each_online_cpu(i) {
247                 if (i != dev->cpu)
248                         tegra2_wake_reset_cpu(i);
249         }
250
251         exit_time = ktime_get();
252         tegra_dvfs_rail_on(tegra_cpu_rail, exit_time);
253
254         if (sleep_completed) {
255                 /*
256                  * Stayed in LP2 for the full time until the next tick,
257                  * adjust the exit latency based on measurement
258                  */
259                 s64 actual_time = ktime_to_us(ktime_sub(exit_time, entry_time));
260                 long offset = (long)(actual_time - request);
261                 int latency = tegra_lp2_exit_latency + offset / 16;
262                 latency = clamp(latency, 0, 10000);
263                 tegra_lp2_exit_latency = latency;
264                 smp_wmb();
265
266                 idle_stats.lp2_completed_count++;
267                 idle_stats.lp2_completed_count_bin[bin]++;
268                 idle_stats.in_lp2_time += actual_time;
269
270                 pr_debug("%lld %lld %ld %d\n", request, actual_time,
271                         offset, bin);
272         }
273
274         return 0;
275 }
276
277 static void tegra2_idle_lp2_cpu_1(struct cpuidle_device *dev,
278                            struct cpuidle_state *state, s64 request)
279 {
280 #ifdef CONFIG_SMP
281         struct tegra_twd_context twd_context;
282
283         if (request < tegra_lp2_exit_latency) {
284                 tegra2_cpu_clear_resettable();
285                 tegra2_lp3_fall_back(dev);
286                 return;
287         }
288
289         /* Save time this CPU must be awakened by. */
290         tegra_cpu1_wake_by_time = ktime_to_us(ktime_get()) + request;
291         smp_wmb();
292
293         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
294
295         tegra_twd_suspend(&twd_context);
296
297         tegra2_sleep_wfi(PLAT_PHYS_OFFSET - PAGE_OFFSET);
298
299         tegra2_cpu_clear_resettable();
300
301         tegra_cpu1_wake_by_time = LLONG_MAX;
302
303         tegra_twd_resume(&twd_context);
304
305         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
306 #endif
307 }
308
309 void tegra2_idle_lp2(struct cpuidle_device *dev,
310                         struct cpuidle_state *state)
311 {
312         s64 request = ktime_to_us(tick_nohz_get_sleep_length());
313         bool last_cpu = tegra_set_cpu_in_lp2(dev->cpu);
314
315         cpu_pm_enter();
316
317         if (dev->cpu == 0) {
318                 if (last_cpu) {
319                         if (tegra2_idle_lp2_cpu_0(dev, state, request) < 0) {
320                                 int i;
321                                 for_each_online_cpu(i) {
322                                         if (i != dev->cpu)
323                                                 tegra2_wake_reset_cpu(i);
324                                 }
325                         }
326                 } else {
327                         tegra2_lp3_fall_back(dev);
328                 }
329         } else {
330                 BUG_ON(last_cpu);
331                 tegra2_idle_lp2_cpu_1(dev, state, request);
332         }
333
334         cpu_pm_exit();
335         tegra_clear_cpu_in_lp2(dev->cpu);
336 }
337
338 void tegra2_cpu_idle_stats_lp2_ready(unsigned int cpu)
339 {
340         idle_stats.cpu_ready_count[cpu]++;
341 }
342
343 void tegra2_cpu_idle_stats_lp2_time(unsigned int cpu, s64 us)
344 {
345         idle_stats.cpu_wants_lp2_time[cpu] += us;
346 }
347
348 #ifdef CONFIG_DEBUG_FS
349 int tegra2_lp2_debug_show(struct seq_file *s, void *data)
350 {
351         int bin;
352         int i;
353         seq_printf(s, "                                    cpu0     cpu1\n");
354         seq_printf(s, "-------------------------------------------------\n");
355         seq_printf(s, "cpu ready:                      %8u %8u\n",
356                 idle_stats.cpu_ready_count[0],
357                 idle_stats.cpu_ready_count[1]);
358         seq_printf(s, "both idle:      %8u        %7u%% %7u%%\n",
359                 idle_stats.both_idle_count,
360                 idle_stats.both_idle_count * 100 /
361                         (idle_stats.cpu_ready_count[0] ?: 1),
362                 idle_stats.both_idle_count * 100 /
363                         (idle_stats.cpu_ready_count[1] ?: 1));
364         seq_printf(s, "tear down:      %8u %7u%%\n", idle_stats.tear_down_count,
365                 idle_stats.tear_down_count * 100 /
366                         (idle_stats.both_idle_count ?: 1));
367         seq_printf(s, "lp2:            %8u %7u%%\n", idle_stats.lp2_count,
368                 idle_stats.lp2_count * 100 /
369                         (idle_stats.both_idle_count ?: 1));
370         seq_printf(s, "lp2 completed:  %8u %7u%%\n",
371                 idle_stats.lp2_completed_count,
372                 idle_stats.lp2_completed_count * 100 /
373                         (idle_stats.lp2_count ?: 1));
374
375         seq_printf(s, "\n");
376         seq_printf(s, "cpu ready time:                 %8llu %8llu ms\n",
377                 div64_u64(idle_stats.cpu_wants_lp2_time[0], 1000),
378                 div64_u64(idle_stats.cpu_wants_lp2_time[1], 1000));
379         seq_printf(s, "lp2 time:       %8llu ms     %7d%% %7d%%\n",
380                 div64_u64(idle_stats.in_lp2_time, 1000),
381                 (int)div64_u64(idle_stats.in_lp2_time * 100,
382                         idle_stats.cpu_wants_lp2_time[0] ?: 1),
383                 (int)div64_u64(idle_stats.in_lp2_time * 100,
384                         idle_stats.cpu_wants_lp2_time[1] ?: 1));
385
386         seq_printf(s, "\n");
387         seq_printf(s, "%19s %8s %8s %8s\n", "", "lp2", "comp", "%");
388         seq_printf(s, "-------------------------------------------------\n");
389         for (bin = 0; bin < 32; bin++) {
390                 if (idle_stats.lp2_count_bin[bin] == 0)
391                         continue;
392                 seq_printf(s, "%6u - %6u ms: %8u %8u %7u%%\n",
393                         1 << (bin - 1), 1 << bin,
394                         idle_stats.lp2_count_bin[bin],
395                         idle_stats.lp2_completed_count_bin[bin],
396                         idle_stats.lp2_completed_count_bin[bin] * 100 /
397                                 idle_stats.lp2_count_bin[bin]);
398         }
399
400         seq_printf(s, "\n");
401         seq_printf(s, "%3s %20s %6s %10s\n",
402                 "int", "name", "count", "last count");
403         seq_printf(s, "--------------------------------------------\n");
404         for (i = 0; i < NR_IRQS; i++) {
405                 if (idle_stats.lp2_int_count[i] == 0)
406                         continue;
407                 seq_printf(s, "%3d %20s %6d %10d\n",
408                         i, irq_to_desc(i)->action ?
409                                 irq_to_desc(i)->action->name ?: "???" : "???",
410                         idle_stats.lp2_int_count[i],
411                         idle_stats.lp2_int_count[i] -
412                                 idle_stats.last_lp2_int_count[i]);
413                 idle_stats.last_lp2_int_count[i] = idle_stats.lp2_int_count[i];
414         };
415         return 0;
416 }
417 #endif