Revert "Merge commit 'main-jb-2012.08.03-B4' into t114-0806"
[linux-2.6.git] / arch / arm / mach-tegra / common.c
1 /*
2  * arch/arm/mach-tegra/common.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Copyright (C) 2010-2012 NVIDIA Corporation
6  *
7  * Author:
8  *      Colin Cross <ccross@android.com>
9  *
10  * This software is licensed under the terms of the GNU General Public
11  * License version 2, as published by the Free Software Foundation, and
12  * may be copied, distributed, and modified under those terms.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  */
20
21 #include <linux/platform_device.h>
22 #include <linux/console.h>
23 #include <linux/init.h>
24 #include <linux/io.h>
25 #include <linux/clk.h>
26 #include <linux/delay.h>
27 #include <linux/of_irq.h>
28 #include <linux/highmem.h>
29 #include <linux/memblock.h>
30 #include <linux/bitops.h>
31 #include <linux/sched.h>
32 #include <linux/cpufreq.h>
33
34 #include <asm/soc.h>
35 #include <asm/hardware/cache-l2x0.h>
36 #include <asm/hardware/gic.h>
37 #include <asm/system.h>
38
39 #include <mach/hardware.h>
40 #include <mach/iomap.h>
41 #include <mach/powergate.h>
42 #include <mach/tegra_smmu.h>
43 #include <mach/gpio-tegra.h>
44
45 #include "apbio.h"
46 #include "board.h"
47 #include "clock.h"
48 #include "dvfs.h"
49 #include "fuse.h"
50 #include "pm.h"
51 #include "reset.h"
52 #include "devices.h"
53 #include "pmc.h"
54 #include "common.h"
55
56 #define MC_SECURITY_CFG2        0x7c
57
58 #define AHB_ARBITRATION_PRIORITY_CTRL           0x4
59 #define   AHB_PRIORITY_WEIGHT(x)        (((x) & 0x7) << 29)
60 #define   PRIORITY_SELECT_USB   BIT(6)
61 #define   PRIORITY_SELECT_USB2  BIT(18)
62 #define   PRIORITY_SELECT_USB3  BIT(17)
63
64 #define AHB_GIZMO_AHB_MEM               0xc
65 #define   ENB_FAST_REARBITRATE  BIT(2)
66 #define   DONT_SPLIT_AHB_WR     BIT(7)
67
68 #define   RECOVERY_MODE BIT(31)
69 #define   BOOTLOADER_MODE       BIT(30)
70 #define   FORCED_RECOVERY_MODE  BIT(1)
71
72 #define AHB_GIZMO_USB           0x1c
73 #define AHB_GIZMO_USB2          0x78
74 #define AHB_GIZMO_USB3          0x7c
75 #define   IMMEDIATE     BIT(18)
76
77 #define AHB_MEM_PREFETCH_CFG3   0xe0
78 #define AHB_MEM_PREFETCH_CFG4   0xe4
79 #define AHB_MEM_PREFETCH_CFG1   0xec
80 #define AHB_MEM_PREFETCH_CFG2   0xf0
81 #define   PREFETCH_ENB  BIT(31)
82 #define   MST_ID(x)     (((x) & 0x1f) << 26)
83 #define   AHBDMA_MST_ID MST_ID(5)
84 #define   USB_MST_ID    MST_ID(6)
85 #define   USB2_MST_ID   MST_ID(18)
86 #define   USB3_MST_ID   MST_ID(17)
87 #define   ADDR_BNDRY(x) (((x) & 0xf) << 21)
88 #define   INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0)
89
90 unsigned long tegra_avp_kernel_start;
91 unsigned long tegra_avp_kernel_size;
92 unsigned long tegra_bootloader_fb_start;
93 unsigned long tegra_bootloader_fb_size;
94 unsigned long tegra_fb_start;
95 unsigned long tegra_fb_size;
96 unsigned long tegra_fb2_start;
97 unsigned long tegra_fb2_size;
98 unsigned long tegra_carveout_start;
99 unsigned long tegra_carveout_size;
100 unsigned long tegra_vpr_start;
101 unsigned long tegra_vpr_size;
102 unsigned long tegra_tsec_start;
103 unsigned long tegra_tsec_size;
104 unsigned long tegra_lp0_vec_start;
105 unsigned long tegra_lp0_vec_size;
106 bool tegra_lp0_vec_relocate;
107 unsigned long tegra_grhost_aperture = ~0ul;
108 static   bool is_tegra_debug_uart_hsport;
109 static struct board_info pmu_board_info;
110 static struct board_info display_board_info;
111 static struct board_info camera_board_info;
112
113 static int pmu_core_edp = 1200; /* default 1.2V EDP limit */
114 static int board_panel_type;
115 static enum power_supply_type pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
116
117 /*
118  * Storage for debug-macro.S's state.
119  *
120  * This must be in .data not .bss so that it gets initialized each time the
121  * kernel is loaded. The data is declared here rather than debug-macro.S so
122  * that multiple inclusions of debug-macro.S point at the same data.
123  */
124 #define TEGRA_DEBUG_UART_OFFSET (TEGRA_DEBUG_UART_BASE & 0xFFFF)
125 u32 tegra_uart_config[3] = {
126         /* Debug UART initialization required */
127         1,
128         /* Debug UART physical address */
129         (u32)(IO_APB_PHYS + TEGRA_DEBUG_UART_OFFSET),
130         /* Debug UART virtual address */
131         (u32)(IO_APB_VIRT + TEGRA_DEBUG_UART_OFFSET),
132 };
133
134 #ifdef CONFIG_OF
135 static const struct of_device_id tegra_dt_irq_match[] __initconst = {
136         { .compatible = "arm,cortex-a9-gic", .data = gic_of_init },
137         { }
138 };
139
140 void __init tegra_dt_init_irq(void)
141 {
142         tegra_init_irq();
143         of_irq_init(tegra_dt_irq_match);
144 }
145 #endif
146
147 #define NEVER_RESET 0
148
149 void tegra_assert_system_reset(char mode, const char *cmd)
150 {
151 #if defined(CONFIG_TEGRA_FPGA_PLATFORM) || NEVER_RESET
152         pr_info("tegra_assert_system_reset() ignored.....");
153         do { } while (1);
154 #else
155         void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
156         u32 reg;
157
158         reg = readl_relaxed(reset + PMC_SCRATCH0);
159         /* Writing recovery kernel or Bootloader mode in SCRATCH0 31:30:1 */
160         if (cmd) {
161                 if (!strcmp(cmd, "recovery"))
162                         reg |= RECOVERY_MODE;
163                 else if (!strcmp(cmd, "bootloader"))
164                         reg |= BOOTLOADER_MODE;
165                 else if (!strcmp(cmd, "forced-recovery"))
166                         reg |= FORCED_RECOVERY_MODE;
167                 else
168                         reg &= ~(BOOTLOADER_MODE | RECOVERY_MODE | FORCED_RECOVERY_MODE);
169         }
170         else {
171                 /* Clearing SCRATCH0 31:30:1 on default reboot */
172                 reg &= ~(BOOTLOADER_MODE | RECOVERY_MODE | FORCED_RECOVERY_MODE);
173         }
174         writel_relaxed(reg, reset + PMC_SCRATCH0);
175         reg = readl_relaxed(reset);
176         reg |= 0x10;
177         writel_relaxed(reg, reset);
178 #endif
179 }
180 static int modem_id;
181 static int sku_override;
182 static int debug_uart_port_id;
183 static enum audio_codec_type audio_codec_name;
184 static enum image_type board_image_type = system_image;
185 static int max_cpu_current;
186
187 /* WARNING: There is implicit client of pllp_out3 like i2c, uart, dsi
188  * and so this clock (pllp_out3) should never be disabled.
189  */
190 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
191 static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = {
192         /* name         parent          rate            enabled */
193         { "clk_m",      NULL,           0,              true },
194 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
195         { "pll_p",      NULL,           216000000,      true },
196         { "pll_p_out1", "pll_p",        28800000,       true },
197         { "pll_p_out2", "pll_p",        48000000,       false },
198         { "pll_p_out3", "pll_p",        72000000,       true },
199         { "pll_p_out4", "pll_p",        108000000,      false },
200         { "pll_m",      "clk_m",        0,              true },
201         { "pll_m_out1", "pll_m",        120000000,      true },
202         { "sclk",       "pll_c_out1",   40000000,       true },
203         { "hclk",       "sclk",         40000000,       true },
204         { "pclk",       "hclk",         40000000,       true },
205         { "mpe",        "pll_c",        0,              false },
206         { "epp",        "pll_c",        0,              false },
207         { "vi_sensor",  "pll_c",        0,              false },
208         { "vi",         "pll_c",        0,              false },
209         { "2d",         "pll_c",        0,              false },
210         { "3d",         "pll_c",        0,              false },
211 #else
212         { "pll_p",      NULL,           216000000,      true },
213         { "pll_p_out1", "pll_p",        28800000,       false },
214         { "pll_p_out2", "pll_p",        48000000,       false },
215         { "pll_p_out3", "pll_p",        72000000,       true },
216         { "pll_m_out1", "pll_m",        275000000,      true },
217         { "pll_c",      NULL,           ULONG_MAX,      false },
218         { "pll_c_out1", "pll_c",        208000000,      false },
219         { "pll_p_out4", "pll_p",        108000000,      false },
220         { "sclk",       "pll_p_out4",   108000000,      true },
221         { "hclk",       "sclk",         108000000,      true },
222         { "pclk",       "hclk",         54000000,       true },
223         { "wake.sclk",  NULL,           250000000,      true },
224 #endif
225         { "sbc1.sclk",  NULL,           40000000,       false},
226         { "sbc2.sclk",  NULL,           40000000,       false},
227         { "sbc3.sclk",  NULL,           40000000,       false},
228         { "sbc4.sclk",  NULL,           40000000,       false},
229 #ifdef CONFIG_TEGRA_SLOW_CSITE
230         { "csite",      "clk_m",        1000000,        true },
231 #else
232         { "csite",      NULL,           0,              true },
233 #endif
234         { "emc",        NULL,           0,              true },
235         { "cpu",        NULL,           0,              true },
236         { "kfuse",      NULL,           0,              true },
237         { "fuse",       NULL,           0,              true },
238         { "pll_u",      NULL,           480000000,      false },
239         { "sdmmc1",     "pll_p",        48000000,       false},
240         { "sdmmc3",     "pll_p",        48000000,       false},
241         { "sdmmc4",     "pll_p",        48000000,       false},
242         { "pll_a",      "pll_p_out1",   0,              false},
243         { "pll_a_out0", "pll_a",        0,              false},
244         { NULL,         NULL,           0,              0},
245 };
246 #endif
247 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
248 static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = {
249         /* name         parent          rate            enabled */
250         { "clk_m",      NULL,           0,              true },
251         { "emc",        NULL,           0,              true },
252         { "cpu",        NULL,           0,              true },
253         { "kfuse",      NULL,           0,              true },
254         { "fuse",       NULL,           0,              true },
255 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
256         { "pll_p",      NULL,           0,              true },
257         { "pll_p_out1", "pll_p",        0,              false },
258         { "pll_p_out2", "pll_p",        48000000,       false },
259         { "pll_p_out3", "pll_p",        0,              true },
260         { "pll_m_out1", "pll_m",        275000000,      false },
261         { "pll_p_out4", "pll_p",        102000000,      true },
262         { "sclk",       "pll_p_out4",   102000000,      true },
263         { "hclk",       "sclk",         102000000,      true },
264         { "pclk",       "hclk",         51000000,       true },
265 #else
266         { "pll_p",      NULL,           216000000,      true },
267         { "pll_p_out1", "pll_p",        28800000,       false },
268         { "pll_p_out2", "pll_p",        48000000,       false },
269         { "pll_p_out3", "pll_p",        72000000,       true },
270         { "pll_m_out1", "pll_m",        275000000,      true },
271         { "pll_p_out4", "pll_p",        108000000,      false },
272         { "sclk",       "pll_p_out4",   108000000,      true },
273         { "hclk",       "sclk",         108000000,      true },
274         { "pclk",       "hclk",         54000000,       true },
275 #endif
276 #ifdef CONFIG_TEGRA_SLOW_CSITE
277         { "csite",      "clk_m",        1000000,        true },
278 #else
279         { "csite",      NULL,           0,              true },
280 #endif
281         { "pll_u",      NULL,           480000000,      false },
282         { "sdmmc1",     "pll_p",        48000000,       false},
283         { "sdmmc3",     "pll_p",        48000000,       false},
284         { "sdmmc4",     "pll_p",        48000000,       false},
285         { "sbc1.sclk",  NULL,           40000000,       false},
286         { "sbc2.sclk",  NULL,           40000000,       false},
287         { "sbc3.sclk",  NULL,           40000000,       false},
288         { "sbc4.sclk",  NULL,           40000000,       false},
289         { "sbc5.sclk",  NULL,           40000000,       false},
290         { "sbc6.sclk",  NULL,           40000000,       false},
291         { "wake.sclk",  NULL,           40000000,       true },
292         { "cbus",       "pll_c",        416000000,      false },
293         { "pll_c_out1", "pll_c",        208000000,      false },
294         { "mselect",    "pll_p",        102000000,      true },
295         { NULL,         NULL,           0,              0},
296 };
297 #endif
298 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
299 static __initdata struct tegra_clk_init_table tegra11x_clk_init_table[] = {
300         /* name         parent          rate            enabled */
301         { "clk_m",      NULL,           0,              true },
302         { "emc",        NULL,           0,              true },
303         { "cpu",        NULL,           0,              true },
304         { "kfuse",      NULL,           0,              true },
305         { "fuse",       NULL,           0,              true },
306         { "sclk",       NULL,           0,              true },
307         { "pll_p",      NULL,           0,              true },
308         { "pll_p_out1", "pll_p",        0,              false },
309         { "pll_p_out3", "pll_p",        0,              true },
310 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
311         { "pll_m_out1", "pll_m",        275000000,      false },
312         { "pll_p_out2",  "pll_p",       102000000,      false },
313         { "sclk",        "pll_p_out2",  102000000,      true },
314         { "pll_p_out4",  "pll_p",       204000000,      true },
315         { "hclk",       "sclk",         102000000,      true },
316         { "pclk",       "hclk",         51000000,       true },
317         { "wake.sclk",  NULL,           40000000,       true },
318         { "mselect",    "pll_p",        102000000,      true },
319         { "host1x",     "pll_p",        102000000,      false },
320         { "cl_dvfs_ref", "pll_p",       54000000,       false },
321         { "cl_dvfs_soc", "pll_p",       54000000,       false },
322 #else
323         { "pll_m_out1", "pll_m",        275000000,      true },
324         { "pll_p_out2", "pll_p",        108000000,      false },
325         { "sclk",       "pll_p_out2",   108000000,      true },
326         { "pll_p_out4", "pll_p",        216000000,      true },
327         { "hclk",       "sclk",         108000000,      true },
328         { "pclk",       "hclk",         54000000,       true },
329         { "wake.sclk",  NULL,           250000000,      true },
330         { "mselect",    "pll_p",        108000000,      true },
331         { "host1x",     "pll_p",        108000000,      false },
332         { "cl_dvfs_ref", "clk_m",       13000000,       false },
333         { "cl_dvfs_soc", "clk_m",       13000000,       false },
334 #endif
335 #ifdef CONFIG_TEGRA_SLOW_CSITE
336         { "csite",      "clk_m",        1000000,        true },
337 #else
338         { "csite",      NULL,           0,              true },
339 #endif
340         { "pll_u",      NULL,           480000000,      false },
341         { "sdmmc1",     "pll_p",        48000000,       false},
342         { "sdmmc3",     "pll_p",        48000000,       false},
343         { "sdmmc4",     "pll_p",        48000000,       false},
344         { "sbc1.sclk",  NULL,           40000000,       false},
345         { "sbc2.sclk",  NULL,           40000000,       false},
346         { "sbc3.sclk",  NULL,           40000000,       false},
347         { "sbc4.sclk",  NULL,           40000000,       false},
348         { "sbc5.sclk",  NULL,           40000000,       false},
349         { "sbc6.sclk",  NULL,           40000000,       false},
350 #ifdef CONFIG_TEGRA_DUAL_CBUS
351         { "c2bus",      "pll_c2",       300000000,      false },
352         { "c3bus",      "pll_c3",       300000000,      false },
353 #else
354         { "cbus",       "pll_c",        416000000,      false },
355         { "pll_c_out1", "pll_c",        208000000,      false },
356 #endif
357         { NULL,         NULL,           0,              0},
358 };
359 #endif
360
361 #ifdef CONFIG_CACHE_L2X0
362 #ifdef CONFIG_TRUSTED_FOUNDATIONS
363 static void tegra_cache_smc(bool enable, u32 arg)
364 {
365         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
366         bool need_affinity_switch;
367         bool can_switch_affinity;
368         bool l2x0_enabled;
369         cpumask_t local_cpu_mask;
370         cpumask_t saved_cpu_mask;
371         unsigned long flags;
372         long ret;
373
374         /*
375          * ISSUE : Some registers of PL310 controler must be written
376          *              from Secure context (and from CPU0)!
377          *
378          * When called form Normal we obtain an abort or do nothing.
379          * Instructions that must be called in Secure:
380          *      - Write to Control register (L2X0_CTRL==0x100)
381          *      - Write in Auxiliary controler (L2X0_AUX_CTRL==0x104)
382          *      - Invalidate all entries (L2X0_INV_WAY==0x77C),
383          *              mandatory at boot time.
384          *      - Tag and Data RAM Latency Control Registers
385          *              (0x108 & 0x10C) must be written in Secure.
386          */
387         need_affinity_switch = (smp_processor_id() != 0);
388         can_switch_affinity = !irqs_disabled();
389
390         WARN_ON(need_affinity_switch && !can_switch_affinity);
391         if (need_affinity_switch && can_switch_affinity) {
392                 cpu_set(0, local_cpu_mask);
393                 sched_getaffinity(0, &saved_cpu_mask);
394                 ret = sched_setaffinity(0, &local_cpu_mask);
395                 WARN_ON(ret != 0);
396         }
397
398         local_irq_save(flags);
399         l2x0_enabled = readl_relaxed(p + L2X0_CTRL) & 1;
400         if (enable && !l2x0_enabled)
401                 tegra_generic_smc(0xFFFFF100, 0x00000001, arg);
402         else if (!enable && l2x0_enabled)
403                 tegra_generic_smc(0xFFFFF100, 0x00000002, arg);
404         local_irq_restore(flags);
405
406         if (need_affinity_switch && can_switch_affinity) {
407                 ret = sched_setaffinity(0, &saved_cpu_mask);
408                 WARN_ON(ret != 0);
409         }
410 }
411
412 static void tegra_l2x0_disable(void)
413 {
414         unsigned long flags;
415         static u32 l2x0_way_mask;
416
417         if (!l2x0_way_mask) {
418                 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
419                 u32 aux_ctrl;
420                 u32 ways;
421
422                 aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
423                 ways = (aux_ctrl & (1 << 16)) ? 16 : 8;
424                 l2x0_way_mask = (1 << ways) - 1;
425         }
426
427         local_irq_save(flags);
428         tegra_cache_smc(false, l2x0_way_mask);
429         local_irq_restore(flags);
430 }
431 #endif  /* CONFIG_TRUSTED_FOUNDATIONS  */
432
433 void tegra_init_cache(bool init)
434 {
435         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
436         u32 aux_ctrl;
437 #ifndef CONFIG_TRUSTED_FOUNDATIONS
438         u32 cache_type;
439         u32 tag_latency, data_latency;
440 #endif
441
442 #ifdef CONFIG_TRUSTED_FOUNDATIONS
443         /* issue the SMC to enable the L2 */
444         aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
445         tegra_cache_smc(true, aux_ctrl);
446
447         /* after init, reread aux_ctrl and register handlers */
448         aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
449         l2x0_init(p, aux_ctrl, 0xFFFFFFFF);
450
451         /* override outer_disable() with our disable */
452         outer_cache.disable = tegra_l2x0_disable;
453 #else
454 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
455         tag_latency = 0x331;
456         data_latency = 0x441;
457 #elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
458 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
459         if (is_lp_cluster()) {
460                 tag_latency = 0x221;
461                 data_latency = 0x221;
462         } else {
463                 u32 speedo;
464
465                 /* relax l2-cache latency for speedos 4,5,6 (T33's chips) */
466                 speedo = tegra_cpu_speedo_id();
467                 if (speedo == 4 || speedo == 5 || speedo == 6 ||
468                     speedo == 12 || speedo == 13) {
469                         tag_latency = 0x442;
470                         data_latency = 0x552;
471                 } else {
472                         tag_latency = 0x441;
473                         data_latency = 0x551;
474                 }
475         }
476 #else
477         tag_latency = 0x770;
478         data_latency = 0x770;
479 #endif
480 #endif
481         writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
482         writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL);
483
484 #if defined(CONFIG_ARCH_TEGRA_3x_SOC)
485 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
486         writel(7, p + L2X0_PREFETCH_CTRL);
487         writel(2, p + L2X0_POWER_CTRL);
488 #endif
489 #endif
490
491         writel(0x3, p + L2X0_POWER_CTRL);
492         cache_type = readl(p + L2X0_CACHE_TYPE);
493         aux_ctrl = (cache_type & 0x700) << (17-8);
494         aux_ctrl |= 0x7C400001;
495         if (init) {
496                 l2x0_init(p, aux_ctrl, 0x8200c3fe);
497         } else {
498                 u32 tmp;
499
500                 tmp = aux_ctrl;
501                 aux_ctrl = readl(p + L2X0_AUX_CTRL);
502                 aux_ctrl &= 0x8200c3fe;
503                 aux_ctrl |= tmp;
504                 writel(aux_ctrl, p + L2X0_AUX_CTRL);
505         }
506         l2x0_enable();
507 #endif
508 }
509 #endif
510
511 static void __init tegra_init_power(void)
512 {
513 #ifdef CONFIG_ARCH_TEGRA_HAS_SATA
514         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_SATA);
515 #endif
516 #ifdef CONFIG_ARCH_TEGRA_HAS_PCIE
517         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_PCIE);
518 #endif
519 }
520
521 static inline unsigned long gizmo_readl(unsigned long offset)
522 {
523         return readl(IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
524 }
525
526 static inline void gizmo_writel(unsigned long value, unsigned long offset)
527 {
528         writel(value, IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
529 }
530
531 static void __init tegra_init_ahb_gizmo_settings(void)
532 {
533         unsigned long val;
534
535         val = gizmo_readl(AHB_GIZMO_AHB_MEM);
536         val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR;
537         gizmo_writel(val, AHB_GIZMO_AHB_MEM);
538
539         val = gizmo_readl(AHB_GIZMO_USB);
540         val |= IMMEDIATE;
541         gizmo_writel(val, AHB_GIZMO_USB);
542
543         val = gizmo_readl(AHB_GIZMO_USB2);
544         val |= IMMEDIATE;
545         gizmo_writel(val, AHB_GIZMO_USB2);
546
547         val = gizmo_readl(AHB_GIZMO_USB3);
548         val |= IMMEDIATE;
549         gizmo_writel(val, AHB_GIZMO_USB3);
550
551         val = gizmo_readl(AHB_ARBITRATION_PRIORITY_CTRL);
552         val |= PRIORITY_SELECT_USB | PRIORITY_SELECT_USB2 | PRIORITY_SELECT_USB3
553                                 | AHB_PRIORITY_WEIGHT(7);
554         gizmo_writel(val, AHB_ARBITRATION_PRIORITY_CTRL);
555
556         val = gizmo_readl(AHB_MEM_PREFETCH_CFG1);
557         val &= ~MST_ID(~0);
558         val |= PREFETCH_ENB | AHBDMA_MST_ID |
559                 ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
560         gizmo_writel(val, AHB_MEM_PREFETCH_CFG1);
561
562         val = gizmo_readl(AHB_MEM_PREFETCH_CFG2);
563         val &= ~MST_ID(~0);
564         val |= PREFETCH_ENB | USB_MST_ID | ADDR_BNDRY(0xc) |
565                 INACTIVITY_TIMEOUT(0x1000);
566         gizmo_writel(val, AHB_MEM_PREFETCH_CFG2);
567
568         val = gizmo_readl(AHB_MEM_PREFETCH_CFG3);
569         val &= ~MST_ID(~0);
570         val |= PREFETCH_ENB | USB3_MST_ID | ADDR_BNDRY(0xc) |
571                 INACTIVITY_TIMEOUT(0x1000);
572         gizmo_writel(val, AHB_MEM_PREFETCH_CFG3);
573
574         val = gizmo_readl(AHB_MEM_PREFETCH_CFG4);
575         val &= ~MST_ID(~0);
576         val |= PREFETCH_ENB | USB2_MST_ID | ADDR_BNDRY(0xc) |
577                 INACTIVITY_TIMEOUT(0x1000);
578         gizmo_writel(val, AHB_MEM_PREFETCH_CFG4);
579 }
580
581 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
582 void __init tegra20_init_early(void)
583 {
584 #ifndef CONFIG_SMP
585         /* For SMP system, initializing the reset handler here is too
586            late. For non-SMP systems, the function that calls the reset
587            handler initializer is not called, so do it here for non-SMP. */
588         tegra_cpu_reset_handler_init();
589 #endif
590         tegra_init_fuse();
591         tegra2_init_clocks();
592         tegra2_init_dvfs();
593         tegra_common_init_clock();
594         tegra_clk_init_from_table(tegra20_clk_init_table);
595         tegra_init_cache(true);
596         tegra_pmc_init();
597         tegra_powergate_init();
598         tegra_init_power();
599         tegra_init_ahb_gizmo_settings();
600         tegra_init_debug_uart_rate();
601         tegra_gpio_resume_init();
602 }
603 #endif
604 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
605 void __init tegra30_init_early(void)
606 {
607 #ifndef CONFIG_SMP
608         /* For SMP system, initializing the reset handler here is too
609            late. For non-SMP systems, the function that calls the reset
610            handler initializer is not called, so do it here for non-SMP. */
611         tegra_cpu_reset_handler_init();
612 #endif
613         tegra_init_fuse();
614         tegra30_init_clocks();
615         tegra3_init_dvfs();
616         tegra_common_init_clock();
617         tegra_clk_init_from_table(tegra30_clk_init_table);
618         tegra_init_cache(true);
619         tegra_pmc_init();
620         tegra_powergate_init();
621         tegra_init_power();
622         tegra_init_ahb_gizmo_settings();
623         tegra_init_debug_uart_rate();
624         tegra_gpio_resume_init();
625 }
626 #endif
627 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
628 void __init tegra11x_init_early(void)
629 {
630 #ifndef CONFIG_SMP
631         /* For SMP system, initializing the reset handler here is too
632            late. For non-SMP systems, the function that calls the reset
633            handler initializer is not called, so do it here for non-SMP. */
634         tegra_cpu_reset_handler_init();
635 #endif
636         tegra_init_fuse();
637         tegra11x_init_clocks();
638         tegra11x_init_dvfs();
639         tegra_common_init_clock();
640         tegra_clk_init_from_table(tegra11x_clk_init_table);
641         tegra11x_clk_init_la();
642         tegra_init_cache(true);
643         tegra_pmc_init();
644         tegra_powergate_init();
645         tegra_init_power();
646         tegra_init_ahb_gizmo_settings();
647         tegra_init_debug_uart_rate();
648         tegra_gpio_resume_init();
649 }
650 #endif
651 static int __init tegra_lp0_vec_arg(char *options)
652 {
653         char *p = options;
654
655         tegra_lp0_vec_size = memparse(p, &p);
656         if (*p == '@')
657                 tegra_lp0_vec_start = memparse(p+1, &p);
658         if (!tegra_lp0_vec_size || !tegra_lp0_vec_start) {
659                 tegra_lp0_vec_size = 0;
660                 tegra_lp0_vec_start = 0;
661         }
662
663         return 0;
664 }
665 early_param("lp0_vec", tegra_lp0_vec_arg);
666
667 static int __init tegra_bootloader_fb_arg(char *options)
668 {
669         char *p = options;
670
671         tegra_bootloader_fb_size = memparse(p, &p);
672         if (*p == '@')
673                 tegra_bootloader_fb_start = memparse(p+1, &p);
674
675         pr_info("Found tegra_fbmem: %08lx@%08lx\n",
676                 tegra_bootloader_fb_size, tegra_bootloader_fb_start);
677
678         return 0;
679 }
680 early_param("tegra_fbmem", tegra_bootloader_fb_arg);
681
682 static int __init tegra_sku_override(char *id)
683 {
684         char *p = id;
685
686         sku_override = memparse(p, &p);
687
688         return 0;
689 }
690 early_param("sku_override", tegra_sku_override);
691
692 int tegra_get_sku_override(void)
693 {
694         return sku_override;
695 }
696
697 static int __init tegra_vpr_arg(char *options)
698 {
699         char *p = options;
700
701         tegra_vpr_size = memparse(p, &p);
702         if (*p == '@')
703                 tegra_vpr_start = memparse(p+1, &p);
704         pr_info("Found vpr, start=0x%lx size=%lx",
705                 tegra_vpr_start, tegra_vpr_size);
706         return 0;
707 }
708 early_param("vpr", tegra_vpr_arg);
709
710 static int __init tegra_tsec_arg(char *options)
711 {
712         char *p = options;
713
714         tegra_tsec_size = memparse(p, &p);
715         if (*p == '@')
716                 tegra_tsec_start = memparse(p+1, &p);
717         pr_info("Found tsec, start=0x%lx size=%lx",
718                 tegra_tsec_start, tegra_tsec_size);
719         return 0;
720 }
721 early_param("tsec", tegra_tsec_arg);
722
723 enum panel_type get_panel_type(void)
724 {
725         return board_panel_type;
726 }
727 static int __init tegra_board_panel_type(char *options)
728 {
729         if (!strcmp(options, "lvds"))
730                 board_panel_type = panel_type_lvds;
731         else if (!strcmp(options, "dsi"))
732                 board_panel_type = panel_type_dsi;
733         else
734                 return 0;
735         return 1;
736 }
737 __setup("panel=", tegra_board_panel_type);
738
739 enum power_supply_type get_power_supply_type(void)
740 {
741         return pow_supply_type;
742 }
743 static int __init tegra_board_power_supply_type(char *options)
744 {
745         if (!strcmp(options, "Adapter"))
746                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
747         if (!strcmp(options, "Mains"))
748                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
749         else if (!strcmp(options, "Battery"))
750                 pow_supply_type = POWER_SUPPLY_TYPE_BATTERY;
751         else
752                 return 0;
753         return 1;
754 }
755 __setup("power_supply=", tegra_board_power_supply_type);
756
757 int get_core_edp(void)
758 {
759         return pmu_core_edp;
760 }
761 static int __init tegra_pmu_core_edp(char *options)
762 {
763         char *p = options;
764         int core_edp = memparse(p, &p);
765         if (core_edp != 0)
766                 pmu_core_edp = core_edp;
767         return 0;
768 }
769 early_param("core_edp_mv", tegra_pmu_core_edp);
770
771 int get_maximum_cpu_current_supported(void)
772 {
773         return max_cpu_current;
774 }
775 static int __init tegra_max_cpu_current(char *options)
776 {
777         char *p = options;
778         max_cpu_current = memparse(p, &p);
779         return 1;
780 }
781 __setup("max_cpu_cur_ma=", tegra_max_cpu_current);
782
783 static int __init tegra_debug_uartport(char *info)
784 {
785         char *p = info;
786         unsigned long long port_id;
787         if (!strncmp(p, "hsport", 6))
788                 is_tegra_debug_uart_hsport = true;
789         else if (!strncmp(p, "lsport", 6))
790                 is_tegra_debug_uart_hsport = false;
791
792         if (p[6] == ',') {
793                 if (p[7] == '-') {
794                         debug_uart_port_id = -1;
795                 } else {
796                         port_id = memparse(p + 7, &p);
797                         debug_uart_port_id = (int) port_id;
798                 }
799         } else {
800                 debug_uart_port_id = -1;
801         }
802
803         return 1;
804 }
805
806 bool is_tegra_debug_uartport_hs(void)
807 {
808         return is_tegra_debug_uart_hsport;
809 }
810
811 int get_tegra_uart_debug_port_id(void)
812 {
813         return debug_uart_port_id;
814 }
815 __setup("debug_uartport=", tegra_debug_uartport);
816
817 static int __init tegra_image_type(char *options)
818 {
819         if (!strcmp(options, "RCK"))
820                 board_image_type = rck_image;
821
822         return 0;
823 }
824
825 enum image_type get_tegra_image_type(void)
826 {
827         return board_image_type;
828 }
829
830 __setup("image=", tegra_image_type);
831
832 static int __init tegra_audio_codec_type(char *info)
833 {
834         char *p = info;
835         if (!strncmp(p, "wm8903", 6))
836                 audio_codec_name = audio_codec_wm8903;
837         else
838                 audio_codec_name = audio_codec_none;
839
840         return 1;
841 }
842
843 enum audio_codec_type get_audio_codec_type(void)
844 {
845         return audio_codec_name;
846 }
847 __setup("audio_codec=", tegra_audio_codec_type);
848
849
850 void tegra_get_board_info(struct board_info *bi)
851 {
852         bi->board_id = (system_serial_high >> 16) & 0xFFFF;
853         bi->sku = (system_serial_high) & 0xFFFF;
854         bi->fab = (system_serial_low >> 24) & 0xFF;
855         bi->major_revision = (system_serial_low >> 16) & 0xFF;
856         bi->minor_revision = (system_serial_low >> 8) & 0xFF;
857 }
858
859 static int __init tegra_pmu_board_info(char *info)
860 {
861         char *p = info;
862         pmu_board_info.board_id = memparse(p, &p);
863         pmu_board_info.sku = memparse(p+1, &p);
864         pmu_board_info.fab = memparse(p+1, &p);
865         pmu_board_info.major_revision = memparse(p+1, &p);
866         pmu_board_info.minor_revision = memparse(p+1, &p);
867         return 1;
868 }
869
870 void tegra_get_pmu_board_info(struct board_info *bi)
871 {
872         memcpy(bi, &pmu_board_info, sizeof(struct board_info));
873 }
874
875 __setup("pmuboard=", tegra_pmu_board_info);
876
877 static int __init tegra_display_board_info(char *info)
878 {
879         char *p = info;
880         display_board_info.board_id = memparse(p, &p);
881         display_board_info.sku = memparse(p+1, &p);
882         display_board_info.fab = memparse(p+1, &p);
883         display_board_info.major_revision = memparse(p+1, &p);
884         display_board_info.minor_revision = memparse(p+1, &p);
885         return 1;
886 }
887
888 void tegra_get_display_board_info(struct board_info *bi)
889 {
890         memcpy(bi, &display_board_info, sizeof(struct board_info));
891 }
892
893 __setup("displayboard=", tegra_display_board_info);
894
895 static int __init tegra_camera_board_info(char *info)
896 {
897         char *p = info;
898         camera_board_info.board_id = memparse(p, &p);
899         camera_board_info.sku = memparse(p+1, &p);
900         camera_board_info.fab = memparse(p+1, &p);
901         camera_board_info.major_revision = memparse(p+1, &p);
902         camera_board_info.minor_revision = memparse(p+1, &p);
903         return 1;
904 }
905
906 void tegra_get_camera_board_info(struct board_info *bi)
907 {
908         memcpy(bi, &camera_board_info, sizeof(struct board_info));
909 }
910
911 __setup("cameraboard=", tegra_camera_board_info);
912
913 static int __init tegra_modem_id(char *id)
914 {
915         char *p = id;
916
917         modem_id = memparse(p, &p);
918         return 1;
919 }
920
921 int tegra_get_modem_id(void)
922 {
923         return modem_id;
924 }
925
926 __setup("modem_id=", tegra_modem_id);
927
928 /*
929  * Tegra has a protected aperture that prevents access by most non-CPU
930  * memory masters to addresses above the aperture value.  Enabling it
931  * secures the CPU's memory from the GPU, except through the GART.
932  */
933 void __init tegra_protected_aperture_init(unsigned long aperture)
934 {
935 #ifndef CONFIG_NVMAP_ALLOW_SYSMEM
936         void __iomem *mc_base = IO_ADDRESS(TEGRA_MC_BASE);
937         pr_info("Enabling Tegra protected aperture at 0x%08lx\n", aperture);
938         writel(aperture, mc_base + MC_SECURITY_CFG2);
939 #else
940         pr_err("Tegra protected aperture disabled because nvmap is using "
941                 "system memory\n");
942 #endif
943 }
944
945 /*
946  * Due to conflicting restrictions on the placement of the framebuffer,
947  * the bootloader is likely to leave the framebuffer pointed at a location
948  * in memory that is outside the grhost aperture.  This function will move
949  * the framebuffer contents from a physical address that is anywher (lowmem,
950  * highmem, or outside the memory map) to a physical address that is outside
951  * the memory map.
952  */
953 void tegra_move_framebuffer(unsigned long to, unsigned long from,
954         unsigned long size)
955 {
956         struct page *page;
957         void __iomem *to_io;
958         void *from_virt;
959         unsigned long i;
960
961         BUG_ON(PAGE_ALIGN((unsigned long)to) != (unsigned long)to);
962         BUG_ON(PAGE_ALIGN(from) != from);
963         BUG_ON(PAGE_ALIGN(size) != size);
964
965         to_io = ioremap(to, size);
966         if (!to_io) {
967                 pr_err("%s: Failed to map target framebuffer\n", __func__);
968                 return;
969         }
970
971         if (pfn_valid(page_to_pfn(phys_to_page(from)))) {
972                 for (i = 0 ; i < size; i += PAGE_SIZE) {
973                         page = phys_to_page(from + i);
974                         from_virt = kmap(page);
975                         memcpy(to_io + i, from_virt, PAGE_SIZE);
976                         kunmap(page);
977                 }
978         } else {
979                 void __iomem *from_io = ioremap(from, size);
980                 if (!from_io) {
981                         pr_err("%s: Failed to map source framebuffer\n",
982                                 __func__);
983                         goto out;
984                 }
985
986                 for (i = 0; i < size; i += 4)
987                         writel(readl(from_io + i), to_io + i);
988
989                 iounmap(from_io);
990         }
991 out:
992         iounmap(to_io);
993 }
994
995 void __init tegra_reserve(unsigned long carveout_size, unsigned long fb_size,
996         unsigned long fb2_size)
997 {
998         const size_t avp_kernel_reserve = SZ_32M;
999 #if !defined(CONFIG_TEGRA_AVP_KERNEL_ON_MMU) /* Tegra2 with AVP MMU */ && \
1000         !defined(CONFIG_TEGRA_AVP_KERNEL_ON_SMMU) /* Tegra3 & up with SMMU */
1001         /* Reserve hardcoded AVP kernel load area starting at 0xXe000000*/
1002         tegra_avp_kernel_size = SZ_1M;
1003         tegra_avp_kernel_start = memblock_end_of_DRAM() - avp_kernel_reserve;
1004         if (memblock_remove(tegra_avp_kernel_start, avp_kernel_reserve)) {
1005                 pr_err("Failed to remove AVP kernel load area %08lx@%08lx "
1006                                 "from memory map\n",
1007                         (unsigned long)avp_kernel_reserve,
1008                         tegra_avp_kernel_start);
1009                 tegra_avp_kernel_size = 0;
1010         }
1011 #endif
1012
1013         if (carveout_size) {
1014                 tegra_carveout_start = memblock_end_of_DRAM() - carveout_size;
1015                 if (memblock_remove(tegra_carveout_start, carveout_size)) {
1016                         pr_err("Failed to remove carveout %08lx@%08lx "
1017                                 "from memory map\n",
1018                                 carveout_size, tegra_carveout_start);
1019                         tegra_carveout_start = 0;
1020                         tegra_carveout_size = 0;
1021                 } else
1022                         tegra_carveout_size = carveout_size;
1023         }
1024
1025         if (fb2_size) {
1026                 tegra_fb2_start = memblock_end_of_DRAM() - fb2_size;
1027                 if (memblock_remove(tegra_fb2_start, fb2_size)) {
1028                         pr_err("Failed to remove second framebuffer "
1029                                 "%08lx@%08lx from memory map\n",
1030                                 fb2_size, tegra_fb2_start);
1031                         tegra_fb2_start = 0;
1032                         tegra_fb2_size = 0;
1033                 } else
1034                         tegra_fb2_size = fb2_size;
1035         }
1036
1037         if (fb_size) {
1038                 tegra_fb_start = memblock_end_of_DRAM() - fb_size;
1039                 if (memblock_remove(tegra_fb_start, fb_size)) {
1040                         pr_err("Failed to remove framebuffer %08lx@%08lx "
1041                                 "from memory map\n",
1042                                 fb_size, tegra_fb_start);
1043                         tegra_fb_start = 0;
1044                         tegra_fb_size = 0;
1045                 } else
1046                         tegra_fb_size = fb_size;
1047         }
1048
1049         if (tegra_fb_size)
1050                 tegra_grhost_aperture = tegra_fb_start;
1051
1052         if (tegra_fb2_size && tegra_fb2_start < tegra_grhost_aperture)
1053                 tegra_grhost_aperture = tegra_fb2_start;
1054
1055         if (tegra_carveout_size && tegra_carveout_start < tegra_grhost_aperture)
1056                 tegra_grhost_aperture = tegra_carveout_start;
1057
1058         if (tegra_lp0_vec_size &&
1059            (tegra_lp0_vec_start < memblock_end_of_DRAM())) {
1060                 if (memblock_reserve(tegra_lp0_vec_start, tegra_lp0_vec_size)) {
1061                         pr_err("Failed to reserve lp0_vec %08lx@%08lx\n",
1062                                 tegra_lp0_vec_size, tegra_lp0_vec_start);
1063                         tegra_lp0_vec_start = 0;
1064                         tegra_lp0_vec_size = 0;
1065                 }
1066                 tegra_lp0_vec_relocate = false;
1067         } else
1068                 tegra_lp0_vec_relocate = true;
1069
1070         /*
1071          * We copy the bootloader's framebuffer to the framebuffer allocated
1072          * above, and then free this one.
1073          * */
1074         if (tegra_bootloader_fb_size) {
1075                 tegra_bootloader_fb_size = PAGE_ALIGN(tegra_bootloader_fb_size);
1076                 if (memblock_reserve(tegra_bootloader_fb_start,
1077                                 tegra_bootloader_fb_size)) {
1078                         pr_err("Failed to reserve bootloader frame buffer "
1079                                 "%08lx@%08lx\n", tegra_bootloader_fb_size,
1080                                 tegra_bootloader_fb_start);
1081                         tegra_bootloader_fb_start = 0;
1082                         tegra_bootloader_fb_size = 0;
1083                 }
1084         }
1085
1086         pr_info("Tegra reserved memory:\n"
1087                 "LP0:                    %08lx - %08lx\n"
1088                 "Bootloader framebuffer: %08lx - %08lx\n"
1089                 "Framebuffer:            %08lx - %08lx\n"
1090                 "2nd Framebuffer:        %08lx - %08lx\n"
1091                 "Carveout:               %08lx - %08lx\n"
1092                 "Vpr:                    %08lx - %08lx\n"
1093                 "Tsec:                   %08lx - %08lx\n",
1094                 tegra_lp0_vec_start,
1095                 tegra_lp0_vec_size ?
1096                         tegra_lp0_vec_start + tegra_lp0_vec_size - 1 : 0,
1097                 tegra_bootloader_fb_start,
1098                 tegra_bootloader_fb_size ?
1099                         tegra_bootloader_fb_start + tegra_bootloader_fb_size - 1
1100                         : 0,
1101                 tegra_fb_start,
1102                 tegra_fb_size ?
1103                         tegra_fb_start + tegra_fb_size - 1 : 0,
1104                 tegra_fb2_start,
1105                 tegra_fb2_size ?
1106                         tegra_fb2_start + tegra_fb2_size - 1 : 0,
1107                 tegra_carveout_start,
1108                 tegra_carveout_size ?
1109                         tegra_carveout_start + tegra_carveout_size - 1 : 0,
1110                 tegra_vpr_start,
1111                 tegra_vpr_size ?
1112                         tegra_vpr_start + tegra_vpr_size - 1 : 0,
1113                 tegra_tsec_start,
1114                 tegra_tsec_size ?
1115                         tegra_tsec_start + tegra_tsec_size - 1 : 0);
1116
1117         if (tegra_avp_kernel_size) {
1118                 /* Return excessive memory reserved for AVP kernel */
1119                 if (tegra_avp_kernel_size < avp_kernel_reserve)
1120                         memblock_add(
1121                                 tegra_avp_kernel_start + tegra_avp_kernel_size,
1122                                 avp_kernel_reserve - tegra_avp_kernel_size);
1123                 pr_info(
1124                 "AVP kernel: %08lx - %08lx\n",
1125                         tegra_avp_kernel_start,
1126                         tegra_avp_kernel_start + tegra_avp_kernel_size - 1);
1127         }
1128 }
1129
1130 static struct resource ram_console_resources[] = {
1131         {
1132                 .flags = IORESOURCE_MEM,
1133         },
1134 };
1135
1136 static struct platform_device ram_console_device = {
1137         .name           = "ram_console",
1138         .id             = -1,
1139         .num_resources  = ARRAY_SIZE(ram_console_resources),
1140         .resource       = ram_console_resources,
1141 };
1142
1143 void __init tegra_ram_console_debug_reserve(unsigned long ram_console_size)
1144 {
1145         struct resource *res;
1146         long ret;
1147
1148         res = platform_get_resource(&ram_console_device, IORESOURCE_MEM, 0);
1149         if (!res)
1150                 goto fail;
1151         res->start = memblock_end_of_DRAM() - ram_console_size;
1152         res->end = res->start + ram_console_size - 1;
1153         ret = memblock_remove(res->start, ram_console_size);
1154         if (ret)
1155                 goto fail;
1156
1157         return;
1158
1159 fail:
1160         ram_console_device.resource = NULL;
1161         ram_console_device.num_resources = 0;
1162         pr_err("Failed to reserve memory block for ram console\n");
1163 }
1164
1165 void __init tegra_ram_console_debug_init(void)
1166 {
1167         int err;
1168
1169         err = platform_device_register(&ram_console_device);
1170         if (err)
1171                 pr_err("%s: ram console registration failed (%d)!\n",
1172                         __func__, err);
1173 }
1174
1175 void __init tegra_release_bootloader_fb(void)
1176 {
1177         /* Since bootloader fb is reserved in common.c, it is freed here. */
1178         if (tegra_bootloader_fb_size)
1179                 if (memblock_free(tegra_bootloader_fb_start,
1180                                                 tegra_bootloader_fb_size))
1181                         pr_err("Failed to free bootloader fb.\n");
1182 }
1183
1184 static struct platform_device *pinmux_devices[] = {
1185         &tegra_gpio_device,
1186         &tegra_pinmux_device,
1187 };
1188
1189 void tegra_enable_pinmux(void)
1190 {
1191         platform_add_devices(pinmux_devices, ARRAY_SIZE(pinmux_devices));
1192 }
1193
1194 struct arm_soc_desc tegra_soc_desc __initdata = {
1195         .name           = "NVIDIA Tegra",
1196         soc_smp_init_ops(tegra_soc_smp_init_ops)
1197         soc_smp_ops(tegra_soc_smp_ops)
1198 };