Ventana: KBC: Removing the KBC usage on ventana
[linux-2.6.git] / arch / arm / mach-tegra / common.c
1 /*
2  * arch/arm/mach-tegra/common.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Copyright (C) 2010-2011 NVIDIA Corporation
6  *
7  * Author:
8  *      Colin Cross <ccross@android.com>
9  *
10  * This software is licensed under the terms of the GNU General Public
11  * License version 2, as published by the Free Software Foundation, and
12  * may be copied, distributed, and modified under those terms.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  */
20
21 #include <linux/platform_device.h>
22 #include <linux/console.h>
23 #include <linux/init.h>
24 #include <linux/io.h>
25 #include <linux/clk.h>
26 #include <linux/delay.h>
27 #include <linux/highmem.h>
28 #include <linux/memblock.h>
29 #include <linux/bitops.h>
30
31 #include <asm/hardware/cache-l2x0.h>
32 #include <asm/system.h>
33
34 #include <mach/gpio.h>
35 #include <mach/iomap.h>
36 #include <mach/pinmux.h>
37 #include <mach/powergate.h>
38 #include <mach/system.h>
39
40 #include "apbio.h"
41 #include "board.h"
42 #include "clock.h"
43 #include "fuse.h"
44 #include "pm.h"
45 #include "reset.h"
46 #include "tegra_smmu.h"
47
48 #define MC_SECURITY_CFG2        0x7c
49
50 #define AHB_ARBITRATION_PRIORITY_CTRL           0x4
51 #define   AHB_PRIORITY_WEIGHT(x)        (((x) & 0x7) << 29)
52 #define   PRIORITY_SELECT_USB   BIT(6)
53 #define   PRIORITY_SELECT_USB2  BIT(18)
54 #define   PRIORITY_SELECT_USB3  BIT(17)
55
56 #define AHB_GIZMO_AHB_MEM               0xc
57 #define   ENB_FAST_REARBITRATE  BIT(2)
58 #define   DONT_SPLIT_AHB_WR     BIT(7)
59
60 #define AHB_GIZMO_USB           0x1c
61 #define AHB_GIZMO_USB2          0x78
62 #define AHB_GIZMO_USB3          0x7c
63 #define   IMMEDIATE     BIT(18)
64
65 #define AHB_MEM_PREFETCH_CFG3   0xe0
66 #define AHB_MEM_PREFETCH_CFG4   0xe4
67 #define AHB_MEM_PREFETCH_CFG1   0xec
68 #define AHB_MEM_PREFETCH_CFG2   0xf0
69 #define   PREFETCH_ENB  BIT(31)
70 #define   MST_ID(x)     (((x) & 0x1f) << 26)
71 #define   AHBDMA_MST_ID MST_ID(5)
72 #define   USB_MST_ID    MST_ID(6)
73 #define   USB2_MST_ID   MST_ID(18)
74 #define   USB3_MST_ID   MST_ID(17)
75 #define   ADDR_BNDRY(x) (((x) & 0xf) << 21)
76 #define   INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0)
77
78 unsigned long tegra_bootloader_fb_start;
79 unsigned long tegra_bootloader_fb_size;
80 unsigned long tegra_fb_start;
81 unsigned long tegra_fb_size;
82 unsigned long tegra_fb2_start;
83 unsigned long tegra_fb2_size;
84 unsigned long tegra_carveout_start;
85 unsigned long tegra_carveout_size;
86 unsigned long tegra_lp0_vec_start;
87 unsigned long tegra_lp0_vec_size;
88 bool tegra_lp0_vec_relocate;
89 unsigned long tegra_grhost_aperture = ~0ul;
90 static   bool is_tegra_debug_uart_hsport;
91 static struct board_info pmu_board_info;
92
93 static int pmu_core_edp = 1200; /* default 1.2V EDP limit */
94 static int board_panel_type;
95
96 void (*arch_reset)(char mode, const char *cmd) = tegra_assert_system_reset;
97
98 #define NEVER_RESET 0
99
100 void tegra_assert_system_reset(char mode, const char *cmd)
101 {
102 #if defined(CONFIG_TEGRA_FPGA_PLATFORM) || NEVER_RESET
103         printk("tegra_assert_system_reset() ignored.....");
104         do { } while (1);
105 #else
106         void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0x00);
107         u32 reg;
108
109         /* use *_related to avoid spinlock since caches are off */
110         reg = readl_relaxed(reset);
111         reg |= 0x10;
112         writel_relaxed(reg, reset);
113 #endif
114 }
115 static int modem_id;
116
117 /* WARNING: There is implicit client of pllp_out3 like i2c, uart, dsi
118  * and so this clock (pllp_out3) should never be disabled.
119  */
120 static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
121         /* name         parent          rate            enabled */
122         { "clk_m",      NULL,           0,              true },
123 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
124 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
125         { "pll_p",      NULL,           216000000,      true },
126         { "pll_p_out1", "pll_p",        28800000,       true },
127         { "pll_p_out2", "pll_p",        48000000,       true },
128         { "pll_p_out3", "pll_p",        72000000,       true },
129         { "pll_p_out4", "pll_p",        108000000,      true },
130         { "pll_m",      "clk_m",        600000000,      true },
131         { "pll_m_out1", "pll_m",        120000000,      true },
132         { "sclk",       "pll_m_out1",   40000000,       true },
133         { "hclk",       "sclk",         40000000,       true },
134         { "pclk",       "hclk",         40000000,       true },
135 #else
136         { "pll_p",      NULL,           408000000,      true },
137         { "pll_p_out1", "pll_p",        9600000,        true },
138         { "pll_p_out2", "pll_p",        48000000,       true },
139         { "pll_p_out3", "pll_p",        102000000,      true },
140         { "pll_m_out1", "pll_m",        275000000,      true },
141         { "pll_p_out4", "pll_p",        102000000,      true },
142         { "sclk",       "pll_p_out4",   102000000,      true },
143         { "hclk",       "sclk",         102000000,      true },
144         { "pclk",       "hclk",         51000000,       true },
145 #endif
146 #else
147         { "pll_p",      NULL,           216000000,      true },
148         { "pll_p_out1", "pll_p",        28800000,       true },
149         { "pll_p_out2", "pll_p",        48000000,       true },
150         { "pll_p_out3", "pll_p",        72000000,       true },
151         { "pll_m_out1", "pll_m",        275000000,      true },
152         { "pll_c",      NULL,           ULONG_MAX,      false },
153         { "pll_c_out1", "pll_c",        208000000,      false },
154         { "pll_p_out4", "pll_p",        108000000,      true },
155         { "sclk",       "pll_p_out4",   108000000,      true },
156         { "hclk",       "sclk",         108000000,      true },
157         { "pclk",       "hclk",         54000000,       true },
158 #endif
159         { "csite",      NULL,           0,              true },
160         { "emc",        NULL,           0,              true },
161         { "cpu",        NULL,           0,              true },
162         { "kfuse",      NULL,           0,              true },
163         { "fuse",       NULL,           0,              true },
164         { "pll_u",      NULL,           480000000,      false },
165         { "sdmmc1",     "pll_p",        48000000,       false},
166         { "sdmmc3",     "pll_p",        48000000,       false},
167         { "sdmmc4",     "pll_p",        48000000,       true},
168 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
169         { "cbus",       "pll_c",        416000000,      false },
170         { "pll_c_out1", "pll_c",        208000000,      false },
171 #endif
172         { NULL,         NULL,           0,              0},
173 };
174
175 void tegra_init_cache(void)
176 {
177 #ifdef CONFIG_CACHE_L2X0
178         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
179         u32 aux_ctrl;
180
181 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
182         writel_relaxed(0x331, p + L2X0_TAG_LATENCY_CTRL);
183         writel_relaxed(0x441, p + L2X0_DATA_LATENCY_CTRL);
184
185 #elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
186 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
187         /* PL310 RAM latency is CPU dependent. NOTE: Changes here
188            must also be reflected in __cortex_a9_l2x0_restart */
189
190         if (is_lp_cluster()) {
191                 writel(0x221, p + L2X0_TAG_LATENCY_CTRL);
192                 writel(0x221, p + L2X0_DATA_LATENCY_CTRL);
193         } else {
194                 writel(0x441, p + L2X0_TAG_LATENCY_CTRL);
195                 writel(0x551, p + L2X0_DATA_LATENCY_CTRL);
196         }
197 #else
198         writel(0x770, p + L2X0_TAG_LATENCY_CTRL);
199         writel(0x770, p + L2X0_DATA_LATENCY_CTRL);
200 #endif
201 #endif
202         aux_ctrl = readl(p + L2X0_CACHE_TYPE);
203         aux_ctrl = (aux_ctrl & 0x700) << (17-8);
204         aux_ctrl |= 0x6C000001;
205         l2x0_init(p, aux_ctrl, 0x8200c3fe);
206 #endif
207 }
208
209 static void __init tegra_init_power(void)
210 {
211 #ifdef CONFIG_ARCH_TEGRA_HAS_SATA
212         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_SATA);
213 #endif
214 #ifdef CONFIG_ARCH_TEGRA_HAS_PCIE
215         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_PCIE);
216 #endif
217 }
218
219 static inline unsigned long gizmo_readl(unsigned long offset)
220 {
221         return readl(IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
222 }
223
224 static inline void gizmo_writel(unsigned long value, unsigned long offset)
225 {
226         writel(value, IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
227 }
228
229 static void __init tegra_init_ahb_gizmo_settings(void)
230 {
231         unsigned long val;
232
233         val = gizmo_readl(AHB_GIZMO_AHB_MEM);
234         val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR;
235         gizmo_writel(val, AHB_GIZMO_AHB_MEM);
236
237         val = gizmo_readl(AHB_GIZMO_USB);
238         val |= IMMEDIATE;
239         gizmo_writel(val, AHB_GIZMO_USB);
240
241         val = gizmo_readl(AHB_GIZMO_USB2);
242         val |= IMMEDIATE;
243         gizmo_writel(val, AHB_GIZMO_USB2);
244
245         val = gizmo_readl(AHB_GIZMO_USB3);
246         val |= IMMEDIATE;
247         gizmo_writel(val, AHB_GIZMO_USB3);
248
249         val = gizmo_readl(AHB_ARBITRATION_PRIORITY_CTRL);
250         val |= PRIORITY_SELECT_USB | PRIORITY_SELECT_USB2 | PRIORITY_SELECT_USB3
251                                 | AHB_PRIORITY_WEIGHT(7);
252         gizmo_writel(val, AHB_ARBITRATION_PRIORITY_CTRL);
253
254         val = gizmo_readl(AHB_MEM_PREFETCH_CFG1);
255         val &= ~MST_ID(~0);
256         val |= PREFETCH_ENB | AHBDMA_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
257         gizmo_writel(val, AHB_MEM_PREFETCH_CFG1);
258
259         val = gizmo_readl(AHB_MEM_PREFETCH_CFG2);
260         val &= ~MST_ID(~0);
261         val |= PREFETCH_ENB | USB_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
262         gizmo_writel(val, AHB_MEM_PREFETCH_CFG2);
263
264         val = gizmo_readl(AHB_MEM_PREFETCH_CFG3);
265         val &= ~MST_ID(~0);
266         val |= PREFETCH_ENB | USB3_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
267         gizmo_writel(val, AHB_MEM_PREFETCH_CFG3);
268
269         val = gizmo_readl(AHB_MEM_PREFETCH_CFG4);
270         val &= ~MST_ID(~0);
271         val |= PREFETCH_ENB | USB2_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
272         gizmo_writel(val, AHB_MEM_PREFETCH_CFG4);
273 }
274
275 static bool console_flushed;
276
277 static void tegra_pm_flush_console(void)
278 {
279         if (console_flushed)
280                 return;
281         console_flushed = true;
282
283         pr_emerg("Restarting %s\n", linux_banner);
284         if (console_trylock()) {
285                 console_unlock();
286                 return;
287         }
288
289         mdelay(50);
290
291         local_irq_disable();
292         if (!console_trylock())
293                 pr_emerg("%s: Console was locked! Busting\n", __func__);
294         else
295                 pr_emerg("%s: Console was locked!\n", __func__);
296         console_unlock();
297 }
298
299 static void tegra_pm_restart(char mode, const char *cmd)
300 {
301         tegra_pm_flush_console();
302         arm_machine_restart(mode, cmd);
303 }
304
305 void __init tegra_init_early(void)
306 {
307         arm_pm_restart = tegra_pm_restart;
308 #ifndef CONFIG_SMP
309         /* For SMP system, initializing the reset handler here is too
310            late. For non-SMP systems, the function that calls the reset
311            handler initializer is not called, so do it here for non-SMP. */
312         tegra_cpu_reset_handler_init();
313 #endif
314         tegra_init_fuse();
315         tegra_gpio_resume_init();
316         tegra_init_clock();
317         tegra_init_pinmux();
318         tegra_clk_init_from_table(common_clk_init_table);
319         tegra_init_power();
320         tegra_init_cache();
321         tegra_init_ahb_gizmo_settings();
322 }
323
324 static int __init tegra_lp0_vec_arg(char *options)
325 {
326         char *p = options;
327
328         tegra_lp0_vec_size = memparse(p, &p);
329         if (*p == '@')
330                 tegra_lp0_vec_start = memparse(p+1, &p);
331         if (!tegra_lp0_vec_size || !tegra_lp0_vec_start) {
332                 tegra_lp0_vec_size = 0;
333                 tegra_lp0_vec_start = 0;
334         }
335
336         return 0;
337 }
338 early_param("lp0_vec", tegra_lp0_vec_arg);
339
340 static int __init tegra_bootloader_fb_arg(char *options)
341 {
342         char *p = options;
343
344         tegra_bootloader_fb_size = memparse(p, &p);
345         if (*p == '@')
346                 tegra_bootloader_fb_start = memparse(p+1, &p);
347
348         pr_info("Found tegra_fbmem: %08lx@%08lx\n",
349                 tegra_bootloader_fb_size, tegra_bootloader_fb_start);
350
351         return 0;
352 }
353 early_param("tegra_fbmem", tegra_bootloader_fb_arg);
354
355 enum panel_type get_panel_type(void)
356 {
357         return board_panel_type;
358 }
359 static int __init tegra_board_panel_type(char *options)
360 {
361         if (!strcmp(options, "lvds"))
362                 board_panel_type = panel_type_lvds;
363         else if (!strcmp(options, "dsi"))
364                 board_panel_type = panel_type_dsi;
365         else
366                 return 0;
367         return 1;
368 }
369 __setup("panel=", tegra_board_panel_type);
370
371 int get_core_edp(void)
372 {
373         return pmu_core_edp;
374 }
375 static int __init tegra_pmu_core_edp(char *options)
376 {
377         char *p = options;
378         int core_edp = memparse(p, &p);
379         if (core_edp != 0)
380                 pmu_core_edp = core_edp;
381         return 1;
382 }
383 __setup("core_edp_mv=", tegra_pmu_core_edp);
384
385 static int __init tegra_debug_uartport(char *info)
386 {
387         if (!strcmp(info, "hsport"))
388                 is_tegra_debug_uart_hsport = true;
389         else if (!strcmp(info, "lsport"))
390                 is_tegra_debug_uart_hsport = false;
391
392         return 1;
393 }
394
395 bool is_tegra_debug_uartport_hs(void)
396 {
397         return is_tegra_debug_uart_hsport;
398 }
399
400 __setup("debug_uartport=", tegra_debug_uartport);
401
402 void tegra_get_board_info(struct board_info *bi)
403 {
404         bi->board_id = (system_serial_high >> 16) & 0xFFFF;
405         bi->sku = (system_serial_high) & 0xFFFF;
406         bi->fab = (system_serial_low >> 24) & 0xFF;
407         bi->major_revision = (system_serial_low >> 16) & 0xFF;
408         bi->minor_revision = (system_serial_low >> 8) & 0xFF;
409 }
410
411 static int __init tegra_pmu_board_info(char *info)
412 {
413         char *p = info;
414         pmu_board_info.board_id = memparse(p, &p);
415         pmu_board_info.sku = memparse(p+1, &p);
416         pmu_board_info.fab = memparse(p+1, &p);
417         pmu_board_info.major_revision = memparse(p+1, &p);
418         pmu_board_info.minor_revision = memparse(p+1, &p);
419         return 1;
420 }
421
422 void tegra_get_pmu_board_info(struct board_info *bi)
423 {
424         memcpy(bi, &pmu_board_info, sizeof(struct board_info));
425 }
426
427 __setup("pmuboard=", tegra_pmu_board_info);
428
429 static int __init tegra_modem_id(char *id)
430 {
431         char *p = id;
432
433         modem_id = memparse(p, &p);
434         return 1;
435 }
436
437 int tegra_get_modem_id(void)
438 {
439         return modem_id;
440 }
441
442 __setup("modem_id=", tegra_modem_id);
443
444 /*
445  * Tegra has a protected aperture that prevents access by most non-CPU
446  * memory masters to addresses above the aperture value.  Enabling it
447  * secures the CPU's memory from the GPU, except through the GART.
448  */
449 void __init tegra_protected_aperture_init(unsigned long aperture)
450 {
451 #ifndef CONFIG_NVMAP_ALLOW_SYSMEM
452         void __iomem *mc_base = IO_ADDRESS(TEGRA_MC_BASE);
453         pr_info("Enabling Tegra protected aperture at 0x%08lx\n", aperture);
454         writel(aperture, mc_base + MC_SECURITY_CFG2);
455 #else
456         pr_err("Tegra protected aperture disabled because nvmap is using "
457                 "system memory\n");
458 #endif
459 }
460
461 /*
462  * Due to conflicting restrictions on the placement of the framebuffer,
463  * the bootloader is likely to leave the framebuffer pointed at a location
464  * in memory that is outside the grhost aperture.  This function will move
465  * the framebuffer contents from a physical address that is anywher (lowmem,
466  * highmem, or outside the memory map) to a physical address that is outside
467  * the memory map.
468  */
469 void tegra_move_framebuffer(unsigned long to, unsigned long from,
470         unsigned long size)
471 {
472         struct page *page;
473         void __iomem *to_io;
474         void *from_virt;
475         unsigned long i;
476
477         BUG_ON(PAGE_ALIGN((unsigned long)to) != (unsigned long)to);
478         BUG_ON(PAGE_ALIGN(from) != from);
479         BUG_ON(PAGE_ALIGN(size) != size);
480
481         to_io = ioremap(to, size);
482         if (!to_io) {
483                 pr_err("%s: Failed to map target framebuffer\n", __func__);
484                 return;
485         }
486
487         if (pfn_valid(page_to_pfn(phys_to_page(from)))) {
488                 for (i = 0 ; i < size; i += PAGE_SIZE) {
489                         page = phys_to_page(from + i);
490                         from_virt = kmap(page);
491                         memcpy(to_io + i, from_virt, PAGE_SIZE);
492                         kunmap(page);
493                 }
494         } else {
495                 void __iomem *from_io = ioremap(from, size);
496                 if (!from_io) {
497                         pr_err("%s: Failed to map source framebuffer\n",
498                                 __func__);
499                         goto out;
500                 }
501
502                 for (i = 0; i < size; i += 4)
503                         writel(readl(from_io + i), to_io + i);
504
505                 iounmap(from_io);
506         }
507 out:
508         iounmap(to_io);
509 }
510
511 #ifdef CONFIG_TEGRA_IOVMM_SMMU
512 /* Support for Tegra3 A01 chip mask that needs to have SMMU IOVA reside in
513  * the upper half of 4GB IOVA space. A02 and after use the bottom 1GB and
514  * do not need to reserve memory.
515  */
516 #define SUPPORT_TEGRA_3_IOVMM_SMMU_A01
517 #endif
518
519 void __init tegra_reserve(unsigned long carveout_size, unsigned long fb_size,
520         unsigned long fb2_size)
521 {
522 #ifdef SUPPORT_TEGRA_3_IOVMM_SMMU_A01
523         int smmu_reserved = 0;
524         struct tegra_smmu_window *smmu_window = tegra_smmu_window(0);
525 #endif
526
527         if (carveout_size) {
528                 tegra_carveout_start = memblock_end_of_DRAM() - carveout_size;
529                 if (memblock_remove(tegra_carveout_start, carveout_size)) {
530                         pr_err("Failed to remove carveout %08lx@%08lx "
531                                 "from memory map\n",
532                                 carveout_size, tegra_carveout_start);
533                         tegra_carveout_start = 0;
534                         tegra_carveout_size = 0;
535                 } else
536                         tegra_carveout_size = carveout_size;
537         }
538
539         if (fb2_size) {
540                 tegra_fb2_start = memblock_end_of_DRAM() - fb2_size;
541                 if (memblock_remove(tegra_fb2_start, fb2_size)) {
542                         pr_err("Failed to remove second framebuffer "
543                                 "%08lx@%08lx from memory map\n",
544                                 fb2_size, tegra_fb2_start);
545                         tegra_fb2_start = 0;
546                         tegra_fb2_size = 0;
547                 } else
548                         tegra_fb2_size = fb2_size;
549         }
550
551         if (fb_size) {
552                 tegra_fb_start = memblock_end_of_DRAM() - fb_size;
553                 if (memblock_remove(tegra_fb_start, fb_size)) {
554                         pr_err("Failed to remove framebuffer %08lx@%08lx "
555                                 "from memory map\n",
556                                 fb_size, tegra_fb_start);
557                         tegra_fb_start = 0;
558                         tegra_fb_size = 0;
559                 } else
560                         tegra_fb_size = fb_size;
561         }
562
563         if (tegra_fb_size)
564                 tegra_grhost_aperture = tegra_fb_start;
565
566         if (tegra_fb2_size && tegra_fb2_start < tegra_grhost_aperture)
567                 tegra_grhost_aperture = tegra_fb2_start;
568
569         if (tegra_carveout_size && tegra_carveout_start < tegra_grhost_aperture)
570                 tegra_grhost_aperture = tegra_carveout_start;
571
572 #ifdef SUPPORT_TEGRA_3_IOVMM_SMMU_A01
573         if (!smmu_window) {
574                 pr_err("No SMMU resource\n");
575         } else {
576                 size_t smmu_window_size;
577
578                 if (tegra_get_revision() == TEGRA_REVISION_A01) {
579                         smmu_window->start = TEGRA_SMMU_BASE_A01;
580                         smmu_window->end   = TEGRA_SMMU_BASE_A01 +
581                                                 TEGRA_SMMU_SIZE_A01 - 1;
582                 }
583                 smmu_window_size = smmu_window->end + 1 - smmu_window->start;
584                 if (smmu_window->start >= 0x80000000) {
585                         if (memblock_reserve(smmu_window->start,
586                                                 smmu_window_size))
587                                 pr_err(
588                         "Failed to reserve SMMU I/O VA window %08lx@%08lx\n",
589                                 (unsigned long)smmu_window_size,
590                                 (unsigned long)smmu_window->start);
591                         else
592                                 smmu_reserved = 1;
593                 }
594         }
595 #endif
596
597         if (tegra_lp0_vec_size &&
598            (tegra_lp0_vec_start < memblock_end_of_DRAM())) {
599                 if (memblock_reserve(tegra_lp0_vec_start, tegra_lp0_vec_size)) {
600                         pr_err("Failed to reserve lp0_vec %08lx@%08lx\n",
601                                 tegra_lp0_vec_size, tegra_lp0_vec_start);
602                         tegra_lp0_vec_start = 0;
603                         tegra_lp0_vec_size = 0;
604                 }
605                 tegra_lp0_vec_relocate = false;
606         } else
607                 tegra_lp0_vec_relocate = true;
608
609         /*
610          * We copy the bootloader's framebuffer to the framebuffer allocated
611          * above, and then free this one.
612          * */
613         if (tegra_bootloader_fb_size) {
614                 tegra_bootloader_fb_size = PAGE_ALIGN(tegra_bootloader_fb_size);
615                 if (memblock_reserve(tegra_bootloader_fb_start,
616                                 tegra_bootloader_fb_size)) {
617                         pr_err("Failed to reserve bootloader frame buffer "
618                                 "%08lx@%08lx\n", tegra_bootloader_fb_size,
619                                 tegra_bootloader_fb_start);
620                         tegra_bootloader_fb_start = 0;
621                         tegra_bootloader_fb_size = 0;
622                 }
623         }
624
625         pr_info("Tegra reserved memory:\n"
626                 "LP0:                    %08lx - %08lx\n"
627                 "Bootloader framebuffer: %08lx - %08lx\n"
628                 "Framebuffer:            %08lx - %08lx\n"
629                 "2nd Framebuffer:        %08lx - %08lx\n"
630                 "Carveout:               %08lx - %08lx\n",
631                 tegra_lp0_vec_start,
632                 tegra_lp0_vec_size ?
633                         tegra_lp0_vec_start + tegra_lp0_vec_size - 1 : 0,
634                 tegra_bootloader_fb_start,
635                 tegra_bootloader_fb_size ?
636                         tegra_bootloader_fb_start + tegra_bootloader_fb_size - 1 : 0,
637                 tegra_fb_start,
638                 tegra_fb_size ?
639                         tegra_fb_start + tegra_fb_size - 1 : 0,
640                 tegra_fb2_start,
641                 tegra_fb2_size ?
642                         tegra_fb2_start + tegra_fb2_size - 1 : 0,
643                 tegra_carveout_start,
644                 tegra_carveout_size ?
645                         tegra_carveout_start + tegra_carveout_size - 1 : 0);
646
647 #ifdef SUPPORT_TEGRA_3_IOVMM_SMMU_A01
648         if (smmu_reserved)
649                 pr_info("SMMU:                   %08lx - %08lx\n",
650                         smmu_window->start, smmu_window->end);
651 #endif
652 }
653
654 void __init tegra_release_bootloader_fb(void)
655 {
656         /* Since bootloader fb is reserved in common.c, it is freed here. */
657         if (tegra_bootloader_fb_size)
658                 if (memblock_free(tegra_bootloader_fb_start,
659                                                 tegra_bootloader_fb_size))
660                         pr_err("Failed to free bootloader fb.\n");
661 }
662