video: tegra: dsi: Enable panel read functionality
[linux-2.6.git] / arch / arm / mach-tegra / common.c
1 /*
2  * arch/arm/mach-tegra/common.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Copyright (C) 2010-2013 NVIDIA Corporation. All rights reserved.
6  *
7  * Author:
8  *      Colin Cross <ccross@android.com>
9  *
10  * This software is licensed under the terms of the GNU General Public
11  * License version 2, as published by the Free Software Foundation, and
12  * may be copied, distributed, and modified under those terms.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  */
20
21 #include <linux/platform_device.h>
22 #include <linux/console.h>
23 #include <linux/init.h>
24 #include <linux/io.h>
25 #include <linux/clk.h>
26 #include <linux/delay.h>
27 #include <linux/of_irq.h>
28 #include <linux/highmem.h>
29 #include <linux/memblock.h>
30 #include <linux/bitops.h>
31 #include <linux/sched.h>
32 #include <linux/cpufreq.h>
33 #include <linux/of.h>
34 #include <linux/persistent_ram.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/sys_soc.h>
37 #include <linux/export.h>
38 #include <linux/bootmem.h>
39 #include <trace/events/nvsecurity.h>
40
41 #include <asm/soc.h>
42 #include <asm/hardware/cache-l2x0.h>
43 #include <asm/hardware/gic.h>
44 #include <asm/system.h>
45 #include <asm/dma-mapping.h>
46
47 #include <mach/hardware.h>
48 #include <mach/iomap.h>
49 #include <mach/powergate.h>
50 #include <mach/tegra_smmu.h>
51 #include <mach/gpio-tegra.h>
52 #include <mach/nct.h>
53
54 #include "apbio.h"
55 #include "board.h"
56 #include "clock.h"
57 #include "dvfs.h"
58 #include "fuse.h"
59 #include "pm.h"
60 #include "reset.h"
61 #include "devices.h"
62 #include "pmc.h"
63 #include "common.h"
64 #include "atomics.h"
65
66 #define MC_SECURITY_CFG2        0x7c
67
68 #define AHB_ARBITRATION_PRIORITY_CTRL           0x4
69 #define   AHB_PRIORITY_WEIGHT(x)        (((x) & 0x7) << 29)
70 #define   PRIORITY_SELECT_USB   BIT(6)
71 #define   PRIORITY_SELECT_USB2  BIT(18)
72 #define   PRIORITY_SELECT_USB3  BIT(17)
73 #define   PRIORITY_SELECT_SE BIT(14)
74
75 #define AHB_GIZMO_AHB_MEM               0xc
76 #define   ENB_FAST_REARBITRATE  BIT(2)
77 #define   DONT_SPLIT_AHB_WR     BIT(7)
78 #define   WR_WAIT_COMMIT_ON_1K  BIT(8)
79
80 #define   RECOVERY_MODE BIT(31)
81 #define   BOOTLOADER_MODE       BIT(30)
82 #define   FORCED_RECOVERY_MODE  BIT(1)
83
84 #define AHB_GIZMO_USB           0x1c
85 #define AHB_GIZMO_USB2          0x78
86 #define AHB_GIZMO_USB3          0x7c
87 #define AHB_GIZMO_SE            0x4c
88 #define   IMMEDIATE     BIT(18)
89
90 #define AHB_MEM_PREFETCH_CFG5   0xc4
91 #define AHB_MEM_PREFETCH_CFG3   0xe0
92 #define AHB_MEM_PREFETCH_CFG4   0xe4
93 #define AHB_MEM_PREFETCH_CFG1   0xec
94 #define AHB_MEM_PREFETCH_CFG2   0xf0
95 #define AHB_MEM_PREFETCH_CFG6   0xcc
96 #define   PREFETCH_ENB  BIT(31)
97 #define   MST_ID(x)     (((x) & 0x1f) << 26)
98 #define   AHBDMA_MST_ID MST_ID(5)
99 #define   USB_MST_ID    MST_ID(6)
100 #define SDMMC4_MST_ID   MST_ID(12)
101 #define   USB2_MST_ID   MST_ID(18)
102 #define   USB3_MST_ID   MST_ID(17)
103 #define   SE_MST_ID     MST_ID(14)
104 #define   ADDR_BNDRY(x) (((x) & 0xf) << 21)
105 #define   INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0)
106
107 unsigned long tegra_avp_kernel_start;
108 unsigned long tegra_avp_kernel_size;
109 unsigned long tegra_bootloader_fb_start;
110 unsigned long tegra_bootloader_fb_size;
111 unsigned long tegra_bootloader_fb2_start;
112 unsigned long tegra_bootloader_fb2_size;
113 unsigned long tegra_fb_start;
114 unsigned long tegra_fb_size;
115 unsigned long tegra_fb2_start;
116 unsigned long tegra_fb2_size;
117 unsigned long tegra_carveout_start;
118 unsigned long tegra_carveout_size;
119 unsigned long tegra_vpr_start;
120 unsigned long tegra_vpr_size;
121 unsigned long tegra_tsec_start;
122 unsigned long tegra_tsec_size;
123 unsigned long tegra_lp0_vec_start;
124 unsigned long tegra_lp0_vec_size;
125 #ifdef CONFIG_TEGRA_NVDUMPER
126 unsigned long nvdumper_reserved;
127 #endif
128 bool tegra_lp0_vec_relocate;
129 unsigned long tegra_grhost_aperture = ~0ul;
130 static   bool is_tegra_debug_uart_hsport;
131 static struct board_info pmu_board_info;
132 static struct board_info display_board_info;
133 static int panel_id;
134 static struct board_info camera_board_info;
135 static struct board_info io_board_info;
136 static struct board_info button_board_info;
137 static struct board_info joystick_board_info;
138 static struct board_info rightspeaker_board_info;
139 static struct board_info leftspeaker_board_info;
140 #ifdef CONFIG_TEGRA_USE_NCT
141 unsigned long tegra_nck_start;
142 unsigned long tegra_nck_size;
143 #endif
144
145 static int pmu_core_edp;
146 static int board_panel_type;
147 static enum power_supply_type pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
148 static int pwr_i2c_clk = 400;
149 static u8 power_config;
150
151 atomic_t __maybe_unused sd_brightness = ATOMIC_INIT(255);
152 EXPORT_SYMBOL(sd_brightness);
153
154 /*
155  * Storage for debug-macro.S's state.
156  *
157  * This must be in .data not .bss so that it gets initialized each time the
158  * kernel is loaded. The data is declared here rather than debug-macro.S so
159  * that multiple inclusions of debug-macro.S point at the same data.
160  */
161 #define TEGRA_DEBUG_UART_OFFSET (TEGRA_DEBUG_UART_BASE & 0xFFFF)
162 u32 tegra_uart_config[3] = {
163         /* Debug UART initialization required */
164         1,
165         /* Debug UART physical address */
166         (u32)(IO_APB_PHYS + TEGRA_DEBUG_UART_OFFSET),
167         /* Debug UART virtual address */
168         (u32)(IO_APB_VIRT + TEGRA_DEBUG_UART_OFFSET),
169 };
170
171 #define NEVER_RESET 0
172
173 void tegra_assert_system_reset(char mode, const char *cmd)
174 {
175 #if defined(CONFIG_TEGRA_FPGA_PLATFORM) || NEVER_RESET
176         pr_info("tegra_assert_system_reset() ignored.....");
177         do { } while (1);
178 #else
179         void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
180         u32 reg;
181
182         reg = readl_relaxed(reset + PMC_SCRATCH0);
183         /* Writing recovery kernel or Bootloader mode in SCRATCH0 31:30:1 */
184         if (cmd) {
185                 if (!strcmp(cmd, "recovery"))
186                         reg |= RECOVERY_MODE;
187                 else if (!strcmp(cmd, "bootloader"))
188                         reg |= BOOTLOADER_MODE;
189                 else if (!strcmp(cmd, "forced-recovery"))
190                         reg |= FORCED_RECOVERY_MODE;
191                 else
192                         reg &= ~(BOOTLOADER_MODE | RECOVERY_MODE | FORCED_RECOVERY_MODE);
193         }
194         else {
195                 /* Clearing SCRATCH0 31:30:1 on default reboot */
196                 reg &= ~(BOOTLOADER_MODE | RECOVERY_MODE | FORCED_RECOVERY_MODE);
197         }
198         writel_relaxed(reg, reset + PMC_SCRATCH0);
199         reg = readl_relaxed(reset);
200         reg |= 0x10;
201         writel_relaxed(reg, reset);
202 #endif
203 }
204 static int modem_id;
205 static int commchip_id;
206 static int sku_override;
207 static int debug_uart_port_id;
208 static enum audio_codec_type audio_codec_name;
209 static enum image_type board_image_type = system_image;
210 static int max_cpu_current;
211 static int max_core_current;
212 static int emc_max_dvfs;
213 static unsigned int memory_type;
214 static int usb_port_owner_info;
215 static int pmic_rst_reason;
216
217 /* WARNING: There is implicit client of pllp_out3 like i2c, uart, dsi
218  * and so this clock (pllp_out3) should never be disabled.
219  */
220 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
221 static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = {
222         /* name         parent          rate            enabled */
223         { "clk_m",      NULL,           0,              true },
224 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
225         { "pll_p",      NULL,           216000000,      true },
226         { "pll_p_out1", "pll_p",        28800000,       true },
227         { "pll_p_out2", "pll_p",        48000000,       false },
228         { "pll_p_out3", "pll_p",        72000000,       true },
229         { "pll_p_out4", "pll_p",        108000000,      false },
230         { "pll_m",      "clk_m",        0,              true },
231         { "pll_m_out1", "pll_m",        120000000,      true },
232         { "sclk",       "pll_c_out1",   40000000,       true },
233         { "hclk",       "sclk",         40000000,       true },
234         { "pclk",       "hclk",         40000000,       true },
235         { "mpe",        "pll_c",        0,              false },
236         { "epp",        "pll_c",        0,              false },
237         { "vi_sensor",  "pll_c",        0,              false },
238         { "vi",         "pll_c",        0,              false },
239         { "2d",         "pll_c",        0,              false },
240         { "3d",         "pll_c",        0,              false },
241 #else
242         { "pll_p",      NULL,           216000000,      true },
243         { "pll_p_out1", "pll_p",        28800000,       false },
244         { "pll_p_out2", "pll_p",        48000000,       false },
245         { "pll_p_out3", "pll_p",        72000000,       true },
246         { "pll_m_out1", "pll_m",        275000000,      true },
247         { "pll_c",      NULL,           ULONG_MAX,      false },
248         { "pll_c_out1", "pll_c",        208000000,      false },
249         { "pll_p_out4", "pll_p",        108000000,      false },
250         { "sclk",       "pll_p_out4",   108000000,      true },
251         { "hclk",       "sclk",         108000000,      true },
252         { "pclk",       "hclk",         54000000,       true },
253 #endif
254         { "sbc1.sclk",  NULL,           40000000,       false},
255         { "sbc2.sclk",  NULL,           40000000,       false},
256         { "sbc3.sclk",  NULL,           40000000,       false},
257         { "sbc4.sclk",  NULL,           40000000,       false},
258 #ifdef CONFIG_TEGRA_SLOW_CSITE
259         { "csite",      "clk_m",        1000000,        true },
260 #else
261         { "csite",      NULL,           0,              true },
262 #endif
263         { "emc",        NULL,           0,              true },
264         { "cpu",        NULL,           0,              true },
265         { "kfuse",      NULL,           0,              true },
266         { "fuse",       NULL,           0,              true },
267         { "pll_u",      NULL,           480000000,      false },
268         { "sdmmc1",     "pll_p",        48000000,       false},
269         { "sdmmc3",     "pll_p",        48000000,       false},
270         { "sdmmc4",     "pll_p",        48000000,       false},
271         { "pll_a",      "pll_p_out1",   0,              false},
272         { "pll_a_out0", "pll_a",        0,              false},
273         { NULL,         NULL,           0,              0},
274 };
275 #endif
276 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
277 static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = {
278         /* name         parent          rate            enabled */
279         { "clk_m",      NULL,           0,              true },
280         { "emc",        NULL,           0,              true },
281         { "cpu",        NULL,           0,              true },
282         { "kfuse",      NULL,           0,              true },
283         { "fuse",       NULL,           0,              true },
284 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
285         { "pll_p",      NULL,           0,              true },
286         { "pll_p_out1", "pll_p",        0,              false },
287         { "pll_p_out2", "pll_p",        48000000,       false },
288         { "pll_p_out3", "pll_p",        0,              true },
289         { "pll_m_out1", "pll_m",        275000000,      false },
290         { "pll_p_out4", "pll_p",        102000000,      true },
291         { "sclk",       "pll_p_out4",   102000000,      true },
292         { "hclk",       "sclk",         102000000,      true },
293         { "pclk",       "hclk",         51000000,       true },
294 #else
295         { "pll_p",      NULL,           216000000,      true },
296         { "pll_p_out1", "pll_p",        28800000,       false },
297         { "pll_p_out2", "pll_p",        48000000,       false },
298         { "pll_p_out3", "pll_p",        72000000,       true },
299         { "pll_m_out1", "pll_m",        275000000,      true },
300         { "pll_p_out4", "pll_p",        108000000,      false },
301         { "sclk",       "pll_p_out4",   108000000,      true },
302         { "hclk",       "sclk",         108000000,      true },
303         { "pclk",       "hclk",         54000000,       true },
304 #endif
305 #ifdef CONFIG_TEGRA_SLOW_CSITE
306         { "csite",      "clk_m",        1000000,        true },
307 #else
308         { "csite",      NULL,           0,              true },
309 #endif
310         { "pll_u",      NULL,           480000000,      false },
311         { "sdmmc1",     "pll_p",        48000000,       false},
312         { "sdmmc3",     "pll_p",        48000000,       false},
313         { "sdmmc4",     "pll_p",        48000000,       false},
314         { "sbc1.sclk",  NULL,           40000000,       false},
315         { "sbc2.sclk",  NULL,           40000000,       false},
316         { "sbc3.sclk",  NULL,           40000000,       false},
317         { "sbc4.sclk",  NULL,           40000000,       false},
318         { "sbc5.sclk",  NULL,           40000000,       false},
319         { "sbc6.sclk",  NULL,           40000000,       false},
320 #ifdef CONFIG_TEGRA_PCI
321         { "mselect",    "pll_p",        204000000,      true },
322 #else
323         { "mselect",    "pll_p",        102000000,      true },
324 #endif
325         { NULL,         NULL,           0,              0},
326 };
327 static __initdata struct tegra_clk_init_table tegra30_cbus_init_table[] = {
328         { "cbus",       "pll_c",        416000000,      false },
329         { "pll_c_out1", "pll_c",        208000000,      false },
330         { NULL,         NULL,           0,              0},
331 };
332 #endif
333 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
334 static __initdata struct tegra_clk_init_table tegra11x_clk_init_table[] = {
335         /* name         parent          rate            enabled */
336         { "clk_m",      NULL,           0,              true },
337         { "emc",        NULL,           0,              true },
338         { "cpu",        NULL,           0,              true },
339         { "kfuse",      NULL,           0,              true },
340         { "fuse",       NULL,           0,              true },
341         { "sclk",       NULL,           0,              true },
342         { "pll_p",      NULL,           0,              true },
343         { "pll_p_out1", "pll_p",        0,              false },
344         { "pll_p_out3", "pll_p",        0,              false },
345 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
346         { "pll_m_out1", "pll_m",        275000000,      false },
347         { "pll_p_out2",  "pll_p",       102000000,      false },
348         { "sclk",        "pll_p_out2",  102000000,      true },
349         { "pll_p_out4",  "pll_p",       204000000,      true },
350         { "hclk",       "sclk",         102000000,      true },
351         { "pclk",       "hclk",         51000000,       true },
352         { "mselect",    "pll_p",        102000000,      true },
353         { "host1x",     "pll_p",        102000000,      false },
354         { "cl_dvfs_ref", "pll_p",       51000000,       true },
355         { "cl_dvfs_soc", "pll_p",       51000000,       true },
356         { "dsialp", "pll_p",    70000000,       false },
357         { "dsiblp", "pll_p",    70000000,       false },
358 #else
359         { "pll_m_out1", "pll_m",        275000000,      true },
360         { "pll_p_out2", "pll_p",        108000000,      false },
361         { "sclk",       "pll_p_out2",   108000000,      true },
362         { "pll_p_out4", "pll_p",        216000000,      true },
363         { "hclk",       "sclk",         108000000,      true },
364         { "pclk",       "hclk",         54000000,       true },
365         { "mselect",    "pll_p",        108000000,      true },
366         { "host1x",     "pll_p",        108000000,      false },
367         { "cl_dvfs_ref", "clk_m",       13000000,       false },
368         { "cl_dvfs_soc", "clk_m",       13000000,       false },
369 #endif
370 #ifdef CONFIG_TEGRA_SLOW_CSITE
371         { "csite",      "clk_m",        1000000,        true },
372 #else
373         { "csite",      NULL,           0,              true },
374 #endif
375         { "pll_u",      NULL,           480000000,      true },
376         { "pll_re_vco", NULL,           612000000,      true },
377         { "xusb_falcon_src",    "pll_p",        204000000,      false},
378         { "xusb_host_src",      "pll_p",        102000000,      false},
379         { "xusb_ss_src",        "pll_re_vco",   122400000,      false},
380         { "xusb_hs_src",        "xusb_ss_div2", 61200000,       false},
381         { "xusb_fs_src",        "pll_u_48M",    48000000,       false},
382         { "sdmmc1",     "pll_p",        48000000,       false},
383         { "sdmmc3",     "pll_p",        48000000,       false},
384         { "sdmmc4",     "pll_p",        48000000,       false},
385         { "sbc1.sclk",  NULL,           40000000,       false},
386         { "sbc2.sclk",  NULL,           40000000,       false},
387         { "sbc3.sclk",  NULL,           40000000,       false},
388         { "sbc4.sclk",  NULL,           40000000,       false},
389         { "sbc5.sclk",  NULL,           40000000,       false},
390         { "sbc6.sclk",  NULL,           40000000,       false},
391 #ifdef CONFIG_TEGRA_PLLM_SCALED
392         { "vi",         "pll_p",        0,              false},
393 #endif
394 #ifdef CONFIG_TEGRA_SOCTHERM
395         { "soc_therm",  "pll_p",        51000000,       false },
396         { "tsensor",    "clk_m",        500000,         false },
397 #endif
398 #ifdef CONFIG_TEGRA_ATOMICS
399         { "atomics",    NULL,           0,              true},
400 #endif
401         { NULL,         NULL,           0,              0},
402 };
403 static __initdata struct tegra_clk_init_table tegra11x_cbus_init_table[] = {
404 #ifdef CONFIG_TEGRA_DUAL_CBUS
405         { "c2bus",      "pll_c2",       250000000,      false },
406         { "c3bus",      "pll_c3",       250000000,      false },
407         { "pll_c",      NULL,           624000000,      false },
408 #else
409         { "cbus",       "pll_c",        250000000,      false },
410 #endif
411         { "pll_c_out1", "pll_c",        150000000,      false },
412         { NULL,         NULL,           0,              0},
413 };
414 #endif
415
416 #ifdef CONFIG_CACHE_L2X0
417 #if defined(CONFIG_ARCH_TEGRA_3x_SOC) || defined(CONFIG_ARCH_TEGRA_2x_SOC)
418 #ifdef CONFIG_TRUSTED_FOUNDATIONS
419 static void tegra_cache_smc(bool enable, u32 arg)
420 {
421         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
422         bool need_affinity_switch;
423         bool can_switch_affinity;
424         bool l2x0_enabled;
425         cpumask_t local_cpu_mask;
426         cpumask_t saved_cpu_mask;
427         unsigned long flags;
428         long ret;
429
430         /*
431          * ISSUE : Some registers of PL310 controler must be written
432          *              from Secure context (and from CPU0)!
433          *
434          * When called form Normal we obtain an abort or do nothing.
435          * Instructions that must be called in Secure:
436          *      - Write to Control register (L2X0_CTRL==0x100)
437          *      - Write in Auxiliary controler (L2X0_AUX_CTRL==0x104)
438          *      - Invalidate all entries (L2X0_INV_WAY==0x77C),
439          *              mandatory at boot time.
440          *      - Tag and Data RAM Latency Control Registers
441          *              (0x108 & 0x10C) must be written in Secure.
442          */
443         need_affinity_switch = (smp_processor_id() != 0);
444         can_switch_affinity = !irqs_disabled();
445
446         WARN_ON(need_affinity_switch && !can_switch_affinity);
447         if (need_affinity_switch && can_switch_affinity) {
448                 cpu_set(0, local_cpu_mask);
449                 sched_getaffinity(0, &saved_cpu_mask);
450                 ret = sched_setaffinity(0, &local_cpu_mask);
451                 WARN_ON(ret != 0);
452         }
453
454         local_irq_save(flags);
455         l2x0_enabled = readl_relaxed(p + L2X0_CTRL) & 1;
456         if (enable && !l2x0_enabled)
457                 tegra_generic_smc(0xFFFFF100, 0x00000001, arg);
458         else if (!enable && l2x0_enabled)
459                 tegra_generic_smc(0xFFFFF100, 0x00000002, arg);
460         local_irq_restore(flags);
461
462         if (need_affinity_switch && can_switch_affinity) {
463                 ret = sched_setaffinity(0, &saved_cpu_mask);
464                 WARN_ON(ret != 0);
465         }
466 }
467
468 static void tegra_l2x0_disable(void)
469 {
470         unsigned long flags;
471         static u32 l2x0_way_mask;
472
473         if (!l2x0_way_mask) {
474                 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
475                 u32 aux_ctrl;
476                 u32 ways;
477
478                 aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
479                 ways = (aux_ctrl & (1 << 16)) ? 16 : 8;
480                 l2x0_way_mask = (1 << ways) - 1;
481         }
482
483         local_irq_save(flags);
484         tegra_cache_smc(false, l2x0_way_mask);
485         local_irq_restore(flags);
486 }
487 #endif  /* CONFIG_TRUSTED_FOUNDATIONS  */
488
489 void tegra_init_cache(bool init)
490 {
491         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
492         u32 aux_ctrl;
493 #ifndef CONFIG_TRUSTED_FOUNDATIONS
494         u32 cache_type;
495         u32 tag_latency, data_latency;
496 #endif
497
498 #ifdef CONFIG_TRUSTED_FOUNDATIONS
499         /* issue the SMC to enable the L2 */
500         aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
501         trace_smc_init_cache(NVSEC_SMC_START);
502         tegra_cache_smc(true, aux_ctrl);
503         trace_smc_init_cache(NVSEC_SMC_DONE);
504
505         /* after init, reread aux_ctrl and register handlers */
506         aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
507         l2x0_init(p, aux_ctrl, 0xFFFFFFFF);
508
509         /* override outer_disable() with our disable */
510         outer_cache.disable = tegra_l2x0_disable;
511 #else
512 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
513         tag_latency = 0x331;
514         data_latency = 0x441;
515 #elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
516 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
517         if (is_lp_cluster()) {
518                 tag_latency = 0x221;
519                 data_latency = 0x221;
520         } else {
521                 u32 speedo;
522
523                 /* relax l2-cache latency for speedos 4,5,6 (T33's chips) */
524                 speedo = tegra_cpu_speedo_id();
525                 if (speedo == 4 || speedo == 5 || speedo == 6 ||
526                     speedo == 12 || speedo == 13) {
527                         tag_latency = 0x442;
528                         data_latency = 0x552;
529                 } else {
530                         tag_latency = 0x441;
531                         data_latency = 0x551;
532                 }
533         }
534 #else
535         tag_latency = 0x770;
536         data_latency = 0x770;
537 #endif
538 #endif
539         writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
540         writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL);
541
542 #if defined(CONFIG_ARCH_TEGRA_3x_SOC)
543 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
544         writel(7, p + L2X0_PREFETCH_CTRL);
545         writel(2, p + L2X0_POWER_CTRL);
546 #endif
547 #endif
548
549         writel(0x3, p + L2X0_POWER_CTRL);
550         cache_type = readl(p + L2X0_CACHE_TYPE);
551         aux_ctrl = (cache_type & 0x700) << (17-8);
552         aux_ctrl |= 0x7C400001;
553         if (init) {
554                 l2x0_init(p, aux_ctrl, 0x8200c3fe);
555         } else {
556                 u32 tmp;
557
558                 tmp = aux_ctrl;
559                 aux_ctrl = readl(p + L2X0_AUX_CTRL);
560                 aux_ctrl &= 0x8200c3fe;
561                 aux_ctrl |= tmp;
562                 writel(aux_ctrl, p + L2X0_AUX_CTRL);
563         }
564         l2x0_enable();
565 #endif
566 }
567 #else
568 void tegra_init_cache(bool init)
569 {
570 }
571 #endif
572 #endif
573
574 static void __init tegra_perf_init(void)
575 {
576         u32 reg;
577
578         asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(reg));
579         reg >>= 11;
580         reg = (1 << (reg & 0x1f))-1;
581         reg |= 0x80000000;
582         asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r"(reg));
583         reg = 1;
584         asm volatile("mcr p15, 0, %0, c9, c14, 0" : : "r"(reg));
585 }
586
587 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
588 static void __init tegra_ramrepair_init(void)
589 {
590         if (tegra_spare_fuse(10)  | tegra_spare_fuse(11)) {
591                 u32 reg;
592                 reg = readl(FLOW_CTRL_RAM_REPAIR);
593                 reg &= ~FLOW_CTRL_RAM_REPAIR_BYPASS_EN;
594                 writel(reg, FLOW_CTRL_RAM_REPAIR);
595         }
596 }
597 #endif
598
599 static void __init tegra_init_power(void)
600 {
601 #ifdef CONFIG_ARCH_TEGRA_HAS_SATA
602         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_SATA);
603 #endif
604 #ifdef CONFIG_ARCH_TEGRA_HAS_PCIE
605         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_PCIE);
606 #endif
607 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
608         /* some partitions need to be powergated by default for t11x */
609         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBA);
610         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBB);
611         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBC);
612 #endif
613 }
614
615 static inline unsigned long gizmo_readl(unsigned long offset)
616 {
617         return readl(IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
618 }
619
620 static inline void gizmo_writel(unsigned long value, unsigned long offset)
621 {
622         writel(value, IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
623 }
624
625 static void __init tegra_init_ahb_gizmo_settings(void)
626 {
627         unsigned long val;
628
629         val = gizmo_readl(AHB_GIZMO_AHB_MEM);
630         val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR;
631
632         if (tegra_get_chipid() == TEGRA_CHIPID_TEGRA11 &&
633                 tegra_revision == TEGRA_REVISION_A02)
634                 val |= WR_WAIT_COMMIT_ON_1K;
635         gizmo_writel(val, AHB_GIZMO_AHB_MEM);
636
637         val = gizmo_readl(AHB_GIZMO_USB);
638         val |= IMMEDIATE;
639         gizmo_writel(val, AHB_GIZMO_USB);
640
641         val = gizmo_readl(AHB_GIZMO_USB2);
642         val |= IMMEDIATE;
643         gizmo_writel(val, AHB_GIZMO_USB2);
644
645         val = gizmo_readl(AHB_GIZMO_USB3);
646         val |= IMMEDIATE;
647         gizmo_writel(val, AHB_GIZMO_USB3);
648
649 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
650         val = gizmo_readl(AHB_GIZMO_SE);
651         val |= IMMEDIATE;
652         gizmo_writel(val, AHB_GIZMO_SE);
653 #endif
654
655         val = gizmo_readl(AHB_ARBITRATION_PRIORITY_CTRL);
656         val |= PRIORITY_SELECT_USB | PRIORITY_SELECT_USB2 | PRIORITY_SELECT_USB3
657                                 | AHB_PRIORITY_WEIGHT(7);
658 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
659         val |= PRIORITY_SELECT_SE;
660 #endif
661         gizmo_writel(val, AHB_ARBITRATION_PRIORITY_CTRL);
662
663         val = gizmo_readl(AHB_MEM_PREFETCH_CFG1);
664         val &= ~MST_ID(~0);
665         val |= PREFETCH_ENB | AHBDMA_MST_ID |
666                 ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
667         gizmo_writel(val, AHB_MEM_PREFETCH_CFG1);
668
669         val = gizmo_readl(AHB_MEM_PREFETCH_CFG2);
670         val &= ~MST_ID(~0);
671         val |= PREFETCH_ENB | USB_MST_ID | ADDR_BNDRY(0xc) |
672                 INACTIVITY_TIMEOUT(0x1000);
673         gizmo_writel(val, AHB_MEM_PREFETCH_CFG2);
674
675         val = gizmo_readl(AHB_MEM_PREFETCH_CFG3);
676         val &= ~MST_ID(~0);
677         val |= PREFETCH_ENB | USB3_MST_ID | ADDR_BNDRY(0xc) |
678                 INACTIVITY_TIMEOUT(0x1000);
679         gizmo_writel(val, AHB_MEM_PREFETCH_CFG3);
680
681         val = gizmo_readl(AHB_MEM_PREFETCH_CFG4);
682         val &= ~MST_ID(~0);
683         val |= PREFETCH_ENB | USB2_MST_ID | ADDR_BNDRY(0xc) |
684                 INACTIVITY_TIMEOUT(0x1000);
685         gizmo_writel(val, AHB_MEM_PREFETCH_CFG4);
686
687 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
688         val = gizmo_readl(AHB_MEM_PREFETCH_CFG5);
689         val &= ~MST_ID(~0);
690         val |= PREFETCH_ENB | SDMMC4_MST_ID;
691         gizmo_writel(val, AHB_MEM_PREFETCH_CFG5);
692
693         val = gizmo_readl(AHB_MEM_PREFETCH_CFG6);
694         val &= ~MST_ID(~0);
695         val |= PREFETCH_ENB | SE_MST_ID | ADDR_BNDRY(0xc) |
696                 INACTIVITY_TIMEOUT(0x1000);
697         gizmo_writel(val, AHB_MEM_PREFETCH_CFG6);
698 #endif
699 }
700
701 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
702 void __init tegra20_init_early(void)
703 {
704 #ifndef CONFIG_SMP
705         /* For SMP system, initializing the reset handler here is too
706            late. For non-SMP systems, the function that calls the reset
707            handler initializer is not called, so do it here for non-SMP. */
708         tegra_cpu_reset_handler_init();
709 #endif
710         tegra_perf_init();
711         tegra_init_fuse();
712         tegra2_init_clocks();
713         tegra2_init_dvfs();
714         tegra_common_init_clock();
715         tegra_clk_init_from_table(tegra20_clk_init_table);
716         tegra_init_cache(true);
717         tegra_pmc_init();
718         tegra_powergate_init();
719         tegra_init_power();
720         tegra_init_ahb_gizmo_settings();
721         tegra_init_debug_uart_rate();
722         tegra_gpio_resume_init();
723         tegra_ram_console_debug_reserve(SZ_1M);
724 }
725 #endif
726 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
727 void __init tegra30_init_early(void)
728 {
729 #ifndef CONFIG_SMP
730         /* For SMP system, initializing the reset handler here is too
731            late. For non-SMP systems, the function that calls the reset
732            handler initializer is not called, so do it here for non-SMP. */
733         tegra_cpu_reset_handler_init();
734 #endif
735         tegra_perf_init();
736         tegra_init_fuse();
737         tegra30_init_clocks();
738         tegra3_init_dvfs();
739         tegra_common_init_clock();
740         tegra_clk_init_from_table(tegra30_clk_init_table);
741         tegra_clk_init_cbus_plls_from_table(tegra30_cbus_init_table);
742         tegra_init_cache(true);
743         tegra_pmc_init();
744         tegra_powergate_init();
745         tegra_init_power();
746         tegra_init_ahb_gizmo_settings();
747         tegra_init_debug_uart_rate();
748         tegra_gpio_resume_init();
749         tegra_ram_console_debug_reserve(SZ_1M);
750
751         init_dma_coherent_pool_size(SZ_1M);
752 }
753 #endif
754 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
755 void __init tegra11x_init_early(void)
756 {
757 #ifndef CONFIG_SMP
758         /* For SMP system, initializing the reset handler here is too
759            late. For non-SMP systems, the function that calls the reset
760            handler initializer is not called, so do it here for non-SMP. */
761         tegra_cpu_reset_handler_init();
762 #endif
763         tegra_perf_init();
764         tegra_init_fuse();
765         tegra_ramrepair_init();
766         tegra11x_init_clocks();
767         tegra11x_init_dvfs();
768         tegra_common_init_clock();
769         tegra_clk_init_from_table(tegra11x_clk_init_table);
770         tegra_clk_init_cbus_plls_from_table(tegra11x_cbus_init_table);
771         tegra11x_clk_init_la();
772         tegra_pmc_init();
773         tegra_powergate_init();
774         tegra_init_power();
775         tegra_init_ahb_gizmo_settings();
776         tegra_init_debug_uart_rate();
777         tegra_gpio_resume_init();
778 #ifdef CONFIG_TEGRA_ATOMICS
779         tegra_atomics_init();
780 #endif
781
782         init_dma_coherent_pool_size(SZ_1M);
783 }
784 #endif
785 static int __init tegra_lp0_vec_arg(char *options)
786 {
787         char *p = options;
788
789         tegra_lp0_vec_size = memparse(p, &p);
790         if (*p == '@')
791                 tegra_lp0_vec_start = memparse(p+1, &p);
792         if (!tegra_lp0_vec_size || !tegra_lp0_vec_start) {
793                 tegra_lp0_vec_size = 0;
794                 tegra_lp0_vec_start = 0;
795         }
796
797         return 0;
798 }
799 early_param("lp0_vec", tegra_lp0_vec_arg);
800
801 #ifdef CONFIG_TEGRA_NVDUMPER
802 static int __init tegra_nvdumper_arg(char *options)
803 {
804         char *p = options;
805
806         nvdumper_reserved = memparse(p, &p);
807         return 0;
808 }
809 early_param("nvdumper_reserved", tegra_nvdumper_arg);
810 #endif
811
812 static int __init tegra_bootloader_fb_arg(char *options)
813 {
814         char *p = options;
815
816         tegra_bootloader_fb_size = memparse(p, &p);
817         if (*p == '@')
818                 tegra_bootloader_fb_start = memparse(p+1, &p);
819
820         pr_info("Found tegra_fbmem: %08lx@%08lx\n",
821                 tegra_bootloader_fb_size, tegra_bootloader_fb_start);
822
823         return 0;
824 }
825 early_param("tegra_fbmem", tegra_bootloader_fb_arg);
826
827 static int __init tegra_bootloader_fb2_arg(char *options)
828 {
829         char *p = options;
830
831         tegra_bootloader_fb2_size = memparse(p, &p);
832         if (*p == '@')
833                 tegra_bootloader_fb2_start = memparse(p+1, &p);
834
835         pr_info("Found tegra_fbmem2: %08lx@%08lx\n",
836                 tegra_bootloader_fb2_size, tegra_bootloader_fb2_start);
837
838         return 0;
839 }
840 early_param("tegra_fbmem2", tegra_bootloader_fb2_arg);
841
842 static int __init tegra_sku_override(char *id)
843 {
844         char *p = id;
845
846         sku_override = memparse(p, &p);
847
848         return 0;
849 }
850 early_param("sku_override", tegra_sku_override);
851
852 int tegra_get_sku_override(void)
853 {
854         return sku_override;
855 }
856
857 static int __init tegra_vpr_arg(char *options)
858 {
859         char *p = options;
860
861         tegra_vpr_size = memparse(p, &p);
862         if (*p == '@')
863                 tegra_vpr_start = memparse(p+1, &p);
864         pr_info("Found vpr, start=0x%lx size=%lx",
865                 tegra_vpr_start, tegra_vpr_size);
866         return 0;
867 }
868 early_param("vpr", tegra_vpr_arg);
869
870 static int __init tegra_tsec_arg(char *options)
871 {
872         char *p = options;
873
874         tegra_tsec_size = memparse(p, &p);
875         if (*p == '@')
876                 tegra_tsec_start = memparse(p+1, &p);
877         pr_info("Found tsec, start=0x%lx size=%lx",
878                 tegra_tsec_start, tegra_tsec_size);
879         return 0;
880 }
881 early_param("tsec", tegra_tsec_arg);
882
883 #ifdef CONFIG_TEGRA_USE_NCT
884 static int __init tegra_nck_arg(char *options)
885 {
886         char *p = options;
887
888         tegra_nck_size = memparse(p, &p);
889         if (*p == '@')
890                 tegra_nck_start = memparse(p+1, &p);
891         if (!tegra_nck_size || !tegra_nck_start) {
892                 tegra_nck_size = 0;
893                 tegra_nck_start = 0;
894         }
895
896         return 0;
897 }
898 early_param("nck", tegra_nck_arg);
899 #endif  /* CONFIG_TEGRA_USE_NCT */
900
901 enum panel_type get_panel_type(void)
902 {
903         return board_panel_type;
904 }
905 static int __init tegra_board_panel_type(char *options)
906 {
907         if (!strcmp(options, "lvds"))
908                 board_panel_type = panel_type_lvds;
909         else if (!strcmp(options, "dsi"))
910                 board_panel_type = panel_type_dsi;
911         else
912                 return 0;
913         return 1;
914 }
915 __setup("panel=", tegra_board_panel_type);
916
917 int tegra_get_board_panel_id(void)
918 {
919         return panel_id;
920 }
921 static int __init tegra_board_panel_id(char *options)
922 {
923         char *p = options;
924         panel_id = memparse(p, &p);
925         return panel_id;
926 }
927 __setup("display_panel=", tegra_board_panel_id);
928
929 u8 get_power_config(void)
930 {
931         return power_config;
932 }
933 static int __init tegra_board_power_config(char *options)
934 {
935         char *p = options;
936         power_config = memparse(p, &p);
937         return 1;
938 }
939 __setup("power-config=", tegra_board_power_config);
940
941 enum power_supply_type get_power_supply_type(void)
942 {
943         return pow_supply_type;
944 }
945 static int __init tegra_board_power_supply_type(char *options)
946 {
947         if (!strcmp(options, "Adapter"))
948                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
949         if (!strcmp(options, "Mains"))
950                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
951         else if (!strcmp(options, "Battery"))
952                 pow_supply_type = POWER_SUPPLY_TYPE_BATTERY;
953         else
954                 return 0;
955         return 1;
956 }
957 __setup("power_supply=", tegra_board_power_supply_type);
958
959 int get_core_edp(void)
960 {
961         return pmu_core_edp;
962 }
963 static int __init tegra_pmu_core_edp(char *options)
964 {
965         char *p = options;
966         int core_edp = memparse(p, &p);
967         if (core_edp != 0)
968                 pmu_core_edp = core_edp;
969         return 0;
970 }
971 early_param("core_edp_mv", tegra_pmu_core_edp);
972
973 int get_maximum_cpu_current_supported(void)
974 {
975         return max_cpu_current;
976 }
977 static int __init tegra_max_cpu_current(char *options)
978 {
979         char *p = options;
980         max_cpu_current = memparse(p, &p);
981         return 1;
982 }
983 __setup("max_cpu_cur_ma=", tegra_max_cpu_current);
984
985 int get_maximum_core_current_supported(void)
986 {
987         return max_core_current;
988 }
989 static int __init tegra_max_core_current(char *options)
990 {
991         char *p = options;
992         max_core_current = memparse(p, &p);
993         return 1;
994 }
995 __setup("core_edp_ma=", tegra_max_core_current);
996
997 int get_emc_max_dvfs(void)
998 {
999         return emc_max_dvfs;
1000 }
1001 static int __init tegra_emc_max_dvfs(char *options)
1002 {
1003         char *p = options;
1004         emc_max_dvfs = memparse(p, &p);
1005         return 1;
1006 }
1007 __setup("emc_max_dvfs=", tegra_emc_max_dvfs);
1008
1009 int tegra_get_memory_type(void)
1010 {
1011         return memory_type;
1012 }
1013 static int __init tegra_memory_type(char *options)
1014 {
1015         char *p = options;
1016         memory_type = memparse(p, &p);
1017         return 1;
1018 }
1019 __setup("memtype=", tegra_memory_type);
1020
1021 static int __init tegra_debug_uartport(char *info)
1022 {
1023         char *p = info;
1024         unsigned long long port_id;
1025         if (!strncmp(p, "hsport", 6))
1026                 is_tegra_debug_uart_hsport = true;
1027         else if (!strncmp(p, "lsport", 6))
1028                 is_tegra_debug_uart_hsport = false;
1029
1030         if (p[6] == ',') {
1031                 if (p[7] == '-') {
1032                         debug_uart_port_id = -1;
1033                 } else {
1034                         port_id = memparse(p + 7, &p);
1035                         debug_uart_port_id = (int) port_id;
1036                 }
1037         } else {
1038                 debug_uart_port_id = -1;
1039         }
1040
1041         return 1;
1042 }
1043
1044 bool is_tegra_debug_uartport_hs(void)
1045 {
1046         return is_tegra_debug_uart_hsport;
1047 }
1048
1049 int get_tegra_uart_debug_port_id(void)
1050 {
1051         return debug_uart_port_id;
1052 }
1053 __setup("debug_uartport=", tegra_debug_uartport);
1054
1055 static int __init tegra_image_type(char *options)
1056 {
1057         if (!strcmp(options, "RCK"))
1058                 board_image_type = rck_image;
1059
1060         return 0;
1061 }
1062
1063 enum image_type get_tegra_image_type(void)
1064 {
1065         return board_image_type;
1066 }
1067
1068 __setup("image=", tegra_image_type);
1069
1070 static int __init tegra_audio_codec_type(char *info)
1071 {
1072         char *p = info;
1073         if (!strncmp(p, "wm8903", 6))
1074                 audio_codec_name = audio_codec_wm8903;
1075         else
1076                 audio_codec_name = audio_codec_none;
1077
1078         return 1;
1079 }
1080
1081 enum audio_codec_type get_audio_codec_type(void)
1082 {
1083         return audio_codec_name;
1084 }
1085 __setup("audio_codec=", tegra_audio_codec_type);
1086
1087 static int tegra_get_pwr_i2c_clk_rate(char *options)
1088 {
1089         int clk = simple_strtol(options, NULL, 16);
1090         if (clk != 0)
1091                 pwr_i2c_clk = clk;
1092         return 0;
1093 }
1094
1095 int get_pwr_i2c_clk_rate(void)
1096 {
1097         return pwr_i2c_clk;
1098 }
1099 __setup("pwr_i2c=", tegra_get_pwr_i2c_clk_rate);
1100
1101 void tegra_get_board_info(struct board_info *bi)
1102 {
1103 #ifdef CONFIG_OF
1104         struct device_node *board_info;
1105         u32 prop_val;
1106         int err;
1107
1108         board_info = of_find_node_by_path("/chosen/board_info");
1109         if (!IS_ERR_OR_NULL(board_info)) {
1110                 memset(bi, 0, sizeof(*bi));
1111
1112                 err = of_property_read_u32(board_info, "id", &prop_val);
1113                 if (err)
1114                         pr_err("failed to read /chosen/board_info/id\n");
1115                 else
1116                         bi->board_id = prop_val;
1117
1118                 err = of_property_read_u32(board_info, "sku", &prop_val);
1119                 if (err)
1120                         pr_err("failed to read /chosen/board_info/sku\n");
1121                 else
1122                         bi->sku = prop_val;
1123
1124                 err = of_property_read_u32(board_info, "fab", &prop_val);
1125                 if (err)
1126                         pr_err("failed to read /chosen/board_info/fab\n");
1127                 else
1128                         bi->fab = prop_val;
1129
1130                 err = of_property_read_u32(board_info, "major_revision", &prop_val);
1131                 if (err)
1132                         pr_err("failed to read /chosen/board_info/major_revision\n");
1133                 else
1134                         bi->major_revision = prop_val;
1135
1136                 err = of_property_read_u32(board_info, "minor_revision", &prop_val);
1137                 if (err)
1138                         pr_err("failed to read /chosen/board_info/minor_revision\n");
1139                 else
1140                         bi->minor_revision = prop_val;
1141                 system_serial_high = (bi->board_id << 16) | bi->sku;
1142                 system_serial_low = (bi->fab << 24) |
1143                         (bi->major_revision << 16) | (bi->minor_revision << 8);
1144         } else {
1145 #endif
1146                 bi->board_id = (system_serial_high >> 16) & 0xFFFF;
1147                 bi->sku = (system_serial_high) & 0xFFFF;
1148                 bi->fab = (system_serial_low >> 24) & 0xFF;
1149                 bi->major_revision = (system_serial_low >> 16) & 0xFF;
1150                 bi->minor_revision = (system_serial_low >> 8) & 0xFF;
1151 #ifdef CONFIG_OF
1152         }
1153 #endif
1154 }
1155
1156 static int __init tegra_pmu_board_info(char *info)
1157 {
1158         char *p = info;
1159         pmu_board_info.board_id = memparse(p, &p);
1160         pmu_board_info.sku = memparse(p+1, &p);
1161         pmu_board_info.fab = memparse(p+1, &p);
1162         pmu_board_info.major_revision = memparse(p+1, &p);
1163         pmu_board_info.minor_revision = memparse(p+1, &p);
1164         return 1;
1165 }
1166
1167 void tegra_get_pmu_board_info(struct board_info *bi)
1168 {
1169         memcpy(bi, &pmu_board_info, sizeof(struct board_info));
1170 }
1171
1172 __setup("pmuboard=", tegra_pmu_board_info);
1173
1174 static int __init tegra_display_board_info(char *info)
1175 {
1176         char *p = info;
1177         display_board_info.board_id = memparse(p, &p);
1178         display_board_info.sku = memparse(p+1, &p);
1179         display_board_info.fab = memparse(p+1, &p);
1180         display_board_info.major_revision = memparse(p+1, &p);
1181         display_board_info.minor_revision = memparse(p+1, &p);
1182         return 1;
1183 }
1184
1185 void tegra_get_display_board_info(struct board_info *bi)
1186 {
1187         memcpy(bi, &display_board_info, sizeof(struct board_info));
1188 }
1189
1190 __setup("displayboard=", tegra_display_board_info);
1191
1192 static int __init tegra_camera_board_info(char *info)
1193 {
1194         char *p = info;
1195         camera_board_info.board_id = memparse(p, &p);
1196         camera_board_info.sku = memparse(p+1, &p);
1197         camera_board_info.fab = memparse(p+1, &p);
1198         camera_board_info.major_revision = memparse(p+1, &p);
1199         camera_board_info.minor_revision = memparse(p+1, &p);
1200         return 1;
1201 }
1202
1203 void tegra_get_camera_board_info(struct board_info *bi)
1204 {
1205         memcpy(bi, &camera_board_info, sizeof(struct board_info));
1206 }
1207
1208 __setup("cameraboard=", tegra_camera_board_info);
1209
1210 static int __init tegra_leftspeaker_board_info(char *info)
1211 {
1212         char *p = info;
1213         leftspeaker_board_info.board_id = memparse(p, &p);
1214         leftspeaker_board_info.sku = memparse(p+1, &p);
1215         leftspeaker_board_info.fab = memparse(p+1, &p);
1216         leftspeaker_board_info.major_revision = memparse(p+1, &p);
1217         leftspeaker_board_info.minor_revision = memparse(p+1, &p);
1218         return 1;
1219 }
1220
1221 void tegra_get_leftspeaker_board_info(struct board_info *bi)
1222 {
1223         memcpy(bi, &leftspeaker_board_info, sizeof(struct board_info));
1224 }
1225
1226 __setup("leftspeakerboard=", tegra_leftspeaker_board_info);
1227
1228 static int __init tegra_rightspeaker_board_info(char *info)
1229 {
1230         char *p = info;
1231         rightspeaker_board_info.board_id = memparse(p, &p);
1232         rightspeaker_board_info.sku = memparse(p+1, &p);
1233         rightspeaker_board_info.fab = memparse(p+1, &p);
1234         rightspeaker_board_info.major_revision = memparse(p+1, &p);
1235         rightspeaker_board_info.minor_revision = memparse(p+1, &p);
1236         return 1;
1237 }
1238
1239 void tegra_get_rightspeaker_board_info(struct board_info *bi)
1240 {
1241         memcpy(bi, &rightspeaker_board_info, sizeof(struct board_info));
1242 }
1243
1244 __setup("rightspeakerboard=", tegra_rightspeaker_board_info);
1245
1246 static int __init tegra_joystick_board_info(char *info)
1247 {
1248         char *p = info;
1249         joystick_board_info.board_id = memparse(p, &p);
1250         joystick_board_info.sku = memparse(p+1, &p);
1251         joystick_board_info.fab = memparse(p+1, &p);
1252         joystick_board_info.major_revision = memparse(p+1, &p);
1253         joystick_board_info.minor_revision = memparse(p+1, &p);
1254         return 1;
1255 }
1256
1257 void tegra_get_joystick_board_info(struct board_info *bi)
1258 {
1259         memcpy(bi, &joystick_board_info, sizeof(struct board_info));
1260 }
1261
1262 __setup("joystickboard=", tegra_joystick_board_info);
1263
1264 static int __init tegra_button_board_info(char *info)
1265 {
1266         char *p = info;
1267         button_board_info.board_id = memparse(p, &p);
1268         button_board_info.sku = memparse(p+1, &p);
1269         button_board_info.fab = memparse(p+1, &p);
1270         button_board_info.major_revision = memparse(p+1, &p);
1271         button_board_info.minor_revision = memparse(p+1, &p);
1272         return 1;
1273 }
1274
1275 void tegra_get_button_board_info(struct board_info *bi)
1276 {
1277         memcpy(bi, &button_board_info, sizeof(struct board_info));
1278 }
1279
1280 __setup("buttonboard=", tegra_button_board_info);
1281
1282 static int __init tegra_io_board_info(char *info)
1283 {
1284         char *p = info;
1285         io_board_info.board_id = memparse(p, &p);
1286         io_board_info.sku = memparse(p+1, &p);
1287         io_board_info.fab = memparse(p+1, &p);
1288         io_board_info.major_revision = memparse(p+1, &p);
1289         io_board_info.minor_revision = memparse(p+1, &p);
1290         return 1;
1291 }
1292
1293 void tegra_get_io_board_info(struct board_info *bi)
1294 {
1295         memcpy(bi, &io_board_info, sizeof(struct board_info));
1296 }
1297
1298 __setup("ioboard=", tegra_io_board_info);
1299
1300 static int __init tegra_modem_id(char *id)
1301 {
1302         char *p = id;
1303
1304         modem_id = memparse(p, &p);
1305         return 1;
1306 }
1307
1308 int tegra_get_modem_id(void)
1309 {
1310         return modem_id;
1311 }
1312
1313 __setup("modem_id=", tegra_modem_id);
1314
1315 static int __init tegra_usb_port_owner_info(char *id)
1316 {
1317         char *p = id;
1318
1319         usb_port_owner_info = memparse(p, &p);
1320         return 1;
1321 }
1322
1323 int tegra_get_usb_port_owner_info(void)
1324 {
1325         return usb_port_owner_info;
1326 }
1327
1328 __setup("usb_port_owner_info=", tegra_usb_port_owner_info);
1329
1330 static int __init tegra_commchip_id(char *id)
1331 {
1332         char *p = id;
1333
1334         if (get_option(&p, &commchip_id) != 1)
1335                 return 0;
1336         return 1;
1337 }
1338
1339 int tegra_get_commchip_id(void)
1340 {
1341         return commchip_id;
1342 }
1343
1344 __setup("commchip_id=", tegra_commchip_id);
1345
1346 int tegra_get_pmic_rst_reason(void)
1347 {
1348         return pmic_rst_reason;
1349 }
1350
1351 static int __init tegra_pmic_rst_reason(char *id)
1352 {
1353         char *p = id;
1354         pmic_rst_reason = memparse(p, &p);
1355         return 1;
1356 }
1357
1358 __setup("pmic_rst_reason=", tegra_pmic_rst_reason);
1359
1360 #ifdef CONFIG_ANDROID
1361 static bool androidboot_mode_charger;
1362
1363 bool get_androidboot_mode_charger(void)
1364 {
1365         return androidboot_mode_charger;
1366 }
1367 static int __init tegra_androidboot_mode(char *options)
1368 {
1369         if (!strcmp(options, "charger"))
1370                 androidboot_mode_charger = true;
1371         else
1372                 androidboot_mode_charger = false;
1373         return 1;
1374 }
1375 __setup("androidboot.mode=", tegra_androidboot_mode);
1376 #endif
1377
1378 /*
1379  * Tegra has a protected aperture that prevents access by most non-CPU
1380  * memory masters to addresses above the aperture value.  Enabling it
1381  * secures the CPU's memory from the GPU, except through the GART.
1382  */
1383 void __init tegra_protected_aperture_init(unsigned long aperture)
1384 {
1385 #ifndef CONFIG_NVMAP_ALLOW_SYSMEM
1386         void __iomem *mc_base = IO_ADDRESS(TEGRA_MC_BASE);
1387         pr_info("Enabling Tegra protected aperture at 0x%08lx\n", aperture);
1388         writel(aperture, mc_base + MC_SECURITY_CFG2);
1389 #else
1390         pr_err("Tegra protected aperture disabled because nvmap is using "
1391                 "system memory\n");
1392 #endif
1393 }
1394
1395 /*
1396  * Due to conflicting restrictions on the placement of the framebuffer,
1397  * the bootloader is likely to leave the framebuffer pointed at a location
1398  * in memory that is outside the grhost aperture.  This function will move
1399  * the framebuffer contents from a physical address that is anywhere (lowmem,
1400  * highmem, or outside the memory map) to a physical address that is outside
1401  * the memory map.
1402  */
1403 void __tegra_move_framebuffer(struct platform_device *pdev,
1404         unsigned long to, unsigned long from,
1405         unsigned long size)
1406 {
1407         struct page *page;
1408         void __iomem *to_io;
1409         void *from_virt;
1410         unsigned long i, addr[] = { to, from, };
1411
1412         BUG_ON(PAGE_ALIGN((unsigned long)to) != (unsigned long)to);
1413         BUG_ON(PAGE_ALIGN(from) != from);
1414         BUG_ON(PAGE_ALIGN(size) != size);
1415
1416         to_io = ioremap(to, size);
1417         if (!to_io) {
1418                 pr_err("%s: Failed to map target framebuffer\n", __func__);
1419                 return;
1420         }
1421
1422         if (pfn_valid(page_to_pfn(phys_to_page(from)))) {
1423                 for (i = 0 ; i < size; i += PAGE_SIZE) {
1424                         page = phys_to_page(from + i);
1425                         from_virt = kmap(page);
1426                         memcpy(to_io + i, from_virt, PAGE_SIZE);
1427                         kunmap(page);
1428                 }
1429         } else {
1430                 void __iomem *from_io = ioremap(from, size);
1431                 if (!from_io) {
1432                         pr_err("%s: Failed to map source framebuffer\n",
1433                                 __func__);
1434                         goto out;
1435                 }
1436
1437                 for (i = 0; i < size; i += 4)
1438                         writel(readl(from_io + i), to_io + i);
1439
1440                 iounmap(from_io);
1441         }
1442
1443         for (i = 0; i < ARRAY_SIZE(addr); i++)
1444                 dma_map_linear_at(NULL, addr[i], size, DMA_TO_DEVICE);
1445 out:
1446         iounmap(to_io);
1447 }
1448
1449 void __tegra_clear_framebuffer(struct platform_device *pdev,
1450                                unsigned long to, unsigned long size)
1451 {
1452         void __iomem *to_io;
1453         unsigned long i;
1454
1455         BUG_ON(PAGE_ALIGN((unsigned long)to) != (unsigned long)to);
1456         BUG_ON(PAGE_ALIGN(size) != size);
1457
1458         to_io = ioremap(to, size);
1459         if (!to_io) {
1460                 pr_err("%s: Failed to map target framebuffer\n", __func__);
1461                 return;
1462         }
1463
1464         if (pfn_valid(page_to_pfn(phys_to_page(to)))) {
1465                 for (i = 0 ; i < size; i += PAGE_SIZE)
1466                         memset(to_io + i, 0, PAGE_SIZE);
1467         } else {
1468                 for (i = 0; i < size; i += 4)
1469                         writel(0, to_io + i);
1470         }
1471         iounmap(to_io);
1472 }
1473
1474 void __init tegra_reserve(unsigned long carveout_size, unsigned long fb_size,
1475         unsigned long fb2_size)
1476 {
1477         const size_t avp_kernel_reserve = SZ_32M;
1478 #if !defined(CONFIG_TEGRA_AVP_KERNEL_ON_MMU) /* Tegra2 with AVP MMU */ && \
1479         !defined(CONFIG_TEGRA_AVP_KERNEL_ON_SMMU) /* Tegra3 & up with SMMU */
1480         /* Reserve hardcoded AVP kernel load area starting at 0xXe000000*/
1481         tegra_avp_kernel_size = SZ_1M;
1482         tegra_avp_kernel_start = memblock_end_of_DRAM() - avp_kernel_reserve;
1483         if (memblock_remove(tegra_avp_kernel_start, avp_kernel_reserve)) {
1484                 pr_err("Failed to remove AVP kernel load area %08lx@%08lx "
1485                                 "from memory map\n",
1486                         (unsigned long)avp_kernel_reserve,
1487                         tegra_avp_kernel_start);
1488                 tegra_avp_kernel_size = 0;
1489         }
1490 #endif
1491
1492         if (carveout_size) {
1493                 tegra_carveout_start = memblock_end_of_DRAM() - carveout_size;
1494                 if (memblock_remove(tegra_carveout_start, carveout_size)) {
1495                         pr_err("Failed to remove carveout %08lx@%08lx "
1496                                 "from memory map\n",
1497                                 carveout_size, tegra_carveout_start);
1498                         tegra_carveout_start = 0;
1499                         tegra_carveout_size = 0;
1500                 } else
1501                         tegra_carveout_size = carveout_size;
1502         }
1503
1504         if (fb2_size) {
1505                 tegra_fb2_start = memblock_end_of_DRAM() - fb2_size;
1506                 if (memblock_remove(tegra_fb2_start, fb2_size)) {
1507                         pr_err("Failed to remove second framebuffer "
1508                                 "%08lx@%08lx from memory map\n",
1509                                 fb2_size, tegra_fb2_start);
1510                         tegra_fb2_start = 0;
1511                         tegra_fb2_size = 0;
1512                 } else
1513                         tegra_fb2_size = fb2_size;
1514         }
1515
1516         if (fb_size) {
1517                 tegra_fb_start = memblock_end_of_DRAM() - fb_size;
1518                 if (memblock_remove(tegra_fb_start, fb_size)) {
1519                         pr_err("Failed to remove framebuffer %08lx@%08lx "
1520                                 "from memory map\n",
1521                                 fb_size, tegra_fb_start);
1522                         tegra_fb_start = 0;
1523                         tegra_fb_size = 0;
1524                 } else
1525                         tegra_fb_size = fb_size;
1526         }
1527
1528         if (tegra_fb_size)
1529                 tegra_grhost_aperture = tegra_fb_start;
1530
1531         if (tegra_fb2_size && tegra_fb2_start < tegra_grhost_aperture)
1532                 tegra_grhost_aperture = tegra_fb2_start;
1533
1534         if (tegra_carveout_size && tegra_carveout_start < tegra_grhost_aperture)
1535                 tegra_grhost_aperture = tegra_carveout_start;
1536
1537         if (tegra_lp0_vec_size &&
1538            (tegra_lp0_vec_start < memblock_end_of_DRAM())) {
1539                 if (memblock_reserve(tegra_lp0_vec_start, tegra_lp0_vec_size)) {
1540                         pr_err("Failed to reserve lp0_vec %08lx@%08lx\n",
1541                                 tegra_lp0_vec_size, tegra_lp0_vec_start);
1542                         tegra_lp0_vec_start = 0;
1543                         tegra_lp0_vec_size = 0;
1544                 }
1545                 tegra_lp0_vec_relocate = false;
1546         } else
1547                 tegra_lp0_vec_relocate = true;
1548
1549 #ifdef CONFIG_TEGRA_NVDUMPER
1550         if (nvdumper_reserved) {
1551                 if (memblock_reserve(nvdumper_reserved, NVDUMPER_RESERVED_SIZE)) {
1552                         pr_err("Failed to reserve nvdumper page %08lx@%08lx\n",
1553                                nvdumper_reserved, NVDUMPER_RESERVED_SIZE);
1554                         nvdumper_reserved = 0;
1555                 }
1556         }
1557 #endif
1558
1559 #ifdef CONFIG_TEGRA_USE_NCT
1560         if (tegra_nck_size &&
1561            (tegra_nck_start < memblock_end_of_DRAM())) {
1562                 if (memblock_reserve(tegra_nck_start, tegra_nck_size)) {
1563                         pr_err("Failed to reserve nck %08lx@%08lx\n",
1564                                 tegra_nck_size, tegra_nck_start);
1565                         tegra_nck_start = 0;
1566                         tegra_nck_size = 0;
1567                 }
1568         }
1569 #endif
1570
1571         /*
1572          * We copy the bootloader's framebuffer to the framebuffer allocated
1573          * above, and then free this one.
1574          * */
1575         if (tegra_bootloader_fb_size) {
1576                 tegra_bootloader_fb_size = PAGE_ALIGN(tegra_bootloader_fb_size);
1577                 if (memblock_reserve(tegra_bootloader_fb_start,
1578                                 tegra_bootloader_fb_size)) {
1579                         pr_err("Failed to reserve bootloader frame buffer "
1580                                 "%08lx@%08lx\n", tegra_bootloader_fb_size,
1581                                 tegra_bootloader_fb_start);
1582                         tegra_bootloader_fb_start = 0;
1583                         tegra_bootloader_fb_size = 0;
1584                 }
1585         }
1586
1587         if (tegra_bootloader_fb2_size) {
1588                 tegra_bootloader_fb2_size =
1589                                 PAGE_ALIGN(tegra_bootloader_fb2_size);
1590                 if (memblock_reserve(tegra_bootloader_fb2_start,
1591                                 tegra_bootloader_fb2_size)) {
1592                         pr_err("Failed to reserve bootloader fb2 %08lx@%08lx\n",
1593                                 tegra_bootloader_fb2_size,
1594                                 tegra_bootloader_fb2_start);
1595                         tegra_bootloader_fb2_start = 0;
1596                         tegra_bootloader_fb2_size = 0;
1597                 }
1598         }
1599
1600         pr_info("Tegra reserved memory:\n"
1601                 "LP0:                    %08lx - %08lx\n"
1602                 "Bootloader framebuffer: %08lx - %08lx\n"
1603                 "Bootloader framebuffer2: %08lx - %08lx\n"
1604                 "Framebuffer:            %08lx - %08lx\n"
1605                 "2nd Framebuffer:        %08lx - %08lx\n"
1606                 "Carveout:               %08lx - %08lx\n"
1607                 "Vpr:                    %08lx - %08lx\n"
1608                 "Tsec:                   %08lx - %08lx\n",
1609                 tegra_lp0_vec_start,
1610                 tegra_lp0_vec_size ?
1611                         tegra_lp0_vec_start + tegra_lp0_vec_size - 1 : 0,
1612                 tegra_bootloader_fb_start,
1613                 tegra_bootloader_fb_size ?
1614                  tegra_bootloader_fb_start + tegra_bootloader_fb_size - 1 : 0,
1615                 tegra_bootloader_fb2_start,
1616                 tegra_bootloader_fb2_size ?
1617                  tegra_bootloader_fb2_start + tegra_bootloader_fb2_size - 1 : 0,
1618                 tegra_fb_start,
1619                 tegra_fb_size ?
1620                         tegra_fb_start + tegra_fb_size - 1 : 0,
1621                 tegra_fb2_start,
1622                 tegra_fb2_size ?
1623                         tegra_fb2_start + tegra_fb2_size - 1 : 0,
1624                 tegra_carveout_start,
1625                 tegra_carveout_size ?
1626                         tegra_carveout_start + tegra_carveout_size - 1 : 0,
1627                 tegra_vpr_start,
1628                 tegra_vpr_size ?
1629                         tegra_vpr_start + tegra_vpr_size - 1 : 0,
1630                 tegra_tsec_start,
1631                 tegra_tsec_size ?
1632                         tegra_tsec_start + tegra_tsec_size - 1 : 0);
1633
1634         if (tegra_avp_kernel_size) {
1635                 /* Return excessive memory reserved for AVP kernel */
1636                 if (tegra_avp_kernel_size < avp_kernel_reserve)
1637                         memblock_add(
1638                                 tegra_avp_kernel_start + tegra_avp_kernel_size,
1639                                 avp_kernel_reserve - tegra_avp_kernel_size);
1640                 pr_info(
1641                 "AVP kernel: %08lx - %08lx\n",
1642                         tegra_avp_kernel_start,
1643                         tegra_avp_kernel_start + tegra_avp_kernel_size - 1);
1644         }
1645
1646 #ifdef CONFIG_TEGRA_NVDUMPER
1647         if (nvdumper_reserved) {
1648                 pr_info("Nvdumper:               %08lx - %08lx\n",
1649                         nvdumper_reserved,
1650                         nvdumper_reserved + NVDUMPER_RESERVED_SIZE - 1);
1651         }
1652 #endif
1653 #ifdef CONFIG_TEGRA_USE_NCT
1654         if (tegra_nck_size) {
1655                 pr_info("Nck:                    %08lx - %08lx\n",
1656                         tegra_nck_start,
1657                         tegra_nck_size ?
1658                                 tegra_nck_start + tegra_nck_size - 1 : 0);
1659         }
1660 #endif
1661 }
1662
1663 #ifdef CONFIG_ANDROID_RAM_CONSOLE
1664 static struct persistent_ram_descriptor desc = {
1665         .name = "ram_console",
1666 };
1667
1668 static struct persistent_ram ram = {
1669         .descs = &desc,
1670         .num_descs = 1,
1671 };
1672
1673 void __init tegra_ram_console_debug_reserve(unsigned long ram_console_size)
1674 {
1675         int ret;
1676
1677         ram.start = memblock_end_of_DRAM() - ram_console_size;
1678         ram.size = ram_console_size;
1679         ram.descs->size = ram_console_size;
1680
1681         INIT_LIST_HEAD(&ram.node);
1682
1683         ret = persistent_ram_early_init(&ram);
1684         if (ret)
1685                 goto fail;
1686
1687         return;
1688
1689 fail:
1690         pr_err("Failed to reserve memory block for ram console\n");
1691 }
1692
1693 static struct resource ram_console_resources[] = {
1694         {
1695                 .flags = IORESOURCE_MEM,
1696         },
1697 };
1698
1699 static struct platform_device ram_console_device = {
1700         .name           = "ram_console",
1701         .id             = -1,
1702         .num_resources  = ARRAY_SIZE(ram_console_resources),
1703         .resource       = ram_console_resources,
1704 };
1705
1706 void __init tegra_ram_console_debug_init(void)
1707 {
1708         int err;
1709
1710         err = platform_device_register(&ram_console_device);
1711         if (err)
1712                 pr_err("%s: ram console registration failed (%d)!\n",
1713                         __func__, err);
1714 }
1715 #endif
1716
1717 int __init tegra_register_fuse(void)
1718 {
1719         return platform_device_register(&tegra_fuse_device);
1720 }
1721
1722 void __init tegra_release_bootloader_fb(void)
1723 {
1724         /* Since bootloader fb is reserved in common.c, it is freed here. */
1725         if (tegra_bootloader_fb_size) {
1726                 if (memblock_free(tegra_bootloader_fb_start,
1727                                                 tegra_bootloader_fb_size))
1728                         pr_err("Failed to free bootloader fb.\n");
1729                 else
1730                         free_bootmem_late(tegra_bootloader_fb_start,
1731                                                 tegra_bootloader_fb_size);
1732         }
1733         if (tegra_bootloader_fb2_size) {
1734                 if (memblock_free(tegra_bootloader_fb2_start,
1735                                                 tegra_bootloader_fb2_size))
1736                         pr_err("Failed to free bootloader fb2.\n");
1737                 else
1738                         free_bootmem_late(tegra_bootloader_fb2_start,
1739                                                 tegra_bootloader_fb2_size);
1740         }
1741 }
1742
1743 static struct platform_device *pinmux_devices[] = {
1744         &tegra_gpio_device,
1745         &tegra_pinmux_device,
1746 };
1747
1748 void tegra_enable_pinmux(void)
1749 {
1750         platform_add_devices(pinmux_devices, ARRAY_SIZE(pinmux_devices));
1751 }
1752
1753 static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
1754         [TEGRA_REVISION_UNKNOWN] = "unknown",
1755         [TEGRA_REVISION_A01]     = "A01",
1756         [TEGRA_REVISION_A02]     = "A02",
1757         [TEGRA_REVISION_A03]     = "A03",
1758         [TEGRA_REVISION_A03p]    = "A03 prime",
1759         [TEGRA_REVISION_A04]     = "A04",
1760         [TEGRA_REVISION_A04p]    = "A04 prime",
1761         [TEGRA_REVISION_QT]      = "QT",
1762 };
1763
1764 static const char * __init tegra_get_revision(void)
1765 {
1766         return kasprintf(GFP_KERNEL, "%s", tegra_revision_name[tegra_revision]);
1767 }
1768
1769 static const char * __init tegra_get_family(void)
1770 {
1771         void __iomem *chip_id = IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804;
1772         u32 cid = readl(chip_id);
1773         cid = (cid >> 8) & 0xFF;
1774
1775         switch (cid) {
1776         case TEGRA_CHIPID_TEGRA2:
1777                 cid = 2;
1778                 break;
1779         case TEGRA_CHIPID_TEGRA3:
1780                 cid = 3;
1781                 break;
1782         case TEGRA_CHIPID_TEGRA11:
1783                 cid = 11;
1784                 break;
1785
1786         case TEGRA_CHIPID_UNKNOWN:
1787         default:
1788                 cid = 0;
1789         }
1790         return kasprintf(GFP_KERNEL, "Tegra%d", cid);
1791 }
1792
1793 static const char * __init tegra_get_soc_id(void)
1794 {
1795         int package_id = tegra_package_id();
1796         return kasprintf(GFP_KERNEL, "REV=%s:SKU=0x%x:PID=0x%x",
1797                 tegra_revision_name[tegra_revision], tegra_sku_id, package_id);
1798 }
1799
1800 static void __init tegra_soc_info_populate(struct soc_device_attribute
1801         *soc_dev_attr, const char *machine)
1802 {
1803         soc_dev_attr->soc_id = tegra_get_soc_id();
1804         soc_dev_attr->machine  = machine;
1805         soc_dev_attr->family   = tegra_get_family();
1806         soc_dev_attr->revision = tegra_get_revision();
1807 }
1808
1809 int __init tegra_soc_device_init(const char *machine)
1810 {
1811         struct soc_device *soc_dev;
1812         struct soc_device_attribute *soc_dev_attr;
1813
1814         soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
1815         if (!soc_dev_attr)
1816                 return -ENOMEM;
1817
1818         tegra_soc_info_populate(soc_dev_attr, machine);
1819
1820         soc_dev = soc_device_register(soc_dev_attr);
1821         if (IS_ERR_OR_NULL(soc_dev)) {
1822                 kfree(soc_dev_attr);
1823                 return -1;
1824         }
1825
1826         return 0;
1827 }
1828 struct arm_soc_desc tegra_soc_desc __initdata = {
1829         .name           = "NVIDIA Tegra",
1830         soc_smp_init_ops(tegra_soc_smp_init_ops)
1831         soc_smp_ops(tegra_soc_smp_ops)
1832 };