arm: tegra: sd: enable sd dpd
[linux-2.6.git] / arch / arm / mach-tegra / common.c
1 /*
2  * arch/arm/mach-tegra/common.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Copyright (C) 2010-2012 NVIDIA Corporation
6  *
7  * Author:
8  *      Colin Cross <ccross@android.com>
9  *
10  * This software is licensed under the terms of the GNU General Public
11  * License version 2, as published by the Free Software Foundation, and
12  * may be copied, distributed, and modified under those terms.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  */
20
21 #include <linux/platform_device.h>
22 #include <linux/console.h>
23 #include <linux/init.h>
24 #include <linux/io.h>
25 #include <linux/clk.h>
26 #include <linux/delay.h>
27 #include <linux/highmem.h>
28 #include <linux/memblock.h>
29 #include <linux/bitops.h>
30 #include <linux/sched.h>
31 #include <linux/cpufreq.h>
32
33 #include <asm/hardware/cache-l2x0.h>
34 #include <asm/system.h>
35
36 #include <mach/gpio.h>
37 #include <mach/iomap.h>
38 #include <mach/pinmux.h>
39 #include <mach/powergate.h>
40 #include <mach/system.h>
41 #include <mach/tegra_smmu.h>
42
43 #include "apbio.h"
44 #include "board.h"
45 #include "clock.h"
46 #include "fuse.h"
47 #include "pm.h"
48 #include "reset.h"
49 #include "devices.h"
50
51 #define MC_SECURITY_CFG2        0x7c
52
53 #define AHB_ARBITRATION_PRIORITY_CTRL           0x4
54 #define   AHB_PRIORITY_WEIGHT(x)        (((x) & 0x7) << 29)
55 #define   PRIORITY_SELECT_USB   BIT(6)
56 #define   PRIORITY_SELECT_USB2  BIT(18)
57 #define   PRIORITY_SELECT_USB3  BIT(17)
58
59 #define AHB_GIZMO_AHB_MEM               0xc
60 #define   ENB_FAST_REARBITRATE  BIT(2)
61 #define   DONT_SPLIT_AHB_WR     BIT(7)
62
63 #define   RECOVERY_MODE BIT(31)
64 #define   BOOTLOADER_MODE       BIT(30)
65 #define   FORCED_RECOVERY_MODE  BIT(1)
66
67 #define AHB_GIZMO_USB           0x1c
68 #define AHB_GIZMO_USB2          0x78
69 #define AHB_GIZMO_USB3          0x7c
70 #define   IMMEDIATE     BIT(18)
71
72 #define AHB_MEM_PREFETCH_CFG3   0xe0
73 #define AHB_MEM_PREFETCH_CFG4   0xe4
74 #define AHB_MEM_PREFETCH_CFG1   0xec
75 #define AHB_MEM_PREFETCH_CFG2   0xf0
76 #define   PREFETCH_ENB  BIT(31)
77 #define   MST_ID(x)     (((x) & 0x1f) << 26)
78 #define   AHBDMA_MST_ID MST_ID(5)
79 #define   USB_MST_ID    MST_ID(6)
80 #define   USB2_MST_ID   MST_ID(18)
81 #define   USB3_MST_ID   MST_ID(17)
82 #define   ADDR_BNDRY(x) (((x) & 0xf) << 21)
83 #define   INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0)
84
85 unsigned long tegra_bootloader_fb_start;
86 unsigned long tegra_bootloader_fb_size;
87 unsigned long tegra_fb_start;
88 unsigned long tegra_fb_size;
89 unsigned long tegra_fb2_start;
90 unsigned long tegra_fb2_size;
91 unsigned long tegra_carveout_start;
92 unsigned long tegra_carveout_size;
93 unsigned long tegra_vpr_start;
94 unsigned long tegra_vpr_size;
95 unsigned long tegra_lp0_vec_start;
96 unsigned long tegra_lp0_vec_size;
97 bool tegra_lp0_vec_relocate;
98 unsigned long tegra_grhost_aperture = ~0ul;
99 static   bool is_tegra_debug_uart_hsport;
100 static struct board_info pmu_board_info;
101 static struct board_info display_board_info;
102 static struct board_info camera_board_info;
103
104 static int pmu_core_edp = 1200; /* default 1.2V EDP limit */
105 static int board_panel_type;
106 static enum power_supply_type pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
107
108 void (*arch_reset)(char mode, const char *cmd) = tegra_assert_system_reset;
109
110 #define NEVER_RESET 0
111
112 void tegra_assert_system_reset(char mode, const char *cmd)
113 {
114 #if defined(CONFIG_TEGRA_FPGA_PLATFORM) || NEVER_RESET
115         printk("tegra_assert_system_reset() ignored.....");
116         do { } while (1);
117 #else
118         void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0x00);
119         u32 reg;
120
121         reg = readl_relaxed(reset + PMC_SCRATCH0);
122         /* Writing recovery kernel or Bootloader mode in SCRATCH0 31:30:1 */
123         if (cmd) {
124                 if (!strcmp(cmd, "recovery"))
125                         reg |= RECOVERY_MODE;
126                 else if (!strcmp(cmd, "bootloader"))
127                         reg |= BOOTLOADER_MODE;
128                 else if (!strcmp(cmd, "forced-recovery"))
129                         reg |= FORCED_RECOVERY_MODE;
130                 else
131                         reg &= ~(BOOTLOADER_MODE | RECOVERY_MODE | FORCED_RECOVERY_MODE);
132         }
133         else {
134                 /* Clearing SCRATCH0 31:30:1 on default reboot */
135                 reg &= ~(BOOTLOADER_MODE | RECOVERY_MODE | FORCED_RECOVERY_MODE);
136         }
137         writel_relaxed(reg, reset + PMC_SCRATCH0);
138         /* use *_related to avoid spinlock since caches are off */
139         reg = readl_relaxed(reset);
140         reg |= 0x10;
141         writel_relaxed(reg, reset);
142 #endif
143 }
144 static int modem_id;
145 static int commchip_id;
146 static int sku_override;
147 static int debug_uart_port_id;
148 static enum audio_codec_type audio_codec_name;
149 static enum image_type board_image_type = system_image;
150 static int max_cpu_current;
151
152 /* WARNING: There is implicit client of pllp_out3 like i2c, uart, dsi
153  * and so this clock (pllp_out3) should never be disabled.
154  */
155 static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
156         /* name         parent          rate            enabled */
157         { "clk_m",      NULL,           0,              true },
158         { "emc",        NULL,           0,              true },
159         { "cpu",        NULL,           0,              true },
160         { "kfuse",      NULL,           0,              true },
161         { "fuse",       NULL,           0,              true },
162         { "sclk",       NULL,           0,              true },
163 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
164 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
165         { "pll_p",      NULL,           216000000,      true },
166         { "pll_p_out1", "pll_p",        28800000,       true },
167         { "pll_p_out2", "pll_p",        48000000,       false },
168         { "pll_p_out3", "pll_p",        72000000,       true },
169         { "pll_p_out4", "pll_p",        108000000,      false },
170         { "pll_m",      "clk_m",        0,              true },
171         { "pll_m_out1", "pll_m",        120000000,      true },
172         { "sclk",       "pll_c_out1",   40000000,       true },
173         { "hclk",       "sclk",         40000000,       true },
174         { "pclk",       "hclk",         40000000,       true },
175         { "mpe",        "pll_c",        0,              false },
176         { "epp",        "pll_c",        0,              false },
177         { "vi_sensor",  "pll_c",        0,              false },
178         { "vi",         "pll_c",        0,              false },
179         { "2d",         "pll_c",        0,              false },
180         { "3d",         "pll_c",        0,              false },
181 #else
182         { "pll_p",      NULL,           0,              true },
183         { "pll_p_out1", "pll_p",        0,              false },
184         { "pll_p_out2", "pll_p",        48000000,       false },
185         { "pll_p_out3", "pll_p",        0,              true },
186         { "pll_m_out1", "pll_m",        275000000,      false },
187         { "pll_p_out4", "pll_p",        102000000,      true },
188         { "sclk",       "pll_p_out4",   102000000,      true },
189         { "hclk",       "sclk",         102000000,      true },
190         { "pclk",       "hclk",         51000000,       true },
191 #endif
192 #else
193         { "pll_p",      NULL,           216000000,      true },
194         { "pll_p_out1", "pll_p",        28800000,       false },
195         { "pll_p_out2", "pll_p",        48000000,       false },
196         { "pll_p_out3", "pll_p",        72000000,       true },
197         { "pll_m_out1", "pll_m",        275000000,      true },
198         { "pll_p_out4", "pll_p",        108000000,      false },
199         { "sclk",       "pll_p_out4",   108000000,      true },
200         { "hclk",       "sclk",         108000000,      true },
201         { "pclk",       "hclk",         54000000,       true },
202 #endif
203 #ifdef CONFIG_TEGRA_SLOW_CSITE
204         { "csite",      "clk_m",        1000000,        true },
205 #else
206         { "csite",      NULL,           0,              true },
207 #endif
208         { "pll_u",      NULL,           480000000,      false },
209         { "sdmmc1",     "pll_p",        48000000,       false},
210         { "sdmmc3",     "pll_p",        48000000,       false},
211         { "sdmmc4",     "pll_p",        48000000,       false},
212         { "sbc1.sclk",  NULL,           40000000,       false},
213         { "sbc2.sclk",  NULL,           40000000,       false},
214         { "sbc3.sclk",  NULL,           40000000,       false},
215         { "sbc4.sclk",  NULL,           40000000,       false},
216 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
217         { "sbc5.sclk",  NULL,           40000000,       false},
218         { "sbc6.sclk",  NULL,           40000000,       false},
219         { "wake.sclk",  NULL,           40000000,       true },
220         { "cbus",       "pll_c",        416000000,      false },
221         { "pll_c_out1", "pll_c",        208000000,      false },
222         { "mselect",    "pll_p",        102000000,      true },
223 #endif
224         { NULL,         NULL,           0,              0},
225 };
226
227 #ifdef CONFIG_CACHE_L2X0
228 #ifdef CONFIG_TRUSTED_FOUNDATIONS
229 static void tegra_cache_smc(bool enable, u32 arg)
230 {
231         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
232         bool need_affinity_switch;
233         bool can_switch_affinity;
234         bool l2x0_enabled;
235         cpumask_t local_cpu_mask;
236         cpumask_t saved_cpu_mask;
237         unsigned long flags;
238         long ret;
239
240         /*
241          * ISSUE : Some registers of PL310 controler must be written
242          *              from Secure context (and from CPU0)!
243          *
244          * When called form Normal we obtain an abort or do nothing.
245          * Instructions that must be called in Secure:
246          *      - Write to Control register (L2X0_CTRL==0x100)
247          *      - Write in Auxiliary controler (L2X0_AUX_CTRL==0x104)
248          *      - Invalidate all entries (L2X0_INV_WAY==0x77C),
249          *              mandatory at boot time.
250          *      - Tag and Data RAM Latency Control Registers
251          *              (0x108 & 0x10C) must be written in Secure.
252          */
253         need_affinity_switch = (smp_processor_id() != 0);
254         can_switch_affinity = !irqs_disabled();
255
256         WARN_ON(need_affinity_switch && !can_switch_affinity);
257         if (need_affinity_switch && can_switch_affinity) {
258                 cpu_set(0, local_cpu_mask);
259                 sched_getaffinity(0, &saved_cpu_mask);
260                 ret = sched_setaffinity(0, &local_cpu_mask);
261                 WARN_ON(ret != 0);
262         }
263
264         local_irq_save(flags);
265         l2x0_enabled = readl_relaxed(p + L2X0_CTRL) & 1;
266         if (enable && !l2x0_enabled)
267                 tegra_generic_smc(0xFFFFF100, 0x00000001, arg);
268         else if (!enable && l2x0_enabled)
269                 tegra_generic_smc(0xFFFFF100, 0x00000002, arg);
270         local_irq_restore(flags);
271
272         if (need_affinity_switch && can_switch_affinity) {
273                 ret = sched_setaffinity(0, &saved_cpu_mask);
274                 WARN_ON(ret != 0);
275         }
276 }
277
278 static void tegra_l2x0_disable(void)
279 {
280         unsigned long flags;
281         static u32 l2x0_way_mask;
282
283         if (!l2x0_way_mask) {
284                 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
285                 u32 aux_ctrl;
286                 u32 ways;
287
288                 aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
289                 ways = (aux_ctrl & (1 << 16)) ? 16 : 8;
290                 l2x0_way_mask = (1 << ways) - 1;
291         }
292
293         local_irq_save(flags);
294         tegra_cache_smc(false, l2x0_way_mask);
295         local_irq_restore(flags);
296 }
297 #endif  /* CONFIG_TRUSTED_FOUNDATIONS  */
298
299 void tegra_init_cache(bool init)
300 {
301         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
302         u32 aux_ctrl;
303
304 #ifdef CONFIG_TRUSTED_FOUNDATIONS
305         /* issue the SMC to enable the L2 */
306         aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
307         tegra_cache_smc(true, aux_ctrl);
308
309         /* after init, reread aux_ctrl and register handlers */
310         aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
311         l2x0_init(p, aux_ctrl, 0xFFFFFFFF);
312
313         /* override outer_disable() with our disable */
314         outer_cache.disable = tegra_l2x0_disable;
315 #else
316 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
317         writel_relaxed(0x331, p + L2X0_TAG_LATENCY_CTRL);
318         writel_relaxed(0x441, p + L2X0_DATA_LATENCY_CTRL);
319
320 #elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
321 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
322         /* PL310 RAM latency is CPU dependent. NOTE: Changes here
323            must also be reflected in __cortex_a9_l2x0_restart */
324
325         if (is_lp_cluster()) {
326                 writel(0x221, p + L2X0_TAG_LATENCY_CTRL);
327                 writel(0x221, p + L2X0_DATA_LATENCY_CTRL);
328         } else {
329                 u32 speedo;
330
331                 /* relax l2-cache latency for speedos 4,5,6 (T33's chips) */
332                 speedo = tegra_cpu_speedo_id();
333                 if (speedo == 4 || speedo == 5 || speedo == 6 ||
334                     speedo == 12 || speedo == 13) {
335                         writel(0x442, p + L2X0_TAG_LATENCY_CTRL);
336                         writel(0x552, p + L2X0_DATA_LATENCY_CTRL);
337                 } else {
338                         writel(0x441, p + L2X0_TAG_LATENCY_CTRL);
339                         writel(0x551, p + L2X0_DATA_LATENCY_CTRL);
340                 }
341         }
342 #else
343         writel(0x770, p + L2X0_TAG_LATENCY_CTRL);
344         writel(0x770, p + L2X0_DATA_LATENCY_CTRL);
345 #endif
346 #endif
347         writel(0x3, p + L2X0_POWER_CTRL);
348         aux_ctrl = readl(p + L2X0_CACHE_TYPE);
349         aux_ctrl = (aux_ctrl & 0x700) << (17-8);
350         aux_ctrl |= 0x7C000001;
351         if (init) {
352                 l2x0_init(p, aux_ctrl, 0x8200c3fe);
353         } else {
354                 u32 tmp;
355
356                 tmp = aux_ctrl;
357                 aux_ctrl = readl(p + L2X0_AUX_CTRL);
358                 aux_ctrl &= 0x8200c3fe;
359                 aux_ctrl |= tmp;
360                 writel(aux_ctrl, p + L2X0_AUX_CTRL);
361         }
362         l2x0_enable();
363 #endif
364 }
365 #endif
366
367 static void __init tegra_init_power(void)
368 {
369 #ifdef CONFIG_ARCH_TEGRA_HAS_SATA
370         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_SATA);
371 #endif
372 #ifdef CONFIG_ARCH_TEGRA_HAS_PCIE
373         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_PCIE);
374 #endif
375 }
376
377 static inline unsigned long gizmo_readl(unsigned long offset)
378 {
379         return readl(IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
380 }
381
382 static inline void gizmo_writel(unsigned long value, unsigned long offset)
383 {
384         writel(value, IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
385 }
386
387 static void __init tegra_init_ahb_gizmo_settings(void)
388 {
389         unsigned long val;
390
391         val = gizmo_readl(AHB_GIZMO_AHB_MEM);
392         val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR;
393         gizmo_writel(val, AHB_GIZMO_AHB_MEM);
394
395         val = gizmo_readl(AHB_GIZMO_USB);
396         val |= IMMEDIATE;
397         gizmo_writel(val, AHB_GIZMO_USB);
398
399         val = gizmo_readl(AHB_GIZMO_USB2);
400         val |= IMMEDIATE;
401         gizmo_writel(val, AHB_GIZMO_USB2);
402
403         val = gizmo_readl(AHB_GIZMO_USB3);
404         val |= IMMEDIATE;
405         gizmo_writel(val, AHB_GIZMO_USB3);
406
407         val = gizmo_readl(AHB_ARBITRATION_PRIORITY_CTRL);
408         val |= PRIORITY_SELECT_USB | PRIORITY_SELECT_USB2 | PRIORITY_SELECT_USB3
409                                 | AHB_PRIORITY_WEIGHT(7);
410         gizmo_writel(val, AHB_ARBITRATION_PRIORITY_CTRL);
411
412         val = gizmo_readl(AHB_MEM_PREFETCH_CFG1);
413         val &= ~MST_ID(~0);
414         val |= PREFETCH_ENB | AHBDMA_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
415         gizmo_writel(val, AHB_MEM_PREFETCH_CFG1);
416
417         val = gizmo_readl(AHB_MEM_PREFETCH_CFG2);
418         val &= ~MST_ID(~0);
419         val |= PREFETCH_ENB | USB_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
420         gizmo_writel(val, AHB_MEM_PREFETCH_CFG2);
421
422         val = gizmo_readl(AHB_MEM_PREFETCH_CFG3);
423         val &= ~MST_ID(~0);
424         val |= PREFETCH_ENB | USB3_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
425         gizmo_writel(val, AHB_MEM_PREFETCH_CFG3);
426
427         val = gizmo_readl(AHB_MEM_PREFETCH_CFG4);
428         val &= ~MST_ID(~0);
429         val |= PREFETCH_ENB | USB2_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
430         gizmo_writel(val, AHB_MEM_PREFETCH_CFG4);
431 }
432
433 void __init tegra_init_early(void)
434 {
435 #ifndef CONFIG_SMP
436         /* For SMP system, initializing the reset handler here is too
437            late. For non-SMP systems, the function that calls the reset
438            handler initializer is not called, so do it here for non-SMP. */
439         tegra_cpu_reset_handler_init();
440 #endif
441         tegra_init_fuse();
442         tegra_gpio_resume_init();
443         tegra_init_clock();
444         tegra_init_pinmux();
445         tegra_clk_init_from_table(common_clk_init_table);
446         tegra_init_power();
447         tegra_init_cache(true);
448         tegra_init_ahb_gizmo_settings();
449         tegra_init_debug_uart_rate();
450 }
451
452 static int __init tegra_lp0_vec_arg(char *options)
453 {
454         char *p = options;
455
456         tegra_lp0_vec_size = memparse(p, &p);
457         if (*p == '@')
458                 tegra_lp0_vec_start = memparse(p+1, &p);
459         if (!tegra_lp0_vec_size || !tegra_lp0_vec_start) {
460                 tegra_lp0_vec_size = 0;
461                 tegra_lp0_vec_start = 0;
462         }
463
464         return 0;
465 }
466 early_param("lp0_vec", tegra_lp0_vec_arg);
467
468 static int __init tegra_bootloader_fb_arg(char *options)
469 {
470         char *p = options;
471
472         tegra_bootloader_fb_size = memparse(p, &p);
473         if (*p == '@')
474                 tegra_bootloader_fb_start = memparse(p+1, &p);
475
476         pr_info("Found tegra_fbmem: %08lx@%08lx\n",
477                 tegra_bootloader_fb_size, tegra_bootloader_fb_start);
478
479         return 0;
480 }
481 early_param("tegra_fbmem", tegra_bootloader_fb_arg);
482
483 static int __init tegra_sku_override(char *id)
484 {
485         char *p = id;
486
487         sku_override = memparse(p, &p);
488
489         return 0;
490 }
491 early_param("sku_override", tegra_sku_override);
492
493 int tegra_get_sku_override(void)
494 {
495         return sku_override;
496 }
497
498 static int __init tegra_vpr_arg(char *options)
499 {
500         char *p = options;
501
502         tegra_vpr_size = memparse(p, &p);
503         if (*p == '@')
504                 tegra_vpr_start = memparse(p+1, &p);
505         pr_info("Found vpr, start=0x%lx size=%lx",
506                 tegra_vpr_start, tegra_vpr_size);
507         return 0;
508 }
509 early_param("vpr", tegra_vpr_arg);
510
511 enum panel_type get_panel_type(void)
512 {
513         return board_panel_type;
514 }
515 static int __init tegra_board_panel_type(char *options)
516 {
517         if (!strcmp(options, "lvds"))
518                 board_panel_type = panel_type_lvds;
519         else if (!strcmp(options, "dsi"))
520                 board_panel_type = panel_type_dsi;
521         else
522                 return 0;
523         return 1;
524 }
525 __setup("panel=", tegra_board_panel_type);
526
527 enum power_supply_type get_power_supply_type(void)
528 {
529         return pow_supply_type;
530 }
531 static int __init tegra_board_power_supply_type(char *options)
532 {
533         if (!strcmp(options, "Adapter"))
534                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
535         if (!strcmp(options, "Mains"))
536                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
537         else if (!strcmp(options, "Battery"))
538                 pow_supply_type = POWER_SUPPLY_TYPE_BATTERY;
539         else
540                 return 0;
541         return 1;
542 }
543 __setup("power_supply=", tegra_board_power_supply_type);
544
545 int get_core_edp(void)
546 {
547         return pmu_core_edp;
548 }
549 static int __init tegra_pmu_core_edp(char *options)
550 {
551         char *p = options;
552         int core_edp = memparse(p, &p);
553         if (core_edp != 0)
554                 pmu_core_edp = core_edp;
555         return 0;
556 }
557 early_param("core_edp_mv", tegra_pmu_core_edp);
558
559 int get_maximum_cpu_current_supported(void)
560 {
561         return max_cpu_current;
562 }
563 static int __init tegra_max_cpu_current(char *options)
564 {
565         char *p = options;
566         max_cpu_current = memparse(p, &p);
567         return 1;
568 }
569 __setup("max_cpu_cur_ma=", tegra_max_cpu_current);
570
571 static int __init tegra_debug_uartport(char *info)
572 {
573         char *p = info;
574         unsigned long long port_id;
575         if (!strncmp(p, "hsport", 6))
576                 is_tegra_debug_uart_hsport = true;
577         else if (!strncmp(p, "lsport", 6))
578                 is_tegra_debug_uart_hsport = false;
579
580         if (p[6] == ',') {
581                 if (p[7] == '-') {
582                         debug_uart_port_id = -1;
583                 } else {
584                         port_id = memparse(p + 7, &p);
585                         debug_uart_port_id = (int) port_id;
586                 }
587         } else {
588                 debug_uart_port_id = -1;
589         }
590
591         return 1;
592 }
593
594 bool is_tegra_debug_uartport_hs(void)
595 {
596         return is_tegra_debug_uart_hsport;
597 }
598
599 int get_tegra_uart_debug_port_id(void)
600 {
601         return debug_uart_port_id;
602 }
603 __setup("debug_uartport=", tegra_debug_uartport);
604
605 static int __init tegra_image_type(char *options)
606 {
607         if (!strcmp(options, "RCK"))
608                 board_image_type = rck_image;
609
610         return 0;
611 }
612
613 enum image_type get_tegra_image_type(void)
614 {
615         return board_image_type;
616 }
617
618 __setup("image=", tegra_image_type);
619
620 static int __init tegra_audio_codec_type(char *info)
621 {
622         char *p = info;
623         if (!strncmp(p, "wm8903", 6))
624                 audio_codec_name = audio_codec_wm8903;
625         else
626                 audio_codec_name = audio_codec_none;
627
628         return 1;
629 }
630
631 enum audio_codec_type get_audio_codec_type(void)
632 {
633         return audio_codec_name;
634 }
635 __setup("audio_codec=", tegra_audio_codec_type);
636
637
638 void tegra_get_board_info(struct board_info *bi)
639 {
640         bi->board_id = (system_serial_high >> 16) & 0xFFFF;
641         bi->sku = (system_serial_high) & 0xFFFF;
642         bi->fab = (system_serial_low >> 24) & 0xFF;
643         bi->major_revision = (system_serial_low >> 16) & 0xFF;
644         bi->minor_revision = (system_serial_low >> 8) & 0xFF;
645 }
646
647 static int __init tegra_pmu_board_info(char *info)
648 {
649         char *p = info;
650         pmu_board_info.board_id = memparse(p, &p);
651         pmu_board_info.sku = memparse(p+1, &p);
652         pmu_board_info.fab = memparse(p+1, &p);
653         pmu_board_info.major_revision = memparse(p+1, &p);
654         pmu_board_info.minor_revision = memparse(p+1, &p);
655         return 1;
656 }
657
658 void tegra_get_pmu_board_info(struct board_info *bi)
659 {
660         memcpy(bi, &pmu_board_info, sizeof(struct board_info));
661 }
662
663 __setup("pmuboard=", tegra_pmu_board_info);
664
665 static int __init tegra_display_board_info(char *info)
666 {
667         char *p = info;
668         display_board_info.board_id = memparse(p, &p);
669         display_board_info.sku = memparse(p+1, &p);
670         display_board_info.fab = memparse(p+1, &p);
671         display_board_info.major_revision = memparse(p+1, &p);
672         display_board_info.minor_revision = memparse(p+1, &p);
673         return 1;
674 }
675
676 void tegra_get_display_board_info(struct board_info *bi)
677 {
678         memcpy(bi, &display_board_info, sizeof(struct board_info));
679 }
680
681 __setup("displayboard=", tegra_display_board_info);
682
683 static int __init tegra_camera_board_info(char *info)
684 {
685         char *p = info;
686         camera_board_info.board_id = memparse(p, &p);
687         camera_board_info.sku = memparse(p+1, &p);
688         camera_board_info.fab = memparse(p+1, &p);
689         camera_board_info.major_revision = memparse(p+1, &p);
690         camera_board_info.minor_revision = memparse(p+1, &p);
691         return 1;
692 }
693
694 void tegra_get_camera_board_info(struct board_info *bi)
695 {
696         memcpy(bi, &camera_board_info, sizeof(struct board_info));
697 }
698
699 __setup("cameraboard=", tegra_camera_board_info);
700
701 static int __init tegra_modem_id(char *id)
702 {
703         char *p = id;
704
705         modem_id = memparse(p, &p);
706         return 1;
707 }
708
709 int tegra_get_modem_id(void)
710 {
711         return modem_id;
712 }
713
714 __setup("modem_id=", tegra_modem_id);
715
716 static int __init tegra_commchip_id(char *id)
717 {
718         char *p = id;
719
720         if (get_option(&p, &commchip_id) != 1)
721                 return 0;
722         return 1;
723 }
724
725 int tegra_get_commchip_id(void)
726 {
727         return commchip_id;
728 }
729
730 __setup("commchip_id=", tegra_commchip_id);
731
732 /*
733  * Tegra has a protected aperture that prevents access by most non-CPU
734  * memory masters to addresses above the aperture value.  Enabling it
735  * secures the CPU's memory from the GPU, except through the GART.
736  */
737 void __init tegra_protected_aperture_init(unsigned long aperture)
738 {
739 #ifndef CONFIG_NVMAP_ALLOW_SYSMEM
740         void __iomem *mc_base = IO_ADDRESS(TEGRA_MC_BASE);
741         pr_info("Enabling Tegra protected aperture at 0x%08lx\n", aperture);
742         writel(aperture, mc_base + MC_SECURITY_CFG2);
743 #else
744         pr_err("Tegra protected aperture disabled because nvmap is using "
745                 "system memory\n");
746 #endif
747 }
748
749 /*
750  * Due to conflicting restrictions on the placement of the framebuffer,
751  * the bootloader is likely to leave the framebuffer pointed at a location
752  * in memory that is outside the grhost aperture.  This function will move
753  * the framebuffer contents from a physical address that is anywher (lowmem,
754  * highmem, or outside the memory map) to a physical address that is outside
755  * the memory map.
756  */
757 void tegra_move_framebuffer(unsigned long to, unsigned long from,
758         unsigned long size)
759 {
760         struct page *page;
761         void __iomem *to_io;
762         void *from_virt;
763         unsigned long i;
764
765         BUG_ON(PAGE_ALIGN((unsigned long)to) != (unsigned long)to);
766         BUG_ON(PAGE_ALIGN(from) != from);
767         BUG_ON(PAGE_ALIGN(size) != size);
768
769         to_io = ioremap(to, size);
770         if (!to_io) {
771                 pr_err("%s: Failed to map target framebuffer\n", __func__);
772                 return;
773         }
774
775         if (pfn_valid(page_to_pfn(phys_to_page(from)))) {
776                 for (i = 0 ; i < size; i += PAGE_SIZE) {
777                         page = phys_to_page(from + i);
778                         from_virt = kmap(page);
779                         memcpy(to_io + i, from_virt, PAGE_SIZE);
780                         kunmap(page);
781                 }
782         } else {
783                 void __iomem *from_io = ioremap(from, size);
784                 if (!from_io) {
785                         pr_err("%s: Failed to map source framebuffer\n",
786                                 __func__);
787                         goto out;
788                 }
789
790                 for (i = 0; i < size; i += 4)
791                         writel(readl(from_io + i), to_io + i);
792
793                 iounmap(from_io);
794         }
795 out:
796         iounmap(to_io);
797 }
798
799 void __init tegra_reserve(unsigned long carveout_size, unsigned long fb_size,
800         unsigned long fb2_size)
801 {
802         if (carveout_size) {
803                 tegra_carveout_start = memblock_end_of_DRAM() - carveout_size;
804                 if (memblock_remove(tegra_carveout_start, carveout_size)) {
805                         pr_err("Failed to remove carveout %08lx@%08lx "
806                                 "from memory map\n",
807                                 carveout_size, tegra_carveout_start);
808                         tegra_carveout_start = 0;
809                         tegra_carveout_size = 0;
810                 } else
811                         tegra_carveout_size = carveout_size;
812         }
813
814         if (fb2_size) {
815                 tegra_fb2_start = memblock_end_of_DRAM() - fb2_size;
816                 if (memblock_remove(tegra_fb2_start, fb2_size)) {
817                         pr_err("Failed to remove second framebuffer "
818                                 "%08lx@%08lx from memory map\n",
819                                 fb2_size, tegra_fb2_start);
820                         tegra_fb2_start = 0;
821                         tegra_fb2_size = 0;
822                 } else
823                         tegra_fb2_size = fb2_size;
824         }
825
826         if (fb_size) {
827                 tegra_fb_start = memblock_end_of_DRAM() - fb_size;
828                 if (memblock_remove(tegra_fb_start, fb_size)) {
829                         pr_err("Failed to remove framebuffer %08lx@%08lx "
830                                 "from memory map\n",
831                                 fb_size, tegra_fb_start);
832                         tegra_fb_start = 0;
833                         tegra_fb_size = 0;
834                 } else
835                         tegra_fb_size = fb_size;
836         }
837
838         if (tegra_fb_size)
839                 tegra_grhost_aperture = tegra_fb_start;
840
841         if (tegra_fb2_size && tegra_fb2_start < tegra_grhost_aperture)
842                 tegra_grhost_aperture = tegra_fb2_start;
843
844         if (tegra_carveout_size && tegra_carveout_start < tegra_grhost_aperture)
845                 tegra_grhost_aperture = tegra_carveout_start;
846
847         if (tegra_lp0_vec_size &&
848            (tegra_lp0_vec_start < memblock_end_of_DRAM())) {
849                 if (memblock_reserve(tegra_lp0_vec_start, tegra_lp0_vec_size)) {
850                         pr_err("Failed to reserve lp0_vec %08lx@%08lx\n",
851                                 tegra_lp0_vec_size, tegra_lp0_vec_start);
852                         tegra_lp0_vec_start = 0;
853                         tegra_lp0_vec_size = 0;
854                 }
855                 tegra_lp0_vec_relocate = false;
856         } else
857                 tegra_lp0_vec_relocate = true;
858
859         /*
860          * We copy the bootloader's framebuffer to the framebuffer allocated
861          * above, and then free this one.
862          * */
863         if (tegra_bootloader_fb_size) {
864                 tegra_bootloader_fb_size = PAGE_ALIGN(tegra_bootloader_fb_size);
865                 if (memblock_reserve(tegra_bootloader_fb_start,
866                                 tegra_bootloader_fb_size)) {
867                         pr_err("Failed to reserve bootloader frame buffer "
868                                 "%08lx@%08lx\n", tegra_bootloader_fb_size,
869                                 tegra_bootloader_fb_start);
870                         tegra_bootloader_fb_start = 0;
871                         tegra_bootloader_fb_size = 0;
872                 }
873         }
874
875         pr_info("Tegra reserved memory:\n"
876                 "LP0:                    %08lx - %08lx\n"
877                 "Bootloader framebuffer: %08lx - %08lx\n"
878                 "Framebuffer:            %08lx - %08lx\n"
879                 "2nd Framebuffer:        %08lx - %08lx\n"
880                 "Carveout:               %08lx - %08lx\n"
881                 "Vpr:                    %08lx - %08lx\n",
882                 tegra_lp0_vec_start,
883                 tegra_lp0_vec_size ?
884                         tegra_lp0_vec_start + tegra_lp0_vec_size - 1 : 0,
885                 tegra_bootloader_fb_start,
886                 tegra_bootloader_fb_size ?
887                         tegra_bootloader_fb_start + tegra_bootloader_fb_size - 1 : 0,
888                 tegra_fb_start,
889                 tegra_fb_size ?
890                         tegra_fb_start + tegra_fb_size - 1 : 0,
891                 tegra_fb2_start,
892                 tegra_fb2_size ?
893                         tegra_fb2_start + tegra_fb2_size - 1 : 0,
894                 tegra_carveout_start,
895                 tegra_carveout_size ?
896                         tegra_carveout_start + tegra_carveout_size - 1 : 0,
897                 tegra_vpr_start,
898                 tegra_vpr_size ?
899                         tegra_vpr_start + tegra_vpr_size - 1 : 0);
900 }
901
902 static struct resource ram_console_resources[] = {
903         {
904                 .flags = IORESOURCE_MEM,
905         },
906 };
907
908 static struct platform_device ram_console_device = {
909         .name           = "ram_console",
910         .id             = -1,
911         .num_resources  = ARRAY_SIZE(ram_console_resources),
912         .resource       = ram_console_resources,
913 };
914
915 void __init tegra_ram_console_debug_reserve(unsigned long ram_console_size)
916 {
917         struct resource *res;
918         long ret;
919
920         res = platform_get_resource(&ram_console_device, IORESOURCE_MEM, 0);
921         if (!res)
922                 goto fail;
923         res->start = memblock_end_of_DRAM() - ram_console_size;
924         res->end = res->start + ram_console_size - 1;
925         ret = memblock_remove(res->start, ram_console_size);
926         if (ret)
927                 goto fail;
928
929         return;
930
931 fail:
932         ram_console_device.resource = NULL;
933         ram_console_device.num_resources = 0;
934         pr_err("Failed to reserve memory block for ram console\n");
935 }
936
937 void __init tegra_ram_console_debug_init(void)
938 {
939         int err;
940
941         err = platform_device_register(&ram_console_device);
942         if (err) {
943                 pr_err("%s: ram console registration failed (%d)!\n", __func__, err);
944         }
945 }
946
947 void __init tegra_release_bootloader_fb(void)
948 {
949         /* Since bootloader fb is reserved in common.c, it is freed here. */
950         if (tegra_bootloader_fb_size)
951                 if (memblock_free(tegra_bootloader_fb_start,
952                                                 tegra_bootloader_fb_size))
953                         pr_err("Failed to free bootloader fb.\n");
954 }
955
956 #ifdef CONFIG_TEGRA_CONVSERVATIVE_GOV_ON_EARLYSUPSEND
957 char cpufreq_default_gov[CONFIG_NR_CPUS][MAX_GOV_NAME_LEN];
958 char *cpufreq_conservative_gov = "conservative";
959
960 void cpufreq_store_default_gov(void)
961 {
962         unsigned int cpu = 0;
963         struct cpufreq_policy *policy;
964
965 #ifndef CONFIG_TEGRA_AUTO_HOTPLUG
966         for_each_online_cpu(cpu)
967 #endif
968         {
969                 policy = cpufreq_cpu_get(cpu);
970                 if (policy && policy->governor) {
971                         sprintf(cpufreq_default_gov[cpu], "%s",
972                                         policy->governor->name);
973                         cpufreq_cpu_put(policy);
974                 } else {
975                         /* No policy or no gov set for this
976                          * online cpu. If we are here, require
977                          * serious debugging hence setting
978                          * as pr_error.
979                          */
980                         pr_err("No gov or No policy for online cpu:%d,"
981                                         , cpu);
982                 }
983         }
984 }
985
986 void cpufreq_change_gov(char *target_gov)
987 {
988         int ret = -EINVAL;
989         unsigned int cpu = 0;
990
991 #ifndef CONFIG_TEGRA_AUTO_HOTPLUG
992         for_each_online_cpu(cpu)
993 #endif
994         {
995                 ret = cpufreq_set_gov(target_gov, cpu);
996                 if (ret < 0)
997                         /* Unable to set gov for the online cpu.
998                          * If it happens, needs to debug.
999                          */
1000                         pr_info("Unable to set gov:%s for online cpu:%d,"
1001                                 , cpufreq_default_gov[cpu]
1002                                         , cpu);
1003         }
1004 }
1005
1006 void cpufreq_restore_default_gov(void)
1007 {
1008         int ret = -EINVAL;
1009         unsigned int cpu = 0;
1010
1011 #ifndef CONFIG_TEGRA_AUTO_HOTPLUG
1012         for_each_online_cpu(cpu)
1013 #endif
1014         {
1015                 if (&cpufreq_default_gov[cpu] &&
1016                         strlen((const char *)&cpufreq_default_gov[cpu])) {
1017                         ret = cpufreq_set_gov(cpufreq_default_gov[cpu], cpu);
1018                         if (ret < 0)
1019                                 /* Unable to restore gov for the cpu as
1020                                  * It was online on suspend and becomes
1021                                  * offline on resume.
1022                                  */
1023                                 pr_info("Unable to restore gov:%s for cpu:%d,"
1024                                                 , cpufreq_default_gov[cpu]
1025                                                         , cpu);
1026                 }
1027                 cpufreq_default_gov[cpu][0] = '\0';
1028         }
1029 }
1030 #endif /* CONFIG_TEGRA_CONVSERVATIVE_GOV_ON_EARLYSUPSEND */