arm: tegra: display: provide framebuffer clear function
[linux-2.6.git] / arch / arm / mach-tegra / common.c
1 /*
2  * arch/arm/mach-tegra/common.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Copyright (C) 2010-2012, NVIDIA Corporation. All rights reserved.
6  *
7  * Author:
8  *      Colin Cross <ccross@android.com>
9  *
10  * This software is licensed under the terms of the GNU General Public
11  * License version 2, as published by the Free Software Foundation, and
12  * may be copied, distributed, and modified under those terms.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  */
20
21 #include <linux/platform_device.h>
22 #include <linux/console.h>
23 #include <linux/init.h>
24 #include <linux/io.h>
25 #include <linux/clk.h>
26 #include <linux/delay.h>
27 #include <linux/highmem.h>
28 #include <linux/memblock.h>
29 #include <linux/bitops.h>
30 #include <linux/sched.h>
31 #include <linux/cpufreq.h>
32 #include <linux/of.h>
33
34 #include <asm/hardware/cache-l2x0.h>
35 #include <asm/system.h>
36
37 #include <mach/gpio.h>
38 #include <mach/iomap.h>
39 #include <mach/pinmux.h>
40 #include <mach/powergate.h>
41 #include <mach/system.h>
42 #include <mach/tegra_smmu.h>
43
44 #include "apbio.h"
45 #include "board.h"
46 #include "clock.h"
47 #include "fuse.h"
48 #include "pm.h"
49 #include "reset.h"
50 #include "devices.h"
51
52 #define MC_SECURITY_CFG2        0x7c
53
54 #define AHB_ARBITRATION_PRIORITY_CTRL           0x4
55 #define   AHB_PRIORITY_WEIGHT(x)        (((x) & 0x7) << 29)
56 #define   PRIORITY_SELECT_USB   BIT(6)
57 #define   PRIORITY_SELECT_USB2  BIT(18)
58 #define   PRIORITY_SELECT_USB3  BIT(17)
59
60 #define AHB_GIZMO_AHB_MEM               0xc
61 #define   ENB_FAST_REARBITRATE  BIT(2)
62 #define   DONT_SPLIT_AHB_WR     BIT(7)
63
64 #define   RECOVERY_MODE BIT(31)
65 #define   BOOTLOADER_MODE       BIT(30)
66 #define   FORCED_RECOVERY_MODE  BIT(1)
67
68 #define AHB_GIZMO_USB           0x1c
69 #define AHB_GIZMO_USB2          0x78
70 #define AHB_GIZMO_USB3          0x7c
71 #define   IMMEDIATE     BIT(18)
72
73 #define AHB_MEM_PREFETCH_CFG3   0xe0
74 #define AHB_MEM_PREFETCH_CFG4   0xe4
75 #define AHB_MEM_PREFETCH_CFG1   0xec
76 #define AHB_MEM_PREFETCH_CFG2   0xf0
77 #define   PREFETCH_ENB  BIT(31)
78 #define   MST_ID(x)     (((x) & 0x1f) << 26)
79 #define   AHBDMA_MST_ID MST_ID(5)
80 #define   USB_MST_ID    MST_ID(6)
81 #define   USB2_MST_ID   MST_ID(18)
82 #define   USB3_MST_ID   MST_ID(17)
83 #define   ADDR_BNDRY(x) (((x) & 0xf) << 21)
84 #define   INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0)
85
86 unsigned long tegra_bootloader_fb_start;
87 unsigned long tegra_bootloader_fb_size;
88 unsigned long tegra_fb_start;
89 unsigned long tegra_fb_size;
90 unsigned long tegra_fb2_start;
91 unsigned long tegra_fb2_size;
92 unsigned long tegra_carveout_start;
93 unsigned long tegra_carveout_size;
94 unsigned long tegra_vpr_start;
95 unsigned long tegra_vpr_size;
96 unsigned long tegra_lp0_vec_start;
97 unsigned long tegra_lp0_vec_size;
98 bool tegra_lp0_vec_relocate;
99 unsigned long tegra_grhost_aperture = ~0ul;
100 static   bool is_tegra_debug_uart_hsport;
101 static struct board_info pmu_board_info;
102 static struct board_info display_board_info;
103 static struct board_info camera_board_info;
104
105 static int pmu_core_edp = 1200; /* default 1.2V EDP limit */
106 static int board_panel_type;
107 static enum power_supply_type pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
108
109 void (*arch_reset)(char mode, const char *cmd) = tegra_assert_system_reset;
110
111 #define NEVER_RESET 0
112
113 void tegra_assert_system_reset(char mode, const char *cmd)
114 {
115 #if defined(CONFIG_TEGRA_FPGA_PLATFORM) || NEVER_RESET
116         printk("tegra_assert_system_reset() ignored.....");
117         do { } while (1);
118 #else
119         void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0x00);
120         u32 reg;
121
122         reg = readl_relaxed(reset + PMC_SCRATCH0);
123         /* Writing recovery kernel or Bootloader mode in SCRATCH0 31:30:1 */
124         if (cmd) {
125                 if (!strcmp(cmd, "recovery"))
126                         reg |= RECOVERY_MODE;
127                 else if (!strcmp(cmd, "bootloader"))
128                         reg |= BOOTLOADER_MODE;
129                 else if (!strcmp(cmd, "forced-recovery"))
130                         reg |= FORCED_RECOVERY_MODE;
131                 else
132                         reg &= ~(BOOTLOADER_MODE | RECOVERY_MODE | FORCED_RECOVERY_MODE);
133         }
134         else {
135                 /* Clearing SCRATCH0 31:30:1 on default reboot */
136                 reg &= ~(BOOTLOADER_MODE | RECOVERY_MODE | FORCED_RECOVERY_MODE);
137         }
138         writel_relaxed(reg, reset + PMC_SCRATCH0);
139         /* use *_related to avoid spinlock since caches are off */
140         reg = readl_relaxed(reset);
141         reg |= 0x10;
142         writel_relaxed(reg, reset);
143 #endif
144 }
145 static int modem_id;
146 static int commchip_id;
147 static int sku_override;
148 static int debug_uart_port_id;
149 static enum audio_codec_type audio_codec_name;
150 static enum image_type board_image_type = system_image;
151 static int max_cpu_current;
152
153 /* WARNING: There is implicit client of pllp_out3 like i2c, uart, dsi
154  * and so this clock (pllp_out3) should never be disabled.
155  */
156 static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
157         /* name         parent          rate            enabled */
158         { "clk_m",      NULL,           0,              true },
159         { "emc",        NULL,           0,              true },
160         { "cpu",        NULL,           0,              true },
161         { "kfuse",      NULL,           0,              true },
162         { "fuse",       NULL,           0,              true },
163         { "sclk",       NULL,           0,              true },
164 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
165 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
166         { "pll_p",      NULL,           216000000,      true },
167         { "pll_p_out1", "pll_p",        28800000,       true },
168         { "pll_p_out2", "pll_p",        48000000,       false },
169         { "pll_p_out3", "pll_p",        72000000,       true },
170         { "pll_p_out4", "pll_p",        108000000,      false },
171         { "pll_m",      "clk_m",        0,              true },
172         { "pll_m_out1", "pll_m",        120000000,      true },
173         { "sclk",       "pll_c_out1",   40000000,       true },
174         { "hclk",       "sclk",         40000000,       true },
175         { "pclk",       "hclk",         40000000,       true },
176         { "mpe",        "pll_c",        0,              false },
177         { "epp",        "pll_c",        0,              false },
178         { "vi_sensor",  "pll_c",        0,              false },
179         { "vi",         "pll_c",        0,              false },
180         { "2d",         "pll_c",        0,              false },
181         { "3d",         "pll_c",        0,              false },
182 #else
183         { "pll_p",      NULL,           0,              true },
184         { "pll_p_out1", "pll_p",        0,              false },
185         { "pll_p_out2", "pll_p",        48000000,       false },
186         { "pll_p_out3", "pll_p",        0,              true },
187         { "pll_m_out1", "pll_m",        275000000,      false },
188         { "pll_p_out4", "pll_p",        102000000,      true },
189         { "sclk",       "pll_p_out4",   102000000,      true },
190         { "hclk",       "sclk",         102000000,      true },
191         { "pclk",       "hclk",         51000000,       true },
192 #endif
193 #else
194         { "pll_p",      NULL,           216000000,      true },
195         { "pll_p_out1", "pll_p",        28800000,       false },
196         { "pll_p_out2", "pll_p",        48000000,       false },
197         { "pll_p_out3", "pll_p",        72000000,       true },
198         { "pll_m_out1", "pll_m",        275000000,      true },
199         { "pll_p_out4", "pll_p",        108000000,      false },
200         { "sclk",       "pll_p_out4",   108000000,      true },
201         { "hclk",       "sclk",         108000000,      true },
202         { "pclk",       "hclk",         54000000,       true },
203 #endif
204 #ifdef CONFIG_TEGRA_SLOW_CSITE
205         { "csite",      "clk_m",        1000000,        true },
206 #else
207         { "csite",      NULL,           0,              true },
208 #endif
209         { "pll_u",      NULL,           480000000,      false },
210         { "sdmmc1",     "pll_p",        48000000,       false},
211         { "sdmmc3",     "pll_p",        48000000,       false},
212         { "sdmmc4",     "pll_p",        48000000,       false},
213         { "sbc1.sclk",  NULL,           40000000,       false},
214         { "sbc2.sclk",  NULL,           40000000,       false},
215         { "sbc3.sclk",  NULL,           40000000,       false},
216         { "sbc4.sclk",  NULL,           40000000,       false},
217 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
218         { "sbc5.sclk",  NULL,           40000000,       false},
219         { "sbc6.sclk",  NULL,           40000000,       false},
220         { "wake.sclk",  NULL,           40000000,       true },
221         { "cpu_mode.sclk", NULL,        80000000,       false },
222         { "cbus",       "pll_c",        416000000,      false },
223         { "pll_c_out1", "pll_c",        208000000,      false },
224         { "mselect",    "pll_p",        102000000,      true },
225 #endif
226         { NULL,         NULL,           0,              0},
227 };
228
229 #ifdef CONFIG_TRUSTED_FOUNDATIONS
230 static inline void tegra_l2x0_disable_tz(void)
231 {
232         static u32 l2x0_way_mask;
233         BUG_ON(smp_processor_id() != 0);
234
235         if (!l2x0_way_mask) {
236                 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
237                 u32 aux_ctrl;
238                 u32 ways;
239
240                 aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
241                 ways = (aux_ctrl & (1 << 16)) ? 16 : 8;
242                 l2x0_way_mask = (1 << ways) - 1;
243         }
244 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
245         /* flush all ways on any disable */
246         tegra_generic_smc_uncached(0xFFFFF100, 0x00000002, l2x0_way_mask);
247 #elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
248         if (tegra_is_cpu_in_lp2(0) == false) {
249                 /*
250                  * If entering LP0/LP1, ask secureos to fully flush and
251                  * disable the L2.
252                  *
253                  * If entering LP2, L2 disable is handled by the secureos
254                  * as part of the tegra_sleep_cpu() SMC. This SMC indicates
255                  * no more secureos tasks will be scheduled, allowing it
256                  * to optimize out L2 flushes on its side.
257                  */
258                 tegra_generic_smc_uncached(0xFFFFF100,
259                                                 0x00000002, l2x0_way_mask);
260         }
261 #endif
262 }
263
264 static inline void tegra_init_cache_tz(bool init)
265 {
266         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
267         u32 aux_ctrl;
268
269         BUG_ON(smp_processor_id() != 0);
270
271         if (init) {
272                 /* init L2 from secureos */
273                 tegra_generic_smc(0xFFFFF100, 0x00000001, 0x0);
274
275                 /* common init called for outer call hookup */
276                 aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
277                 l2x0_init(p, aux_ctrl, 0xFFFFFFFF);
278
279                 /* use our outer_disable() routine */
280                 outer_cache.disable = tegra_l2x0_disable_tz;
281         } else {
282                 /* reenable L2 in secureos */
283                 aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
284                 tegra_generic_smc_uncached(0xFFFFF100, 0x00000004, aux_ctrl);
285         }
286 }
287 #endif  /* CONFIG_TRUSTED_FOUNDATIONS  */
288
289 #ifdef CONFIG_CACHE_L2X0
290 /*
291  * We define our own outer_disable() to avoid L2 flush upon LP2 entry.
292  * Since the Tegra kernel will always be in single core mode when
293  * L2 is being disabled, we can omit the locking. Since we are not
294  * accessing the spinlock we also avoid the problem of the spinlock
295  * storage getting out of sync.
296  */
297 static inline void tegra_l2x0_disable(void)
298 {
299         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
300         writel_relaxed(0, p + L2X0_CTRL);
301         dsb();
302 }
303
304 void tegra_init_cache(bool init)
305 {
306 #ifdef CONFIG_TRUSTED_FOUNDATIONS
307         /* enable/re-enable of L2 handled by secureos */
308         return tegra_init_cache_tz(init);
309 #else
310         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
311         u32 aux_ctrl;
312
313 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
314         writel_relaxed(0x331, p + L2X0_TAG_LATENCY_CTRL);
315         writel_relaxed(0x441, p + L2X0_DATA_LATENCY_CTRL);
316
317 #elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
318 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
319         /* PL310 RAM latency is CPU dependent. NOTE: Changes here
320            must also be reflected in __cortex_a9_l2x0_restart */
321
322         if (is_lp_cluster()) {
323                 writel(0x221, p + L2X0_TAG_LATENCY_CTRL);
324                 writel(0x221, p + L2X0_DATA_LATENCY_CTRL);
325         } else {
326                 u32 speedo;
327
328                 /* relax l2-cache latency for speedos 4,5,6 (T33's chips) */
329                 speedo = tegra_cpu_speedo_id();
330                 if (speedo == 4 || speedo == 5 || speedo == 6 ||
331                     speedo == 12 || speedo == 13) {
332                         writel(0x442, p + L2X0_TAG_LATENCY_CTRL);
333                         writel(0x552, p + L2X0_DATA_LATENCY_CTRL);
334                 } else {
335                         writel(0x441, p + L2X0_TAG_LATENCY_CTRL);
336                         writel(0x551, p + L2X0_DATA_LATENCY_CTRL);
337                 }
338         }
339 #else
340         writel(0x770, p + L2X0_TAG_LATENCY_CTRL);
341         writel(0x770, p + L2X0_DATA_LATENCY_CTRL);
342 #endif
343 #endif
344         writel(0x3, p + L2X0_POWER_CTRL);
345         aux_ctrl = readl(p + L2X0_CACHE_TYPE);
346         aux_ctrl = (aux_ctrl & 0x700) << (17-8);
347         aux_ctrl |= 0x7C000001;
348         if (init) {
349                 l2x0_init(p, aux_ctrl, 0x8200c3fe);
350                 /* use our outer_disable() routine to avoid flush */
351                 outer_cache.disable = tegra_l2x0_disable;
352         } else {
353                 u32 tmp;
354
355                 tmp = aux_ctrl;
356                 aux_ctrl = readl(p + L2X0_AUX_CTRL);
357                 aux_ctrl &= 0x8200c3fe;
358                 aux_ctrl |= tmp;
359                 writel(aux_ctrl, p + L2X0_AUX_CTRL);
360         }
361         l2x0_enable();
362 #endif
363 }
364 #endif /* CONFIG_CACHE_L2X0 */
365
366 static void __init tegra_init_power(void)
367 {
368 #ifdef CONFIG_ARCH_TEGRA_HAS_SATA
369         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_SATA);
370 #endif
371 #ifdef CONFIG_ARCH_TEGRA_HAS_PCIE
372         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_PCIE);
373 #endif
374 }
375
376 static inline unsigned long gizmo_readl(unsigned long offset)
377 {
378         return readl(IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
379 }
380
381 static inline void gizmo_writel(unsigned long value, unsigned long offset)
382 {
383         writel(value, IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
384 }
385
386 static void __init tegra_init_ahb_gizmo_settings(void)
387 {
388         unsigned long val;
389
390         val = gizmo_readl(AHB_GIZMO_AHB_MEM);
391         val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR;
392         gizmo_writel(val, AHB_GIZMO_AHB_MEM);
393
394         val = gizmo_readl(AHB_GIZMO_USB);
395         val |= IMMEDIATE;
396         gizmo_writel(val, AHB_GIZMO_USB);
397
398         val = gizmo_readl(AHB_GIZMO_USB2);
399         val |= IMMEDIATE;
400         gizmo_writel(val, AHB_GIZMO_USB2);
401
402         val = gizmo_readl(AHB_GIZMO_USB3);
403         val |= IMMEDIATE;
404         gizmo_writel(val, AHB_GIZMO_USB3);
405
406         val = gizmo_readl(AHB_ARBITRATION_PRIORITY_CTRL);
407         val |= PRIORITY_SELECT_USB | PRIORITY_SELECT_USB2 | PRIORITY_SELECT_USB3
408                                 | AHB_PRIORITY_WEIGHT(7);
409         gizmo_writel(val, AHB_ARBITRATION_PRIORITY_CTRL);
410
411         val = gizmo_readl(AHB_MEM_PREFETCH_CFG1);
412         val &= ~MST_ID(~0);
413         val |= PREFETCH_ENB | AHBDMA_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
414         gizmo_writel(val, AHB_MEM_PREFETCH_CFG1);
415
416         val = gizmo_readl(AHB_MEM_PREFETCH_CFG2);
417         val &= ~MST_ID(~0);
418         val |= PREFETCH_ENB | USB_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
419         gizmo_writel(val, AHB_MEM_PREFETCH_CFG2);
420
421         val = gizmo_readl(AHB_MEM_PREFETCH_CFG3);
422         val &= ~MST_ID(~0);
423         val |= PREFETCH_ENB | USB3_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
424         gizmo_writel(val, AHB_MEM_PREFETCH_CFG3);
425
426         val = gizmo_readl(AHB_MEM_PREFETCH_CFG4);
427         val &= ~MST_ID(~0);
428         val |= PREFETCH_ENB | USB2_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
429         gizmo_writel(val, AHB_MEM_PREFETCH_CFG4);
430 }
431
432 void __init tegra_init_early(void)
433 {
434 #ifndef CONFIG_SMP
435         /* For SMP system, initializing the reset handler here is too
436            late. For non-SMP systems, the function that calls the reset
437            handler initializer is not called, so do it here for non-SMP. */
438         tegra_cpu_reset_handler_init();
439 #endif
440         tegra_init_fuse();
441         tegra_gpio_resume_init();
442         tegra_init_clock();
443         tegra_init_pinmux();
444         tegra_clk_init_from_table(common_clk_init_table);
445         tegra_init_power();
446         tegra_init_cache(true);
447         tegra_init_ahb_gizmo_settings();
448         tegra_init_debug_uart_rate();
449 }
450
451 static int __init tegra_lp0_vec_arg(char *options)
452 {
453         char *p = options;
454
455         tegra_lp0_vec_size = memparse(p, &p);
456         if (*p == '@')
457                 tegra_lp0_vec_start = memparse(p+1, &p);
458         if (!tegra_lp0_vec_size || !tegra_lp0_vec_start) {
459                 tegra_lp0_vec_size = 0;
460                 tegra_lp0_vec_start = 0;
461         }
462
463         return 0;
464 }
465 early_param("lp0_vec", tegra_lp0_vec_arg);
466
467 static int __init tegra_bootloader_fb_arg(char *options)
468 {
469         char *p = options;
470
471         tegra_bootloader_fb_size = memparse(p, &p);
472         if (*p == '@')
473                 tegra_bootloader_fb_start = memparse(p+1, &p);
474
475         pr_info("Found tegra_fbmem: %08lx@%08lx\n",
476                 tegra_bootloader_fb_size, tegra_bootloader_fb_start);
477
478         return 0;
479 }
480 early_param("tegra_fbmem", tegra_bootloader_fb_arg);
481
482 static int __init tegra_sku_override(char *id)
483 {
484         char *p = id;
485
486         sku_override = memparse(p, &p);
487
488         return 0;
489 }
490 early_param("sku_override", tegra_sku_override);
491
492 int tegra_get_sku_override(void)
493 {
494         return sku_override;
495 }
496
497 static int __init tegra_vpr_arg(char *options)
498 {
499         char *p = options;
500
501         tegra_vpr_size = memparse(p, &p);
502         if (*p == '@')
503                 tegra_vpr_start = memparse(p+1, &p);
504         pr_info("Found vpr, start=0x%lx size=%lx",
505                 tegra_vpr_start, tegra_vpr_size);
506         return 0;
507 }
508 early_param("vpr", tegra_vpr_arg);
509
510 enum panel_type get_panel_type(void)
511 {
512         return board_panel_type;
513 }
514 static int __init tegra_board_panel_type(char *options)
515 {
516         if (!strcmp(options, "lvds"))
517                 board_panel_type = panel_type_lvds;
518         else if (!strcmp(options, "dsi"))
519                 board_panel_type = panel_type_dsi;
520         else
521                 return 0;
522         return 1;
523 }
524 __setup("panel=", tegra_board_panel_type);
525
526 enum power_supply_type get_power_supply_type(void)
527 {
528         return pow_supply_type;
529 }
530 static int __init tegra_board_power_supply_type(char *options)
531 {
532         if (!strcmp(options, "Adapter"))
533                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
534         if (!strcmp(options, "Mains"))
535                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
536         else if (!strcmp(options, "Battery"))
537                 pow_supply_type = POWER_SUPPLY_TYPE_BATTERY;
538         else
539                 return 0;
540         return 1;
541 }
542 __setup("power_supply=", tegra_board_power_supply_type);
543
544 int get_core_edp(void)
545 {
546         return pmu_core_edp;
547 }
548 static int __init tegra_pmu_core_edp(char *options)
549 {
550         char *p = options;
551         int core_edp = memparse(p, &p);
552         if (core_edp != 0)
553                 pmu_core_edp = core_edp;
554         return 0;
555 }
556 early_param("core_edp_mv", tegra_pmu_core_edp);
557
558 int get_maximum_cpu_current_supported(void)
559 {
560         return max_cpu_current;
561 }
562 static int __init tegra_max_cpu_current(char *options)
563 {
564         char *p = options;
565         max_cpu_current = memparse(p, &p);
566         return 1;
567 }
568 __setup("max_cpu_cur_ma=", tegra_max_cpu_current);
569
570 static int __init tegra_debug_uartport(char *info)
571 {
572         char *p = info;
573         unsigned long long port_id;
574         if (!strncmp(p, "hsport", 6))
575                 is_tegra_debug_uart_hsport = true;
576         else if (!strncmp(p, "lsport", 6))
577                 is_tegra_debug_uart_hsport = false;
578
579         if (p[6] == ',') {
580                 if (p[7] == '-') {
581                         debug_uart_port_id = -1;
582                 } else {
583                         port_id = memparse(p + 7, &p);
584                         debug_uart_port_id = (int) port_id;
585                 }
586         } else {
587                 debug_uart_port_id = -1;
588         }
589
590         return 1;
591 }
592
593 bool is_tegra_debug_uartport_hs(void)
594 {
595         return is_tegra_debug_uart_hsport;
596 }
597
598 int get_tegra_uart_debug_port_id(void)
599 {
600         return debug_uart_port_id;
601 }
602 __setup("debug_uartport=", tegra_debug_uartport);
603
604 static int __init tegra_image_type(char *options)
605 {
606         if (!strcmp(options, "RCK"))
607                 board_image_type = rck_image;
608
609         return 0;
610 }
611
612 enum image_type get_tegra_image_type(void)
613 {
614         return board_image_type;
615 }
616
617 __setup("image=", tegra_image_type);
618
619 static int __init tegra_audio_codec_type(char *info)
620 {
621         char *p = info;
622         if (!strncmp(p, "wm8903", 6))
623                 audio_codec_name = audio_codec_wm8903;
624         else
625                 audio_codec_name = audio_codec_none;
626
627         return 1;
628 }
629
630 enum audio_codec_type get_audio_codec_type(void)
631 {
632         return audio_codec_name;
633 }
634 __setup("audio_codec=", tegra_audio_codec_type);
635
636
637 void tegra_get_board_info(struct board_info *bi)
638 {
639 #ifdef CONFIG_OF
640         struct device_node *board_info;
641         u32 prop_val;
642         int err;
643
644         board_info = of_find_node_by_path("/chosen/board_info");
645         if (!IS_ERR_OR_NULL(board_info)) {
646                 memset(bi, 0, sizeof(*bi));
647
648                 err = of_property_read_u32(board_info, "id", &prop_val);
649                 if (err)
650                         pr_err("failed to read /chosen/board_info/id\n");
651                 else
652                         bi->board_id = prop_val;
653
654                 err = of_property_read_u32(board_info, "sku", &prop_val);
655                 if (err)
656                         pr_err("failed to read /chosen/board_info/sku\n");
657                 else
658                         bi->sku = prop_val;
659
660                 err = of_property_read_u32(board_info, "fab", &prop_val);
661                 if (err)
662                         pr_err("failed to read /chosen/board_info/fab\n");
663                 else
664                         bi->fab = prop_val;
665
666                 err = of_property_read_u32(board_info, "major_revision", &prop_val);
667                 if (err)
668                         pr_err("failed to read /chosen/board_info/major_revision\n");
669                 else
670                         bi->major_revision = prop_val;
671
672                 err = of_property_read_u32(board_info, "minor_revision", &prop_val);
673                 if (err)
674                         pr_err("failed to read /chosen/board_info/minor_revision\n");
675                 else
676                         bi->minor_revision = prop_val;
677         } else {
678 #endif
679                 bi->board_id = (system_serial_high >> 16) & 0xFFFF;
680                 bi->sku = (system_serial_high) & 0xFFFF;
681                 bi->fab = (system_serial_low >> 24) & 0xFF;
682                 bi->major_revision = (system_serial_low >> 16) & 0xFF;
683                 bi->minor_revision = (system_serial_low >> 8) & 0xFF;
684 #ifdef CONFIG_OF
685         }
686 #endif
687 }
688
689 static int __init tegra_pmu_board_info(char *info)
690 {
691         char *p = info;
692         pmu_board_info.board_id = memparse(p, &p);
693         pmu_board_info.sku = memparse(p+1, &p);
694         pmu_board_info.fab = memparse(p+1, &p);
695         pmu_board_info.major_revision = memparse(p+1, &p);
696         pmu_board_info.minor_revision = memparse(p+1, &p);
697         return 1;
698 }
699
700 void tegra_get_pmu_board_info(struct board_info *bi)
701 {
702         memcpy(bi, &pmu_board_info, sizeof(struct board_info));
703 }
704
705 __setup("pmuboard=", tegra_pmu_board_info);
706
707 static int __init tegra_display_board_info(char *info)
708 {
709         char *p = info;
710         display_board_info.board_id = memparse(p, &p);
711         display_board_info.sku = memparse(p+1, &p);
712         display_board_info.fab = memparse(p+1, &p);
713         display_board_info.major_revision = memparse(p+1, &p);
714         display_board_info.minor_revision = memparse(p+1, &p);
715         return 1;
716 }
717
718 void tegra_get_display_board_info(struct board_info *bi)
719 {
720         memcpy(bi, &display_board_info, sizeof(struct board_info));
721 }
722
723 __setup("displayboard=", tegra_display_board_info);
724
725 static int __init tegra_camera_board_info(char *info)
726 {
727         char *p = info;
728         camera_board_info.board_id = memparse(p, &p);
729         camera_board_info.sku = memparse(p+1, &p);
730         camera_board_info.fab = memparse(p+1, &p);
731         camera_board_info.major_revision = memparse(p+1, &p);
732         camera_board_info.minor_revision = memparse(p+1, &p);
733         return 1;
734 }
735
736 void tegra_get_camera_board_info(struct board_info *bi)
737 {
738         memcpy(bi, &camera_board_info, sizeof(struct board_info));
739 }
740
741 __setup("cameraboard=", tegra_camera_board_info);
742
743 static int __init tegra_modem_id(char *id)
744 {
745         char *p = id;
746
747         modem_id = memparse(p, &p);
748         return 1;
749 }
750
751 int tegra_get_modem_id(void)
752 {
753         return modem_id;
754 }
755
756 __setup("modem_id=", tegra_modem_id);
757
758 static int __init tegra_commchip_id(char *id)
759 {
760         char *p = id;
761
762         if (get_option(&p, &commchip_id) != 1)
763                 return 0;
764         return 1;
765 }
766
767 int tegra_get_commchip_id(void)
768 {
769         return commchip_id;
770 }
771
772 __setup("commchip_id=", tegra_commchip_id);
773
774 /*
775  * Tegra has a protected aperture that prevents access by most non-CPU
776  * memory masters to addresses above the aperture value.  Enabling it
777  * secures the CPU's memory from the GPU, except through the GART.
778  */
779 void __init tegra_protected_aperture_init(unsigned long aperture)
780 {
781 #ifndef CONFIG_NVMAP_ALLOW_SYSMEM
782         void __iomem *mc_base = IO_ADDRESS(TEGRA_MC_BASE);
783         pr_info("Enabling Tegra protected aperture at 0x%08lx\n", aperture);
784         writel(aperture, mc_base + MC_SECURITY_CFG2);
785 #else
786         pr_err("Tegra protected aperture disabled because nvmap is using "
787                 "system memory\n");
788 #endif
789 }
790
791 /*
792  * Due to conflicting restrictions on the placement of the framebuffer,
793  * the bootloader is likely to leave the framebuffer pointed at a location
794  * in memory that is outside the grhost aperture.  This function will move
795  * the framebuffer contents from a physical address that is anywher (lowmem,
796  * highmem, or outside the memory map) to a physical address that is outside
797  * the memory map.
798  */
799 void tegra_move_framebuffer(unsigned long to, unsigned long from,
800         unsigned long size)
801 {
802         struct page *page;
803         void __iomem *to_io;
804         void *from_virt;
805         unsigned long i;
806
807         BUG_ON(PAGE_ALIGN((unsigned long)to) != (unsigned long)to);
808         BUG_ON(PAGE_ALIGN(from) != from);
809         BUG_ON(PAGE_ALIGN(size) != size);
810
811         to_io = ioremap(to, size);
812         if (!to_io) {
813                 pr_err("%s: Failed to map target framebuffer\n", __func__);
814                 return;
815         }
816
817         if (pfn_valid(page_to_pfn(phys_to_page(from)))) {
818                 for (i = 0 ; i < size; i += PAGE_SIZE) {
819                         page = phys_to_page(from + i);
820                         from_virt = kmap(page);
821                         memcpy(to_io + i, from_virt, PAGE_SIZE);
822                         kunmap(page);
823                 }
824         } else {
825                 void __iomem *from_io = ioremap(from, size);
826                 if (!from_io) {
827                         pr_err("%s: Failed to map source framebuffer\n",
828                                 __func__);
829                         goto out;
830                 }
831
832                 for (i = 0; i < size; i += 4)
833                         writel(readl(from_io + i), to_io + i);
834
835                 iounmap(from_io);
836         }
837 out:
838         iounmap(to_io);
839 }
840
841 void tegra_clear_framebuffer(unsigned long to, unsigned long size)
842 {
843         void __iomem *to_io;
844         unsigned long i;
845
846         BUG_ON(PAGE_ALIGN((unsigned long)to) != (unsigned long)to);
847         BUG_ON(PAGE_ALIGN(size) != size);
848
849         to_io = ioremap(to, size);
850         if (!to_io) {
851                 pr_err("%s: Failed to map target framebuffer\n", __func__);
852                 return;
853         }
854
855         if (pfn_valid(page_to_pfn(phys_to_page(to)))) {
856                 for (i = 0 ; i < size; i += PAGE_SIZE)
857                         memset(to_io + i, 0, PAGE_SIZE);
858         } else {
859                 for (i = 0; i < size; i += 4)
860                         writel(0, to_io + i);
861         }
862         iounmap(to_io);
863 }
864
865 void __init tegra_reserve(unsigned long carveout_size, unsigned long fb_size,
866         unsigned long fb2_size)
867 {
868         if (carveout_size) {
869                 tegra_carveout_start = memblock_end_of_DRAM() - carveout_size;
870                 if (memblock_remove(tegra_carveout_start, carveout_size)) {
871                         pr_err("Failed to remove carveout %08lx@%08lx "
872                                 "from memory map\n",
873                                 carveout_size, tegra_carveout_start);
874                         tegra_carveout_start = 0;
875                         tegra_carveout_size = 0;
876                 } else
877                         tegra_carveout_size = carveout_size;
878         }
879
880         if (fb2_size) {
881                 tegra_fb2_start = memblock_end_of_DRAM() - fb2_size;
882                 if (memblock_remove(tegra_fb2_start, fb2_size)) {
883                         pr_err("Failed to remove second framebuffer "
884                                 "%08lx@%08lx from memory map\n",
885                                 fb2_size, tegra_fb2_start);
886                         tegra_fb2_start = 0;
887                         tegra_fb2_size = 0;
888                 } else
889                         tegra_fb2_size = fb2_size;
890         }
891
892         if (fb_size) {
893                 tegra_fb_start = memblock_end_of_DRAM() - fb_size;
894                 if (memblock_remove(tegra_fb_start, fb_size)) {
895                         pr_err("Failed to remove framebuffer %08lx@%08lx "
896                                 "from memory map\n",
897                                 fb_size, tegra_fb_start);
898                         tegra_fb_start = 0;
899                         tegra_fb_size = 0;
900                 } else
901                         tegra_fb_size = fb_size;
902         }
903
904         if (tegra_fb_size)
905                 tegra_grhost_aperture = tegra_fb_start;
906
907         if (tegra_fb2_size && tegra_fb2_start < tegra_grhost_aperture)
908                 tegra_grhost_aperture = tegra_fb2_start;
909
910         if (tegra_carveout_size && tegra_carveout_start < tegra_grhost_aperture)
911                 tegra_grhost_aperture = tegra_carveout_start;
912
913         if (tegra_lp0_vec_size &&
914            (tegra_lp0_vec_start < memblock_end_of_DRAM())) {
915                 if (memblock_reserve(tegra_lp0_vec_start, tegra_lp0_vec_size)) {
916                         pr_err("Failed to reserve lp0_vec %08lx@%08lx\n",
917                                 tegra_lp0_vec_size, tegra_lp0_vec_start);
918                         tegra_lp0_vec_start = 0;
919                         tegra_lp0_vec_size = 0;
920                 }
921                 tegra_lp0_vec_relocate = false;
922         } else
923                 tegra_lp0_vec_relocate = true;
924
925         /*
926          * We copy the bootloader's framebuffer to the framebuffer allocated
927          * above, and then free this one.
928          * */
929         if (tegra_bootloader_fb_size) {
930                 tegra_bootloader_fb_size = PAGE_ALIGN(tegra_bootloader_fb_size);
931                 if (memblock_reserve(tegra_bootloader_fb_start,
932                                 tegra_bootloader_fb_size)) {
933                         pr_err("Failed to reserve bootloader frame buffer "
934                                 "%08lx@%08lx\n", tegra_bootloader_fb_size,
935                                 tegra_bootloader_fb_start);
936                         tegra_bootloader_fb_start = 0;
937                         tegra_bootloader_fb_size = 0;
938                 }
939         }
940
941         pr_info("Tegra reserved memory:\n"
942                 "LP0:                    %08lx - %08lx\n"
943                 "Bootloader framebuffer: %08lx - %08lx\n"
944                 "Framebuffer:            %08lx - %08lx\n"
945                 "2nd Framebuffer:        %08lx - %08lx\n"
946                 "Carveout:               %08lx - %08lx\n"
947                 "Vpr:                    %08lx - %08lx\n",
948                 tegra_lp0_vec_start,
949                 tegra_lp0_vec_size ?
950                         tegra_lp0_vec_start + tegra_lp0_vec_size - 1 : 0,
951                 tegra_bootloader_fb_start,
952                 tegra_bootloader_fb_size ?
953                         tegra_bootloader_fb_start + tegra_bootloader_fb_size - 1 : 0,
954                 tegra_fb_start,
955                 tegra_fb_size ?
956                         tegra_fb_start + tegra_fb_size - 1 : 0,
957                 tegra_fb2_start,
958                 tegra_fb2_size ?
959                         tegra_fb2_start + tegra_fb2_size - 1 : 0,
960                 tegra_carveout_start,
961                 tegra_carveout_size ?
962                         tegra_carveout_start + tegra_carveout_size - 1 : 0,
963                 tegra_vpr_start,
964                 tegra_vpr_size ?
965                         tegra_vpr_start + tegra_vpr_size - 1 : 0);
966 }
967
968 static struct resource ram_console_resources[] = {
969         {
970                 .flags = IORESOURCE_MEM,
971         },
972 };
973
974 static struct platform_device ram_console_device = {
975         .name           = "ram_console",
976         .id             = -1,
977         .num_resources  = ARRAY_SIZE(ram_console_resources),
978         .resource       = ram_console_resources,
979 };
980
981 void __init tegra_ram_console_debug_reserve(unsigned long ram_console_size)
982 {
983         struct resource *res;
984         long ret;
985
986         res = platform_get_resource(&ram_console_device, IORESOURCE_MEM, 0);
987         if (!res)
988                 goto fail;
989         res->start = memblock_end_of_DRAM() - ram_console_size;
990         res->end = res->start + ram_console_size - 1;
991         ret = memblock_remove(res->start, ram_console_size);
992         if (ret)
993                 goto fail;
994
995         return;
996
997 fail:
998         ram_console_device.resource = NULL;
999         ram_console_device.num_resources = 0;
1000         pr_err("Failed to reserve memory block for ram console\n");
1001 }
1002
1003 void __init tegra_ram_console_debug_init(void)
1004 {
1005         int err;
1006
1007         err = platform_device_register(&ram_console_device);
1008         if (err) {
1009                 pr_err("%s: ram console registration failed (%d)!\n", __func__, err);
1010         }
1011 }
1012
1013 void __init tegra_release_bootloader_fb(void)
1014 {
1015         /* Since bootloader fb is reserved in common.c, it is freed here. */
1016         if (tegra_bootloader_fb_size)
1017                 if (memblock_free(tegra_bootloader_fb_start,
1018                                                 tegra_bootloader_fb_size))
1019                         pr_err("Failed to free bootloader fb.\n");
1020 }
1021
1022 #ifdef CONFIG_TEGRA_CONVSERVATIVE_GOV_ON_EARLYSUPSEND
1023 char cpufreq_default_gov[CONFIG_NR_CPUS][MAX_GOV_NAME_LEN];
1024 char *cpufreq_conservative_gov = "conservative";
1025
1026 void cpufreq_store_default_gov(void)
1027 {
1028         unsigned int cpu = 0;
1029         struct cpufreq_policy *policy;
1030
1031 #ifndef CONFIG_TEGRA_AUTO_HOTPLUG
1032         for_each_online_cpu(cpu)
1033 #endif
1034         {
1035                 policy = cpufreq_cpu_get(cpu);
1036                 if (policy && policy->governor) {
1037                         sprintf(cpufreq_default_gov[cpu], "%s",
1038                                         policy->governor->name);
1039                         cpufreq_cpu_put(policy);
1040                 } else {
1041                         /* No policy or no gov set for this
1042                          * online cpu. If we are here, require
1043                          * serious debugging hence setting
1044                          * as pr_error.
1045                          */
1046                         pr_err("No gov or No policy for online cpu:%d,"
1047                                         , cpu);
1048                 }
1049         }
1050 }
1051
1052 void cpufreq_change_gov(char *target_gov)
1053 {
1054         int ret = -EINVAL;
1055         unsigned int cpu = 0;
1056
1057 #ifndef CONFIG_TEGRA_AUTO_HOTPLUG
1058         for_each_online_cpu(cpu)
1059 #endif
1060         {
1061                 ret = cpufreq_set_gov(target_gov, cpu);
1062                 if (ret < 0)
1063                         /* Unable to set gov for the online cpu.
1064                          * If it happens, needs to debug.
1065                          */
1066                         pr_info("Unable to set gov:%s for online cpu:%d,"
1067                                 , cpufreq_default_gov[cpu]
1068                                         , cpu);
1069         }
1070 }
1071
1072 void cpufreq_restore_default_gov(void)
1073 {
1074         int ret = -EINVAL;
1075         unsigned int cpu = 0;
1076
1077 #ifndef CONFIG_TEGRA_AUTO_HOTPLUG
1078         for_each_online_cpu(cpu)
1079 #endif
1080         {
1081                 if (&cpufreq_default_gov[cpu] &&
1082                         strlen((const char *)&cpufreq_default_gov[cpu])) {
1083                         ret = cpufreq_set_gov(cpufreq_default_gov[cpu], cpu);
1084                         if (ret < 0)
1085                                 /* Unable to restore gov for the cpu as
1086                                  * It was online on suspend and becomes
1087                                  * offline on resume.
1088                                  */
1089                                 pr_info("Unable to restore gov:%s for cpu:%d,"
1090                                                 , cpufreq_default_gov[cpu]
1091                                                         , cpu);
1092                 }
1093                 cpufreq_default_gov[cpu][0] = '\0';
1094         }
1095 }
1096 #endif /* CONFIG_TEGRA_CONVSERVATIVE_GOV_ON_EARLYSUPSEND */