2cc7206d127e0b32320cc7a95f811308e418b8ec
[linux-2.6.git] / arch / arm / mach-tegra / common.c
1 /*
2  * arch/arm/mach-tegra/common.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Copyright (C) 2010-2013 NVIDIA Corporation. All rights reserved.
6  *
7  * Author:
8  *      Colin Cross <ccross@android.com>
9  *
10  * This software is licensed under the terms of the GNU General Public
11  * License version 2, as published by the Free Software Foundation, and
12  * may be copied, distributed, and modified under those terms.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  */
20
21 #include <linux/platform_device.h>
22 #include <linux/console.h>
23 #include <linux/init.h>
24 #include <linux/io.h>
25 #include <linux/clk.h>
26 #include <linux/delay.h>
27 #include <linux/of_irq.h>
28 #include <linux/highmem.h>
29 #include <linux/memblock.h>
30 #include <linux/bitops.h>
31 #include <linux/sched.h>
32 #include <linux/cpufreq.h>
33 #include <linux/of.h>
34 #include <linux/persistent_ram.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/sys_soc.h>
37 #include <linux/export.h>
38 #include <linux/bootmem.h>
39 #include <trace/events/nvsecurity.h>
40
41 #include <asm/soc.h>
42 #include <asm/hardware/cache-l2x0.h>
43 #include <asm/hardware/gic.h>
44 #include <asm/system.h>
45 #include <asm/dma-mapping.h>
46
47 #include <mach/hardware.h>
48 #include <mach/iomap.h>
49 #include <mach/powergate.h>
50 #include <mach/tegra_smmu.h>
51 #include <mach/gpio-tegra.h>
52 #include <mach/nct.h>
53
54 #include "apbio.h"
55 #include "board.h"
56 #include "clock.h"
57 #include "dvfs.h"
58 #include "fuse.h"
59 #include "pm.h"
60 #include "reset.h"
61 #include "devices.h"
62 #include "pmc.h"
63 #include "common.h"
64 #include "atomics.h"
65
66 #define MC_SECURITY_CFG2        0x7c
67
68 #define AHB_ARBITRATION_PRIORITY_CTRL           0x4
69 #define   AHB_PRIORITY_WEIGHT(x)        (((x) & 0x7) << 29)
70 #define   PRIORITY_SELECT_USB   BIT(6)
71 #define   PRIORITY_SELECT_USB2  BIT(18)
72 #define   PRIORITY_SELECT_USB3  BIT(17)
73 #define   PRIORITY_SELECT_SE BIT(14)
74
75 #define AHB_GIZMO_AHB_MEM               0xc
76 #define   ENB_FAST_REARBITRATE  BIT(2)
77 #define   DONT_SPLIT_AHB_WR     BIT(7)
78 #define   WR_WAIT_COMMIT_ON_1K  BIT(8)
79
80 #define   RECOVERY_MODE BIT(31)
81 #define   BOOTLOADER_MODE       BIT(30)
82 #define   FORCED_RECOVERY_MODE  BIT(1)
83
84 #define AHB_GIZMO_USB           0x1c
85 #define AHB_GIZMO_USB2          0x78
86 #define AHB_GIZMO_USB3          0x7c
87 #define AHB_GIZMO_SE            0x4c
88 #define   IMMEDIATE     BIT(18)
89
90 #define AHB_MEM_PREFETCH_CFG5   0xc8
91 #define AHB_MEM_PREFETCH_CFG3   0xe0
92 #define AHB_MEM_PREFETCH_CFG4   0xe4
93 #define AHB_MEM_PREFETCH_CFG1   0xec
94 #define AHB_MEM_PREFETCH_CFG2   0xf0
95 #define AHB_MEM_PREFETCH_CFG6   0xcc
96 #define   PREFETCH_ENB  BIT(31)
97 #define   MST_ID(x)     (((x) & 0x1f) << 26)
98 #define   AHBDMA_MST_ID MST_ID(5)
99 #define   USB_MST_ID    MST_ID(6)
100 #define SDMMC4_MST_ID   MST_ID(12)
101 #define   USB2_MST_ID   MST_ID(18)
102 #define   USB3_MST_ID   MST_ID(17)
103 #define   SE_MST_ID     MST_ID(14)
104 #define   ADDR_BNDRY(x) (((x) & 0xf) << 21)
105 #define   INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0)
106
107 unsigned long tegra_avp_kernel_start;
108 unsigned long tegra_avp_kernel_size;
109 unsigned long tegra_bootloader_fb_start;
110 unsigned long tegra_bootloader_fb_size;
111 unsigned long tegra_bootloader_fb2_start;
112 unsigned long tegra_bootloader_fb2_size;
113 unsigned long tegra_fb_start;
114 unsigned long tegra_fb_size;
115 unsigned long tegra_fb2_start;
116 unsigned long tegra_fb2_size;
117 unsigned long tegra_carveout_start;
118 unsigned long tegra_carveout_size;
119 unsigned long tegra_vpr_start;
120 unsigned long tegra_vpr_size;
121 unsigned long tegra_tsec_start;
122 unsigned long tegra_tsec_size;
123 unsigned long tegra_lp0_vec_start;
124 unsigned long tegra_lp0_vec_size;
125 #ifdef CONFIG_TEGRA_NVDUMPER
126 unsigned long nvdumper_reserved;
127 #endif
128 bool tegra_lp0_vec_relocate;
129 unsigned long tegra_grhost_aperture = ~0ul;
130 static   bool is_tegra_debug_uart_hsport;
131 static struct board_info pmu_board_info;
132 static struct board_info display_board_info;
133 static int panel_id;
134 static struct board_info camera_board_info;
135 static struct board_info io_board_info;
136 static struct board_info button_board_info;
137 static struct board_info joystick_board_info;
138 static struct board_info rightspeaker_board_info;
139 static struct board_info leftspeaker_board_info;
140 #ifdef CONFIG_TEGRA_USE_NCT
141 unsigned long tegra_nck_start;
142 unsigned long tegra_nck_size;
143 #endif
144
145 static int pmu_core_edp;
146 static int board_panel_type;
147 static enum power_supply_type pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
148 static int pwr_i2c_clk = 400;
149 static u8 power_config;
150
151 atomic_t __maybe_unused sd_brightness = ATOMIC_INIT(255);
152 EXPORT_SYMBOL(sd_brightness);
153
154 /*
155  * Storage for debug-macro.S's state.
156  *
157  * This must be in .data not .bss so that it gets initialized each time the
158  * kernel is loaded. The data is declared here rather than debug-macro.S so
159  * that multiple inclusions of debug-macro.S point at the same data.
160  */
161 #define TEGRA_DEBUG_UART_OFFSET (TEGRA_DEBUG_UART_BASE & 0xFFFF)
162 u32 tegra_uart_config[3] = {
163         /* Debug UART initialization required */
164         1,
165         /* Debug UART physical address */
166         (u32)(IO_APB_PHYS + TEGRA_DEBUG_UART_OFFSET),
167         /* Debug UART virtual address */
168         (u32)(IO_APB_VIRT + TEGRA_DEBUG_UART_OFFSET),
169 };
170
171 #define NEVER_RESET 0
172
173 void tegra_assert_system_reset(char mode, const char *cmd)
174 {
175 #if defined(CONFIG_TEGRA_FPGA_PLATFORM) || NEVER_RESET
176         pr_info("tegra_assert_system_reset() ignored.....");
177         do { } while (1);
178 #else
179         void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
180         u32 reg;
181
182         reg = readl_relaxed(reset + PMC_SCRATCH0);
183         /* Writing recovery kernel or Bootloader mode in SCRATCH0 31:30:1 */
184         if (cmd) {
185                 if (!strcmp(cmd, "recovery"))
186                         reg |= RECOVERY_MODE;
187                 else if (!strcmp(cmd, "bootloader"))
188                         reg |= BOOTLOADER_MODE;
189                 else if (!strcmp(cmd, "forced-recovery"))
190                         reg |= FORCED_RECOVERY_MODE;
191                 else
192                         reg &= ~(BOOTLOADER_MODE | RECOVERY_MODE | FORCED_RECOVERY_MODE);
193         }
194         else {
195                 /* Clearing SCRATCH0 31:30:1 on default reboot */
196                 reg &= ~(BOOTLOADER_MODE | RECOVERY_MODE | FORCED_RECOVERY_MODE);
197         }
198         writel_relaxed(reg, reset + PMC_SCRATCH0);
199         reg = readl_relaxed(reset);
200         reg |= 0x10;
201         writel_relaxed(reg, reset);
202 #endif
203 }
204 static int modem_id;
205 static int commchip_id;
206 static int sku_override;
207 static int debug_uart_port_id;
208 static enum audio_codec_type audio_codec_name;
209 static enum image_type board_image_type = system_image;
210 static int max_cpu_current;
211 static int max_core_current;
212 static int emc_max_dvfs;
213 static unsigned int memory_type;
214 static int usb_port_owner_info;
215 static int pmic_rst_reason;
216
217 /* WARNING: There is implicit client of pllp_out3 like i2c, uart, dsi
218  * and so this clock (pllp_out3) should never be disabled.
219  */
220 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
221 static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = {
222         /* name         parent          rate            enabled */
223         { "clk_m",      NULL,           0,              true },
224 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
225         { "pll_p",      NULL,           216000000,      true },
226         { "pll_p_out1", "pll_p",        28800000,       true },
227         { "pll_p_out2", "pll_p",        48000000,       false },
228         { "pll_p_out3", "pll_p",        72000000,       true },
229         { "pll_p_out4", "pll_p",        108000000,      false },
230         { "pll_m",      "clk_m",        0,              true },
231         { "pll_m_out1", "pll_m",        120000000,      true },
232         { "sclk",       "pll_c_out1",   40000000,       true },
233         { "hclk",       "sclk",         40000000,       true },
234         { "pclk",       "hclk",         40000000,       true },
235         { "mpe",        "pll_c",        0,              false },
236         { "epp",        "pll_c",        0,              false },
237         { "vi_sensor",  "pll_c",        0,              false },
238         { "vi",         "pll_c",        0,              false },
239         { "2d",         "pll_c",        0,              false },
240         { "3d",         "pll_c",        0,              false },
241 #else
242         { "pll_p",      NULL,           216000000,      true },
243         { "pll_p_out1", "pll_p",        28800000,       false },
244         { "pll_p_out2", "pll_p",        48000000,       false },
245         { "pll_p_out3", "pll_p",        72000000,       true },
246         { "pll_m_out1", "pll_m",        275000000,      true },
247         { "pll_c",      NULL,           ULONG_MAX,      false },
248         { "pll_c_out1", "pll_c",        208000000,      false },
249         { "pll_p_out4", "pll_p",        108000000,      false },
250         { "sclk",       "pll_p_out4",   108000000,      true },
251         { "hclk",       "sclk",         108000000,      true },
252         { "pclk",       "hclk",         54000000,       true },
253 #endif
254         { "sbc1.sclk",  NULL,           40000000,       false},
255         { "sbc2.sclk",  NULL,           40000000,       false},
256         { "sbc3.sclk",  NULL,           40000000,       false},
257         { "sbc4.sclk",  NULL,           40000000,       false},
258 #ifdef CONFIG_TEGRA_SLOW_CSITE
259         { "csite",      "clk_m",        1000000,        true },
260 #else
261         { "csite",      NULL,           0,              true },
262 #endif
263         { "emc",        NULL,           0,              true },
264         { "cpu",        NULL,           0,              true },
265         { "kfuse",      NULL,           0,              true },
266         { "fuse",       NULL,           0,              true },
267         { "pll_u",      NULL,           480000000,      false },
268         { "sdmmc1",     "pll_p",        48000000,       false},
269         { "sdmmc3",     "pll_p",        48000000,       false},
270         { "sdmmc4",     "pll_p",        48000000,       false},
271         { "pll_a",      "pll_p_out1",   0,              false},
272         { "pll_a_out0", "pll_a",        0,              false},
273         { NULL,         NULL,           0,              0},
274 };
275 #endif
276 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
277 static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = {
278         /* name         parent          rate            enabled */
279         { "clk_m",      NULL,           0,              true },
280         { "emc",        NULL,           0,              true },
281         { "cpu",        NULL,           0,              true },
282         { "kfuse",      NULL,           0,              true },
283         { "fuse",       NULL,           0,              true },
284 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
285         { "pll_p",      NULL,           0,              true },
286         { "pll_p_out1", "pll_p",        0,              false },
287         { "pll_p_out2", "pll_p",        48000000,       false },
288         { "pll_p_out3", "pll_p",        0,              true },
289         { "pll_m_out1", "pll_m",        275000000,      false },
290         { "pll_p_out4", "pll_p",        102000000,      true },
291         { "sclk",       "pll_p_out4",   102000000,      true },
292         { "hclk",       "sclk",         102000000,      true },
293         { "pclk",       "hclk",         51000000,       true },
294 #else
295         { "pll_p",      NULL,           216000000,      true },
296         { "pll_p_out1", "pll_p",        28800000,       false },
297         { "pll_p_out2", "pll_p",        48000000,       false },
298         { "pll_p_out3", "pll_p",        72000000,       true },
299         { "pll_m_out1", "pll_m",        275000000,      true },
300         { "pll_p_out4", "pll_p",        108000000,      false },
301         { "sclk",       "pll_p_out4",   108000000,      true },
302         { "hclk",       "sclk",         108000000,      true },
303         { "pclk",       "hclk",         54000000,       true },
304 #endif
305 #ifdef CONFIG_TEGRA_SLOW_CSITE
306         { "csite",      "clk_m",        1000000,        true },
307 #else
308         { "csite",      NULL,           0,              true },
309 #endif
310         { "pll_u",      NULL,           480000000,      false },
311         { "sdmmc1",     "pll_p",        48000000,       false},
312         { "sdmmc3",     "pll_p",        48000000,       false},
313         { "sdmmc4",     "pll_p",        48000000,       false},
314         { "sbc1.sclk",  NULL,           40000000,       false},
315         { "sbc2.sclk",  NULL,           40000000,       false},
316         { "sbc3.sclk",  NULL,           40000000,       false},
317         { "sbc4.sclk",  NULL,           40000000,       false},
318         { "sbc5.sclk",  NULL,           40000000,       false},
319         { "sbc6.sclk",  NULL,           40000000,       false},
320 #ifdef CONFIG_TEGRA_PCI
321         { "mselect",    "pll_p",        204000000,      true },
322 #else
323         { "mselect",    "pll_p",        102000000,      true },
324 #endif
325         { NULL,         NULL,           0,              0},
326 };
327 static __initdata struct tegra_clk_init_table tegra30_cbus_init_table[] = {
328         { "cbus",       "pll_c",        416000000,      false },
329         { "pll_c_out1", "pll_c",        208000000,      false },
330         { NULL,         NULL,           0,              0},
331 };
332 #endif
333 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
334 static __initdata struct tegra_clk_init_table tegra11x_clk_init_table[] = {
335         /* name         parent          rate            enabled */
336         { "clk_m",      NULL,           0,              true },
337         { "emc",        NULL,           0,              true },
338         { "cpu",        NULL,           0,              true },
339         { "kfuse",      NULL,           0,              true },
340         { "fuse",       NULL,           0,              true },
341         { "sclk",       NULL,           0,              true },
342         { "pll_p",      NULL,           0,              true },
343         { "pll_p_out1", "pll_p",        0,              false },
344         { "pll_p_out3", "pll_p",        0,              false },
345 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
346         { "pll_m_out1", "pll_m",        275000000,      false },
347         { "pll_p_out2",  "pll_p",       102000000,      false },
348         { "sclk",        "pll_p_out2",  102000000,      true },
349         { "pll_p_out4",  "pll_p",       204000000,      true },
350         { "hclk",       "sclk",         102000000,      true },
351         { "pclk",       "hclk",         51000000,       true },
352         { "mselect",    "pll_p",        102000000,      true },
353         { "host1x",     "pll_p",        102000000,      false },
354         { "cl_dvfs_ref", "pll_p",       51000000,       true },
355         { "cl_dvfs_soc", "pll_p",       51000000,       true },
356         { "dsialp", "pll_p",    70000000,       false },
357         { "dsiblp", "pll_p",    70000000,       false },
358 #else
359         { "pll_m_out1", "pll_m",        275000000,      true },
360         { "pll_p_out2", "pll_p",        108000000,      false },
361         { "sclk",       "pll_p_out2",   108000000,      true },
362         { "pll_p_out4", "pll_p",        216000000,      true },
363         { "hclk",       "sclk",         108000000,      true },
364         { "pclk",       "hclk",         54000000,       true },
365         { "mselect",    "pll_p",        108000000,      true },
366         { "host1x",     "pll_p",        108000000,      false },
367         { "cl_dvfs_ref", "clk_m",       13000000,       false },
368         { "cl_dvfs_soc", "clk_m",       13000000,       false },
369 #endif
370 #ifdef CONFIG_TEGRA_SLOW_CSITE
371         { "csite",      "clk_m",        1000000,        true },
372 #else
373         { "csite",      NULL,           0,              true },
374 #endif
375         { "pll_u",      NULL,           480000000,      true },
376         { "pll_re_vco", NULL,           612000000,      true },
377         { "xusb_falcon_src",    "pll_p",        204000000,      false},
378         { "xusb_host_src",      "pll_p",        102000000,      false},
379         { "xusb_ss_src",        "pll_re_vco",   122400000,      false},
380         { "xusb_hs_src",        "xusb_ss_div2", 61200000,       false},
381         { "xusb_fs_src",        "pll_u_48M",    48000000,       false},
382         { "sdmmc1",     "pll_p",        48000000,       false},
383         { "sdmmc3",     "pll_p",        48000000,       false},
384         { "sdmmc4",     "pll_p",        48000000,       false},
385         { "sbc1.sclk",  NULL,           40000000,       false},
386         { "sbc2.sclk",  NULL,           40000000,       false},
387         { "sbc3.sclk",  NULL,           40000000,       false},
388         { "sbc4.sclk",  NULL,           40000000,       false},
389         { "sbc5.sclk",  NULL,           40000000,       false},
390         { "sbc6.sclk",  NULL,           40000000,       false},
391 #ifdef CONFIG_TEGRA_PLLM_SCALED
392         { "vi",         "pll_p",        0,              false},
393 #endif
394 #ifdef CONFIG_TEGRA_SOCTHERM
395         { "soc_therm",  "pll_p",        51000000,       false },
396         { "tsensor",    "clk_m",        500000,         false },
397 #endif
398 #ifdef CONFIG_TEGRA_ATOMICS
399         { "atomics",    NULL,           0,              true},
400 #endif
401         { NULL,         NULL,           0,              0},
402 };
403 static __initdata struct tegra_clk_init_table tegra11x_cbus_init_table[] = {
404 #ifdef CONFIG_TEGRA_DUAL_CBUS
405         { "c2bus",      "pll_c2",       250000000,      false },
406         { "c3bus",      "pll_c3",       250000000,      false },
407         { "pll_c",      NULL,           624000000,      false },
408 #else
409         { "cbus",       "pll_c",        250000000,      false },
410 #endif
411         { "pll_c_out1", "pll_c",        150000000,      false },
412         { NULL,         NULL,           0,              0},
413 };
414 #endif
415
416 #ifdef CONFIG_CACHE_L2X0
417 #if defined(CONFIG_ARCH_TEGRA_3x_SOC) || defined(CONFIG_ARCH_TEGRA_2x_SOC)
418 #ifdef CONFIG_TRUSTED_FOUNDATIONS
419 static void tegra_cache_smc(bool enable, u32 arg)
420 {
421         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
422         bool need_affinity_switch;
423         bool can_switch_affinity;
424         bool l2x0_enabled;
425         cpumask_t local_cpu_mask;
426         cpumask_t saved_cpu_mask;
427         unsigned long flags;
428         long ret;
429
430         /*
431          * ISSUE : Some registers of PL310 controler must be written
432          *              from Secure context (and from CPU0)!
433          *
434          * When called form Normal we obtain an abort or do nothing.
435          * Instructions that must be called in Secure:
436          *      - Write to Control register (L2X0_CTRL==0x100)
437          *      - Write in Auxiliary controler (L2X0_AUX_CTRL==0x104)
438          *      - Invalidate all entries (L2X0_INV_WAY==0x77C),
439          *              mandatory at boot time.
440          *      - Tag and Data RAM Latency Control Registers
441          *              (0x108 & 0x10C) must be written in Secure.
442          */
443         need_affinity_switch = (smp_processor_id() != 0);
444         can_switch_affinity = !irqs_disabled();
445
446         WARN_ON(need_affinity_switch && !can_switch_affinity);
447         if (need_affinity_switch && can_switch_affinity) {
448                 cpu_set(0, local_cpu_mask);
449                 sched_getaffinity(0, &saved_cpu_mask);
450                 ret = sched_setaffinity(0, &local_cpu_mask);
451                 WARN_ON(ret != 0);
452         }
453
454         local_irq_save(flags);
455         l2x0_enabled = readl_relaxed(p + L2X0_CTRL) & 1;
456         if (enable && !l2x0_enabled)
457                 tegra_generic_smc(0xFFFFF100, 0x00000001, arg);
458         else if (!enable && l2x0_enabled)
459                 tegra_generic_smc(0xFFFFF100, 0x00000002, arg);
460         local_irq_restore(flags);
461
462         if (need_affinity_switch && can_switch_affinity) {
463                 ret = sched_setaffinity(0, &saved_cpu_mask);
464                 WARN_ON(ret != 0);
465         }
466 }
467
468 static void tegra_l2x0_disable(void)
469 {
470         unsigned long flags;
471         static u32 l2x0_way_mask;
472
473         if (!l2x0_way_mask) {
474                 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
475                 u32 aux_ctrl;
476                 u32 ways;
477
478                 aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
479                 ways = (aux_ctrl & (1 << 16)) ? 16 : 8;
480                 l2x0_way_mask = (1 << ways) - 1;
481         }
482
483         local_irq_save(flags);
484         tegra_cache_smc(false, l2x0_way_mask);
485         local_irq_restore(flags);
486 }
487 #endif  /* CONFIG_TRUSTED_FOUNDATIONS  */
488
489 void tegra_init_cache(bool init)
490 {
491         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
492         u32 aux_ctrl;
493 #ifndef CONFIG_TRUSTED_FOUNDATIONS
494         u32 cache_type;
495         u32 tag_latency, data_latency;
496 #endif
497
498 #ifdef CONFIG_TRUSTED_FOUNDATIONS
499         /* issue the SMC to enable the L2 */
500         aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
501         trace_smc_init_cache(NVSEC_SMC_START);
502         tegra_cache_smc(true, aux_ctrl);
503         trace_smc_init_cache(NVSEC_SMC_DONE);
504
505         /* after init, reread aux_ctrl and register handlers */
506         aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
507         l2x0_init(p, aux_ctrl, 0xFFFFFFFF);
508
509         /* override outer_disable() with our disable */
510         outer_cache.disable = tegra_l2x0_disable;
511 #else
512 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
513         tag_latency = 0x331;
514         data_latency = 0x441;
515 #elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
516 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
517         if (is_lp_cluster()) {
518                 tag_latency = 0x221;
519                 data_latency = 0x221;
520         } else {
521                 u32 speedo;
522
523                 /* relax l2-cache latency for speedos 4,5,6 (T33's chips) */
524                 speedo = tegra_cpu_speedo_id();
525                 if (speedo == 4 || speedo == 5 || speedo == 6 ||
526                     speedo == 12 || speedo == 13) {
527                         tag_latency = 0x442;
528                         data_latency = 0x552;
529                 } else {
530                         tag_latency = 0x441;
531                         data_latency = 0x551;
532                 }
533         }
534 #else
535         tag_latency = 0x770;
536         data_latency = 0x770;
537 #endif
538 #endif
539         writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
540         writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL);
541
542 #if defined(CONFIG_ARCH_TEGRA_3x_SOC)
543 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
544         writel(7, p + L2X0_PREFETCH_CTRL);
545         writel(2, p + L2X0_POWER_CTRL);
546 #endif
547 #endif
548
549         writel(0x3, p + L2X0_POWER_CTRL);
550         cache_type = readl(p + L2X0_CACHE_TYPE);
551         aux_ctrl = (cache_type & 0x700) << (17-8);
552         aux_ctrl |= 0x7C400001;
553         if (init) {
554                 l2x0_init(p, aux_ctrl, 0x8200c3fe);
555         } else {
556                 u32 tmp;
557
558                 tmp = aux_ctrl;
559                 aux_ctrl = readl(p + L2X0_AUX_CTRL);
560                 aux_ctrl &= 0x8200c3fe;
561                 aux_ctrl |= tmp;
562                 writel(aux_ctrl, p + L2X0_AUX_CTRL);
563         }
564         l2x0_enable();
565 #endif
566 }
567 #else
568 void tegra_init_cache(bool init)
569 {
570 }
571 #endif
572 #endif
573
574 static void __init tegra_perf_init(void)
575 {
576         u32 reg;
577
578         asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(reg));
579         reg >>= 11;
580         reg = (1 << (reg & 0x1f))-1;
581         reg |= 0x80000000;
582         asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r"(reg));
583         reg = 1;
584         asm volatile("mcr p15, 0, %0, c9, c14, 0" : : "r"(reg));
585 }
586
587 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
588 static void __init tegra_ramrepair_init(void)
589 {
590         if (tegra_spare_fuse(10)  | tegra_spare_fuse(11)) {
591                 u32 reg;
592                 reg = readl(FLOW_CTRL_RAM_REPAIR);
593                 reg &= ~FLOW_CTRL_RAM_REPAIR_BYPASS_EN;
594                 writel(reg, FLOW_CTRL_RAM_REPAIR);
595         }
596 }
597 #endif
598
599 static void __init tegra_init_power(void)
600 {
601 #ifdef CONFIG_ARCH_TEGRA_HAS_SATA
602         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_SATA);
603 #endif
604 #ifdef CONFIG_ARCH_TEGRA_HAS_PCIE
605         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_PCIE);
606 #endif
607 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
608         /* some partitions need to be powergated by default for t11x */
609         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBA);
610         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBB);
611         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBC);
612 #endif
613 }
614
615 static inline unsigned long gizmo_readl(unsigned long offset)
616 {
617         return readl(IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
618 }
619
620 static inline void gizmo_writel(unsigned long value, unsigned long offset)
621 {
622         writel(value, IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
623 }
624
625 static void __init tegra_init_ahb_gizmo_settings(void)
626 {
627         unsigned long val;
628
629         val = gizmo_readl(AHB_GIZMO_AHB_MEM);
630         val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR;
631
632         if (tegra_get_chipid() == TEGRA_CHIPID_TEGRA11)
633                 val |= WR_WAIT_COMMIT_ON_1K;
634         gizmo_writel(val, AHB_GIZMO_AHB_MEM);
635
636         val = gizmo_readl(AHB_GIZMO_USB);
637         val |= IMMEDIATE;
638         gizmo_writel(val, AHB_GIZMO_USB);
639
640         val = gizmo_readl(AHB_GIZMO_USB2);
641         val |= IMMEDIATE;
642         gizmo_writel(val, AHB_GIZMO_USB2);
643
644         val = gizmo_readl(AHB_GIZMO_USB3);
645         val |= IMMEDIATE;
646         gizmo_writel(val, AHB_GIZMO_USB3);
647
648 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
649         val = gizmo_readl(AHB_GIZMO_SE);
650         val |= IMMEDIATE;
651         gizmo_writel(val, AHB_GIZMO_SE);
652 #endif
653
654         val = gizmo_readl(AHB_ARBITRATION_PRIORITY_CTRL);
655         val |= PRIORITY_SELECT_USB | PRIORITY_SELECT_USB2 | PRIORITY_SELECT_USB3
656                                 | AHB_PRIORITY_WEIGHT(7);
657 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
658         val |= PRIORITY_SELECT_SE;
659 #endif
660         gizmo_writel(val, AHB_ARBITRATION_PRIORITY_CTRL);
661
662         val = gizmo_readl(AHB_MEM_PREFETCH_CFG1);
663         val &= ~MST_ID(~0);
664         val |= PREFETCH_ENB | AHBDMA_MST_ID |
665                 ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
666         gizmo_writel(val, AHB_MEM_PREFETCH_CFG1);
667
668         val = gizmo_readl(AHB_MEM_PREFETCH_CFG2);
669         val &= ~MST_ID(~0);
670         val |= PREFETCH_ENB | USB_MST_ID | ADDR_BNDRY(0xc) |
671                 INACTIVITY_TIMEOUT(0x1000);
672         gizmo_writel(val, AHB_MEM_PREFETCH_CFG2);
673
674         val = gizmo_readl(AHB_MEM_PREFETCH_CFG3);
675         val &= ~MST_ID(~0);
676         val |= PREFETCH_ENB | USB3_MST_ID | ADDR_BNDRY(0xc) |
677                 INACTIVITY_TIMEOUT(0x1000);
678         gizmo_writel(val, AHB_MEM_PREFETCH_CFG3);
679
680         val = gizmo_readl(AHB_MEM_PREFETCH_CFG4);
681         val &= ~MST_ID(~0);
682         val |= PREFETCH_ENB | USB2_MST_ID | ADDR_BNDRY(0xc) |
683                 INACTIVITY_TIMEOUT(0x1000);
684         gizmo_writel(val, AHB_MEM_PREFETCH_CFG4);
685
686 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
687         val = gizmo_readl(AHB_MEM_PREFETCH_CFG5);
688         val &= ~MST_ID(~0);
689         val |= PREFETCH_ENB | SDMMC4_MST_ID;
690         gizmo_writel(val, AHB_MEM_PREFETCH_CFG5);
691
692         val = gizmo_readl(AHB_MEM_PREFETCH_CFG6);
693         val &= ~MST_ID(~0);
694         val |= PREFETCH_ENB | SE_MST_ID | ADDR_BNDRY(0xc) |
695                 INACTIVITY_TIMEOUT(0x1000);
696         gizmo_writel(val, AHB_MEM_PREFETCH_CFG6);
697 #endif
698 }
699
700 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
701 void __init tegra20_init_early(void)
702 {
703 #ifndef CONFIG_SMP
704         /* For SMP system, initializing the reset handler here is too
705            late. For non-SMP systems, the function that calls the reset
706            handler initializer is not called, so do it here for non-SMP. */
707         tegra_cpu_reset_handler_init();
708 #endif
709         tegra_perf_init();
710         tegra_init_fuse();
711         tegra2_init_clocks();
712         tegra2_init_dvfs();
713         tegra_common_init_clock();
714         tegra_clk_init_from_table(tegra20_clk_init_table);
715         tegra_init_cache(true);
716         tegra_pmc_init();
717         tegra_powergate_init();
718         tegra_init_power();
719         tegra_init_ahb_gizmo_settings();
720         tegra_init_debug_uart_rate();
721         tegra_gpio_resume_init();
722         tegra_ram_console_debug_reserve(SZ_1M);
723 }
724 #endif
725 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
726 void __init tegra30_init_early(void)
727 {
728 #ifndef CONFIG_SMP
729         /* For SMP system, initializing the reset handler here is too
730            late. For non-SMP systems, the function that calls the reset
731            handler initializer is not called, so do it here for non-SMP. */
732         tegra_cpu_reset_handler_init();
733 #endif
734         tegra_perf_init();
735         tegra_init_fuse();
736         tegra30_init_clocks();
737         tegra3_init_dvfs();
738         tegra_common_init_clock();
739         tegra_clk_init_from_table(tegra30_clk_init_table);
740         tegra_clk_init_cbus_plls_from_table(tegra30_cbus_init_table);
741         tegra_init_cache(true);
742         tegra_pmc_init();
743         tegra_powergate_init();
744         tegra_init_power();
745         tegra_init_ahb_gizmo_settings();
746         tegra_init_debug_uart_rate();
747         tegra_gpio_resume_init();
748         tegra_ram_console_debug_reserve(SZ_1M);
749
750         init_dma_coherent_pool_size(SZ_1M);
751 }
752 #endif
753 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
754 void __init tegra11x_init_early(void)
755 {
756 #ifndef CONFIG_SMP
757         /* For SMP system, initializing the reset handler here is too
758            late. For non-SMP systems, the function that calls the reset
759            handler initializer is not called, so do it here for non-SMP. */
760         tegra_cpu_reset_handler_init();
761 #endif
762         tegra_perf_init();
763         tegra_init_fuse();
764         tegra_ramrepair_init();
765         tegra11x_init_clocks();
766         tegra11x_init_dvfs();
767         tegra_common_init_clock();
768         tegra_clk_init_from_table(tegra11x_clk_init_table);
769         tegra_clk_init_cbus_plls_from_table(tegra11x_cbus_init_table);
770         tegra11x_clk_init_la();
771         tegra_pmc_init();
772         tegra_powergate_init();
773         tegra_init_power();
774         tegra_init_ahb_gizmo_settings();
775         tegra_init_debug_uart_rate();
776         tegra_gpio_resume_init();
777 #ifdef CONFIG_TEGRA_ATOMICS
778         tegra_atomics_init();
779 #endif
780
781         init_dma_coherent_pool_size(SZ_1M);
782 }
783 #endif
784 static int __init tegra_lp0_vec_arg(char *options)
785 {
786         char *p = options;
787
788         tegra_lp0_vec_size = memparse(p, &p);
789         if (*p == '@')
790                 tegra_lp0_vec_start = memparse(p+1, &p);
791         if (!tegra_lp0_vec_size || !tegra_lp0_vec_start) {
792                 tegra_lp0_vec_size = 0;
793                 tegra_lp0_vec_start = 0;
794         }
795
796         return 0;
797 }
798 early_param("lp0_vec", tegra_lp0_vec_arg);
799
800 #ifdef CONFIG_TEGRA_NVDUMPER
801 static int __init tegra_nvdumper_arg(char *options)
802 {
803         char *p = options;
804
805         nvdumper_reserved = memparse(p, &p);
806         return 0;
807 }
808 early_param("nvdumper_reserved", tegra_nvdumper_arg);
809 #endif
810
811 static int __init tegra_bootloader_fb_arg(char *options)
812 {
813         char *p = options;
814
815         tegra_bootloader_fb_size = memparse(p, &p);
816         if (*p == '@')
817                 tegra_bootloader_fb_start = memparse(p+1, &p);
818
819         pr_info("Found tegra_fbmem: %08lx@%08lx\n",
820                 tegra_bootloader_fb_size, tegra_bootloader_fb_start);
821
822         return 0;
823 }
824 early_param("tegra_fbmem", tegra_bootloader_fb_arg);
825
826 static int __init tegra_bootloader_fb2_arg(char *options)
827 {
828         char *p = options;
829
830         tegra_bootloader_fb2_size = memparse(p, &p);
831         if (*p == '@')
832                 tegra_bootloader_fb2_start = memparse(p+1, &p);
833
834         pr_info("Found tegra_fbmem2: %08lx@%08lx\n",
835                 tegra_bootloader_fb2_size, tegra_bootloader_fb2_start);
836
837         return 0;
838 }
839 early_param("tegra_fbmem2", tegra_bootloader_fb2_arg);
840
841 static int __init tegra_sku_override(char *id)
842 {
843         char *p = id;
844
845         sku_override = memparse(p, &p);
846
847         return 0;
848 }
849 early_param("sku_override", tegra_sku_override);
850
851 int tegra_get_sku_override(void)
852 {
853         return sku_override;
854 }
855
856 static int __init tegra_vpr_arg(char *options)
857 {
858         char *p = options;
859
860         tegra_vpr_size = memparse(p, &p);
861         if (*p == '@')
862                 tegra_vpr_start = memparse(p+1, &p);
863         pr_info("Found vpr, start=0x%lx size=%lx",
864                 tegra_vpr_start, tegra_vpr_size);
865         return 0;
866 }
867 early_param("vpr", tegra_vpr_arg);
868
869 static int __init tegra_tsec_arg(char *options)
870 {
871         char *p = options;
872
873         tegra_tsec_size = memparse(p, &p);
874         if (*p == '@')
875                 tegra_tsec_start = memparse(p+1, &p);
876         pr_info("Found tsec, start=0x%lx size=%lx",
877                 tegra_tsec_start, tegra_tsec_size);
878         return 0;
879 }
880 early_param("tsec", tegra_tsec_arg);
881
882 #ifdef CONFIG_TEGRA_USE_NCT
883 static int __init tegra_nck_arg(char *options)
884 {
885         char *p = options;
886
887         tegra_nck_size = memparse(p, &p);
888         if (*p == '@')
889                 tegra_nck_start = memparse(p+1, &p);
890         if (!tegra_nck_size || !tegra_nck_start) {
891                 tegra_nck_size = 0;
892                 tegra_nck_start = 0;
893         }
894
895         return 0;
896 }
897 early_param("nck", tegra_nck_arg);
898 #endif  /* CONFIG_TEGRA_USE_NCT */
899
900 enum panel_type get_panel_type(void)
901 {
902         return board_panel_type;
903 }
904 static int __init tegra_board_panel_type(char *options)
905 {
906         if (!strcmp(options, "lvds"))
907                 board_panel_type = panel_type_lvds;
908         else if (!strcmp(options, "dsi"))
909                 board_panel_type = panel_type_dsi;
910         else
911                 return 0;
912         return 1;
913 }
914 __setup("panel=", tegra_board_panel_type);
915
916 int tegra_get_board_panel_id(void)
917 {
918         return panel_id;
919 }
920 static int __init tegra_board_panel_id(char *options)
921 {
922         char *p = options;
923         panel_id = memparse(p, &p);
924         return panel_id;
925 }
926 __setup("display_panel=", tegra_board_panel_id);
927
928 u8 get_power_config(void)
929 {
930         return power_config;
931 }
932 static int __init tegra_board_power_config(char *options)
933 {
934         char *p = options;
935         power_config = memparse(p, &p);
936         return 1;
937 }
938 __setup("power-config=", tegra_board_power_config);
939
940 enum power_supply_type get_power_supply_type(void)
941 {
942         return pow_supply_type;
943 }
944 static int __init tegra_board_power_supply_type(char *options)
945 {
946         if (!strcmp(options, "Adapter"))
947                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
948         if (!strcmp(options, "Mains"))
949                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
950         else if (!strcmp(options, "Battery"))
951                 pow_supply_type = POWER_SUPPLY_TYPE_BATTERY;
952         else
953                 return 0;
954         return 1;
955 }
956 __setup("power_supply=", tegra_board_power_supply_type);
957
958 int get_core_edp(void)
959 {
960         return pmu_core_edp;
961 }
962 static int __init tegra_pmu_core_edp(char *options)
963 {
964         char *p = options;
965         int core_edp = memparse(p, &p);
966         if (core_edp != 0)
967                 pmu_core_edp = core_edp;
968         return 0;
969 }
970 early_param("core_edp_mv", tegra_pmu_core_edp);
971
972 int get_maximum_cpu_current_supported(void)
973 {
974         return max_cpu_current;
975 }
976 static int __init tegra_max_cpu_current(char *options)
977 {
978         char *p = options;
979         max_cpu_current = memparse(p, &p);
980         return 1;
981 }
982 __setup("max_cpu_cur_ma=", tegra_max_cpu_current);
983
984 int get_maximum_core_current_supported(void)
985 {
986         return max_core_current;
987 }
988 static int __init tegra_max_core_current(char *options)
989 {
990         char *p = options;
991         max_core_current = memparse(p, &p);
992         return 0;
993 }
994 early_param("core_edp_ma", tegra_max_core_current);
995
996 int get_emc_max_dvfs(void)
997 {
998         return emc_max_dvfs;
999 }
1000 static int __init tegra_emc_max_dvfs(char *options)
1001 {
1002         char *p = options;
1003         emc_max_dvfs = memparse(p, &p);
1004         return 1;
1005 }
1006 __setup("emc_max_dvfs=", tegra_emc_max_dvfs);
1007
1008 int tegra_get_memory_type(void)
1009 {
1010         return memory_type;
1011 }
1012 static int __init tegra_memory_type(char *options)
1013 {
1014         char *p = options;
1015         memory_type = memparse(p, &p);
1016         return 1;
1017 }
1018 __setup("memtype=", tegra_memory_type);
1019
1020 static int __init tegra_debug_uartport(char *info)
1021 {
1022         char *p = info;
1023         unsigned long long port_id;
1024         if (!strncmp(p, "hsport", 6))
1025                 is_tegra_debug_uart_hsport = true;
1026         else if (!strncmp(p, "lsport", 6))
1027                 is_tegra_debug_uart_hsport = false;
1028
1029         if (p[6] == ',') {
1030                 if (p[7] == '-') {
1031                         debug_uart_port_id = -1;
1032                 } else {
1033                         port_id = memparse(p + 7, &p);
1034                         debug_uart_port_id = (int) port_id;
1035                 }
1036         } else {
1037                 debug_uart_port_id = -1;
1038         }
1039
1040         return 1;
1041 }
1042
1043 bool is_tegra_debug_uartport_hs(void)
1044 {
1045         return is_tegra_debug_uart_hsport;
1046 }
1047
1048 int get_tegra_uart_debug_port_id(void)
1049 {
1050         return debug_uart_port_id;
1051 }
1052 __setup("debug_uartport=", tegra_debug_uartport);
1053
1054 static int __init tegra_image_type(char *options)
1055 {
1056         if (!strcmp(options, "RCK"))
1057                 board_image_type = rck_image;
1058
1059         return 0;
1060 }
1061
1062 enum image_type get_tegra_image_type(void)
1063 {
1064         return board_image_type;
1065 }
1066
1067 __setup("image=", tegra_image_type);
1068
1069 static int __init tegra_audio_codec_type(char *info)
1070 {
1071         char *p = info;
1072         if (!strncmp(p, "wm8903", 6))
1073                 audio_codec_name = audio_codec_wm8903;
1074         else
1075                 audio_codec_name = audio_codec_none;
1076
1077         return 1;
1078 }
1079
1080 enum audio_codec_type get_audio_codec_type(void)
1081 {
1082         return audio_codec_name;
1083 }
1084 __setup("audio_codec=", tegra_audio_codec_type);
1085
1086 static int tegra_get_pwr_i2c_clk_rate(char *options)
1087 {
1088         int clk = simple_strtol(options, NULL, 16);
1089         if (clk != 0)
1090                 pwr_i2c_clk = clk;
1091         return 0;
1092 }
1093
1094 int get_pwr_i2c_clk_rate(void)
1095 {
1096         return pwr_i2c_clk;
1097 }
1098 __setup("pwr_i2c=", tegra_get_pwr_i2c_clk_rate);
1099
1100 void tegra_get_board_info(struct board_info *bi)
1101 {
1102 #ifdef CONFIG_OF
1103         struct device_node *board_info;
1104         u32 prop_val;
1105         int err;
1106
1107         board_info = of_find_node_by_path("/chosen/board_info");
1108         if (!IS_ERR_OR_NULL(board_info)) {
1109                 memset(bi, 0, sizeof(*bi));
1110
1111                 err = of_property_read_u32(board_info, "id", &prop_val);
1112                 if (err)
1113                         pr_err("failed to read /chosen/board_info/id\n");
1114                 else
1115                         bi->board_id = prop_val;
1116
1117                 err = of_property_read_u32(board_info, "sku", &prop_val);
1118                 if (err)
1119                         pr_err("failed to read /chosen/board_info/sku\n");
1120                 else
1121                         bi->sku = prop_val;
1122
1123                 err = of_property_read_u32(board_info, "fab", &prop_val);
1124                 if (err)
1125                         pr_err("failed to read /chosen/board_info/fab\n");
1126                 else
1127                         bi->fab = prop_val;
1128
1129                 err = of_property_read_u32(board_info, "major_revision", &prop_val);
1130                 if (err)
1131                         pr_err("failed to read /chosen/board_info/major_revision\n");
1132                 else
1133                         bi->major_revision = prop_val;
1134
1135                 err = of_property_read_u32(board_info, "minor_revision", &prop_val);
1136                 if (err)
1137                         pr_err("failed to read /chosen/board_info/minor_revision\n");
1138                 else
1139                         bi->minor_revision = prop_val;
1140                 system_serial_high = (bi->board_id << 16) | bi->sku;
1141                 system_serial_low = (bi->fab << 24) |
1142                         (bi->major_revision << 16) | (bi->minor_revision << 8);
1143         } else {
1144 #endif
1145                 bi->board_id = (system_serial_high >> 16) & 0xFFFF;
1146                 bi->sku = (system_serial_high) & 0xFFFF;
1147                 bi->fab = (system_serial_low >> 24) & 0xFF;
1148                 bi->major_revision = (system_serial_low >> 16) & 0xFF;
1149                 bi->minor_revision = (system_serial_low >> 8) & 0xFF;
1150 #ifdef CONFIG_OF
1151         }
1152 #endif
1153 }
1154
1155 static int __init tegra_pmu_board_info(char *info)
1156 {
1157         char *p = info;
1158         pmu_board_info.board_id = memparse(p, &p);
1159         pmu_board_info.sku = memparse(p+1, &p);
1160         pmu_board_info.fab = memparse(p+1, &p);
1161         pmu_board_info.major_revision = memparse(p+1, &p);
1162         pmu_board_info.minor_revision = memparse(p+1, &p);
1163         return 1;
1164 }
1165
1166 void tegra_get_pmu_board_info(struct board_info *bi)
1167 {
1168         memcpy(bi, &pmu_board_info, sizeof(struct board_info));
1169 }
1170
1171 __setup("pmuboard=", tegra_pmu_board_info);
1172
1173 static int __init tegra_display_board_info(char *info)
1174 {
1175         char *p = info;
1176         display_board_info.board_id = memparse(p, &p);
1177         display_board_info.sku = memparse(p+1, &p);
1178         display_board_info.fab = memparse(p+1, &p);
1179         display_board_info.major_revision = memparse(p+1, &p);
1180         display_board_info.minor_revision = memparse(p+1, &p);
1181         return 1;
1182 }
1183
1184 void tegra_get_display_board_info(struct board_info *bi)
1185 {
1186         memcpy(bi, &display_board_info, sizeof(struct board_info));
1187 }
1188
1189 __setup("displayboard=", tegra_display_board_info);
1190
1191 static int __init tegra_camera_board_info(char *info)
1192 {
1193         char *p = info;
1194         camera_board_info.board_id = memparse(p, &p);
1195         camera_board_info.sku = memparse(p+1, &p);
1196         camera_board_info.fab = memparse(p+1, &p);
1197         camera_board_info.major_revision = memparse(p+1, &p);
1198         camera_board_info.minor_revision = memparse(p+1, &p);
1199         return 1;
1200 }
1201
1202 void tegra_get_camera_board_info(struct board_info *bi)
1203 {
1204         memcpy(bi, &camera_board_info, sizeof(struct board_info));
1205 }
1206
1207 __setup("cameraboard=", tegra_camera_board_info);
1208
1209 static int __init tegra_leftspeaker_board_info(char *info)
1210 {
1211         char *p = info;
1212         leftspeaker_board_info.board_id = memparse(p, &p);
1213         leftspeaker_board_info.sku = memparse(p+1, &p);
1214         leftspeaker_board_info.fab = memparse(p+1, &p);
1215         leftspeaker_board_info.major_revision = memparse(p+1, &p);
1216         leftspeaker_board_info.minor_revision = memparse(p+1, &p);
1217         return 1;
1218 }
1219
1220 void tegra_get_leftspeaker_board_info(struct board_info *bi)
1221 {
1222         memcpy(bi, &leftspeaker_board_info, sizeof(struct board_info));
1223 }
1224
1225 __setup("leftspeakerboard=", tegra_leftspeaker_board_info);
1226
1227 static int __init tegra_rightspeaker_board_info(char *info)
1228 {
1229         char *p = info;
1230         rightspeaker_board_info.board_id = memparse(p, &p);
1231         rightspeaker_board_info.sku = memparse(p+1, &p);
1232         rightspeaker_board_info.fab = memparse(p+1, &p);
1233         rightspeaker_board_info.major_revision = memparse(p+1, &p);
1234         rightspeaker_board_info.minor_revision = memparse(p+1, &p);
1235         return 1;
1236 }
1237
1238 void tegra_get_rightspeaker_board_info(struct board_info *bi)
1239 {
1240         memcpy(bi, &rightspeaker_board_info, sizeof(struct board_info));
1241 }
1242
1243 __setup("rightspeakerboard=", tegra_rightspeaker_board_info);
1244
1245 static int __init tegra_joystick_board_info(char *info)
1246 {
1247         char *p = info;
1248         joystick_board_info.board_id = memparse(p, &p);
1249         joystick_board_info.sku = memparse(p+1, &p);
1250         joystick_board_info.fab = memparse(p+1, &p);
1251         joystick_board_info.major_revision = memparse(p+1, &p);
1252         joystick_board_info.minor_revision = memparse(p+1, &p);
1253         return 1;
1254 }
1255
1256 void tegra_get_joystick_board_info(struct board_info *bi)
1257 {
1258         memcpy(bi, &joystick_board_info, sizeof(struct board_info));
1259 }
1260
1261 __setup("joystickboard=", tegra_joystick_board_info);
1262
1263 static int __init tegra_button_board_info(char *info)
1264 {
1265         char *p = info;
1266         button_board_info.board_id = memparse(p, &p);
1267         button_board_info.sku = memparse(p+1, &p);
1268         button_board_info.fab = memparse(p+1, &p);
1269         button_board_info.major_revision = memparse(p+1, &p);
1270         button_board_info.minor_revision = memparse(p+1, &p);
1271         return 1;
1272 }
1273
1274 void tegra_get_button_board_info(struct board_info *bi)
1275 {
1276         memcpy(bi, &button_board_info, sizeof(struct board_info));
1277 }
1278
1279 __setup("buttonboard=", tegra_button_board_info);
1280
1281 static int __init tegra_io_board_info(char *info)
1282 {
1283         char *p = info;
1284         io_board_info.board_id = memparse(p, &p);
1285         io_board_info.sku = memparse(p+1, &p);
1286         io_board_info.fab = memparse(p+1, &p);
1287         io_board_info.major_revision = memparse(p+1, &p);
1288         io_board_info.minor_revision = memparse(p+1, &p);
1289         return 1;
1290 }
1291
1292 void tegra_get_io_board_info(struct board_info *bi)
1293 {
1294         memcpy(bi, &io_board_info, sizeof(struct board_info));
1295 }
1296
1297 __setup("ioboard=", tegra_io_board_info);
1298
1299 static int __init tegra_modem_id(char *id)
1300 {
1301         char *p = id;
1302
1303         modem_id = memparse(p, &p);
1304         return 1;
1305 }
1306
1307 int tegra_get_modem_id(void)
1308 {
1309         return modem_id;
1310 }
1311
1312 __setup("modem_id=", tegra_modem_id);
1313
1314 static int __init tegra_usb_port_owner_info(char *id)
1315 {
1316         char *p = id;
1317
1318         usb_port_owner_info = memparse(p, &p);
1319         return 1;
1320 }
1321
1322 int tegra_get_usb_port_owner_info(void)
1323 {
1324         return usb_port_owner_info;
1325 }
1326
1327 __setup("usb_port_owner_info=", tegra_usb_port_owner_info);
1328
1329 static int __init tegra_commchip_id(char *id)
1330 {
1331         char *p = id;
1332
1333         if (get_option(&p, &commchip_id) != 1)
1334                 return 0;
1335         return 1;
1336 }
1337
1338 int tegra_get_commchip_id(void)
1339 {
1340         return commchip_id;
1341 }
1342
1343 __setup("commchip_id=", tegra_commchip_id);
1344
1345 int tegra_get_pmic_rst_reason(void)
1346 {
1347         return pmic_rst_reason;
1348 }
1349
1350 static int __init tegra_pmic_rst_reason(char *id)
1351 {
1352         char *p = id;
1353         pmic_rst_reason = memparse(p, &p);
1354         return 1;
1355 }
1356
1357 __setup("pmic_rst_reason=", tegra_pmic_rst_reason);
1358
1359 #ifdef CONFIG_ANDROID
1360 static bool androidboot_mode_charger;
1361
1362 bool get_androidboot_mode_charger(void)
1363 {
1364         return androidboot_mode_charger;
1365 }
1366 static int __init tegra_androidboot_mode(char *options)
1367 {
1368         if (!strcmp(options, "charger"))
1369                 androidboot_mode_charger = true;
1370         else
1371                 androidboot_mode_charger = false;
1372         return 1;
1373 }
1374 __setup("androidboot.mode=", tegra_androidboot_mode);
1375 #endif
1376
1377 /*
1378  * Tegra has a protected aperture that prevents access by most non-CPU
1379  * memory masters to addresses above the aperture value.  Enabling it
1380  * secures the CPU's memory from the GPU, except through the GART.
1381  */
1382 void __init tegra_protected_aperture_init(unsigned long aperture)
1383 {
1384 #ifndef CONFIG_NVMAP_ALLOW_SYSMEM
1385         void __iomem *mc_base = IO_ADDRESS(TEGRA_MC_BASE);
1386         pr_info("Enabling Tegra protected aperture at 0x%08lx\n", aperture);
1387         writel(aperture, mc_base + MC_SECURITY_CFG2);
1388 #else
1389         pr_err("Tegra protected aperture disabled because nvmap is using "
1390                 "system memory\n");
1391 #endif
1392 }
1393
1394 /*
1395  * Due to conflicting restrictions on the placement of the framebuffer,
1396  * the bootloader is likely to leave the framebuffer pointed at a location
1397  * in memory that is outside the grhost aperture.  This function will move
1398  * the framebuffer contents from a physical address that is anywhere (lowmem,
1399  * highmem, or outside the memory map) to a physical address that is outside
1400  * the memory map.
1401  */
1402 void __tegra_move_framebuffer(struct platform_device *pdev,
1403         unsigned long to, unsigned long from,
1404         unsigned long size)
1405 {
1406         struct page *page;
1407         void __iomem *to_io;
1408         void *from_virt;
1409         unsigned long i, addr[] = { to, from, };
1410
1411         BUG_ON(PAGE_ALIGN((unsigned long)to) != (unsigned long)to);
1412         BUG_ON(PAGE_ALIGN(from) != from);
1413         BUG_ON(PAGE_ALIGN(size) != size);
1414
1415         to_io = ioremap(to, size);
1416         if (!to_io) {
1417                 pr_err("%s: Failed to map target framebuffer\n", __func__);
1418                 return;
1419         }
1420
1421         if (pfn_valid(page_to_pfn(phys_to_page(from)))) {
1422                 for (i = 0 ; i < size; i += PAGE_SIZE) {
1423                         page = phys_to_page(from + i);
1424                         from_virt = kmap(page);
1425                         memcpy(to_io + i, from_virt, PAGE_SIZE);
1426                         kunmap(page);
1427                 }
1428         } else {
1429                 void __iomem *from_io = ioremap(from, size);
1430                 if (!from_io) {
1431                         pr_err("%s: Failed to map source framebuffer\n",
1432                                 __func__);
1433                         goto out;
1434                 }
1435
1436                 for (i = 0; i < size; i += 4)
1437                         writel(readl(from_io + i), to_io + i);
1438
1439                 iounmap(from_io);
1440         }
1441
1442         for (i = 0; i < ARRAY_SIZE(addr); i++)
1443                 dma_map_linear_at(NULL, addr[i], size, DMA_TO_DEVICE);
1444 out:
1445         iounmap(to_io);
1446 }
1447
1448 void __tegra_clear_framebuffer(struct platform_device *pdev,
1449                                unsigned long to, unsigned long size)
1450 {
1451         void __iomem *to_io;
1452         unsigned long i;
1453
1454         BUG_ON(PAGE_ALIGN((unsigned long)to) != (unsigned long)to);
1455         BUG_ON(PAGE_ALIGN(size) != size);
1456
1457         to_io = ioremap(to, size);
1458         if (!to_io) {
1459                 pr_err("%s: Failed to map target framebuffer\n", __func__);
1460                 return;
1461         }
1462
1463         if (pfn_valid(page_to_pfn(phys_to_page(to)))) {
1464                 for (i = 0 ; i < size; i += PAGE_SIZE)
1465                         memset(to_io + i, 0, PAGE_SIZE);
1466         } else {
1467                 for (i = 0; i < size; i += 4)
1468                         writel(0, to_io + i);
1469         }
1470         iounmap(to_io);
1471 }
1472
1473 void __init tegra_reserve(unsigned long carveout_size, unsigned long fb_size,
1474         unsigned long fb2_size)
1475 {
1476         const size_t avp_kernel_reserve = SZ_32M;
1477 #if !defined(CONFIG_TEGRA_AVP_KERNEL_ON_MMU) /* Tegra2 with AVP MMU */ && \
1478         !defined(CONFIG_TEGRA_AVP_KERNEL_ON_SMMU) /* Tegra3 & up with SMMU */
1479         /* Reserve hardcoded AVP kernel load area starting at 0xXe000000*/
1480         tegra_avp_kernel_size = SZ_1M;
1481         tegra_avp_kernel_start = memblock_end_of_DRAM() - avp_kernel_reserve;
1482         if (memblock_remove(tegra_avp_kernel_start, avp_kernel_reserve)) {
1483                 pr_err("Failed to remove AVP kernel load area %08lx@%08lx "
1484                                 "from memory map\n",
1485                         (unsigned long)avp_kernel_reserve,
1486                         tegra_avp_kernel_start);
1487                 tegra_avp_kernel_size = 0;
1488         }
1489 #endif
1490
1491         if (carveout_size) {
1492                 tegra_carveout_start = memblock_end_of_DRAM() - carveout_size;
1493                 if (memblock_remove(tegra_carveout_start, carveout_size)) {
1494                         pr_err("Failed to remove carveout %08lx@%08lx "
1495                                 "from memory map\n",
1496                                 carveout_size, tegra_carveout_start);
1497                         tegra_carveout_start = 0;
1498                         tegra_carveout_size = 0;
1499                 } else
1500                         tegra_carveout_size = carveout_size;
1501         }
1502
1503         if (fb2_size) {
1504                 tegra_fb2_start = memblock_end_of_DRAM() - fb2_size;
1505                 if (memblock_remove(tegra_fb2_start, fb2_size)) {
1506                         pr_err("Failed to remove second framebuffer "
1507                                 "%08lx@%08lx from memory map\n",
1508                                 fb2_size, tegra_fb2_start);
1509                         tegra_fb2_start = 0;
1510                         tegra_fb2_size = 0;
1511                 } else
1512                         tegra_fb2_size = fb2_size;
1513         }
1514
1515         if (fb_size) {
1516                 tegra_fb_start = memblock_end_of_DRAM() - fb_size;
1517                 if (memblock_remove(tegra_fb_start, fb_size)) {
1518                         pr_err("Failed to remove framebuffer %08lx@%08lx "
1519                                 "from memory map\n",
1520                                 fb_size, tegra_fb_start);
1521                         tegra_fb_start = 0;
1522                         tegra_fb_size = 0;
1523                 } else
1524                         tegra_fb_size = fb_size;
1525         }
1526
1527         if (tegra_fb_size)
1528                 tegra_grhost_aperture = tegra_fb_start;
1529
1530         if (tegra_fb2_size && tegra_fb2_start < tegra_grhost_aperture)
1531                 tegra_grhost_aperture = tegra_fb2_start;
1532
1533         if (tegra_carveout_size && tegra_carveout_start < tegra_grhost_aperture)
1534                 tegra_grhost_aperture = tegra_carveout_start;
1535
1536         if (tegra_lp0_vec_size &&
1537            (tegra_lp0_vec_start < memblock_end_of_DRAM())) {
1538                 if (memblock_reserve(tegra_lp0_vec_start, tegra_lp0_vec_size)) {
1539                         pr_err("Failed to reserve lp0_vec %08lx@%08lx\n",
1540                                 tegra_lp0_vec_size, tegra_lp0_vec_start);
1541                         tegra_lp0_vec_start = 0;
1542                         tegra_lp0_vec_size = 0;
1543                 }
1544                 tegra_lp0_vec_relocate = false;
1545         } else
1546                 tegra_lp0_vec_relocate = true;
1547
1548 #ifdef CONFIG_TEGRA_NVDUMPER
1549         if (nvdumper_reserved) {
1550                 if (memblock_reserve(nvdumper_reserved, NVDUMPER_RESERVED_SIZE)) {
1551                         pr_err("Failed to reserve nvdumper page %08lx@%08lx\n",
1552                                nvdumper_reserved, NVDUMPER_RESERVED_SIZE);
1553                         nvdumper_reserved = 0;
1554                 }
1555         }
1556 #endif
1557
1558 #ifdef CONFIG_TEGRA_USE_NCT
1559         if (tegra_nck_size &&
1560            (tegra_nck_start < memblock_end_of_DRAM())) {
1561                 if (memblock_reserve(tegra_nck_start, tegra_nck_size)) {
1562                         pr_err("Failed to reserve nck %08lx@%08lx\n",
1563                                 tegra_nck_size, tegra_nck_start);
1564                         tegra_nck_start = 0;
1565                         tegra_nck_size = 0;
1566                 }
1567         }
1568 #endif
1569
1570         /*
1571          * We copy the bootloader's framebuffer to the framebuffer allocated
1572          * above, and then free this one.
1573          * */
1574         if (tegra_bootloader_fb_size) {
1575                 tegra_bootloader_fb_size = PAGE_ALIGN(tegra_bootloader_fb_size);
1576                 if (memblock_reserve(tegra_bootloader_fb_start,
1577                                 tegra_bootloader_fb_size)) {
1578                         pr_err("Failed to reserve bootloader frame buffer "
1579                                 "%08lx@%08lx\n", tegra_bootloader_fb_size,
1580                                 tegra_bootloader_fb_start);
1581                         tegra_bootloader_fb_start = 0;
1582                         tegra_bootloader_fb_size = 0;
1583                 }
1584         }
1585
1586         if (tegra_bootloader_fb2_size) {
1587                 tegra_bootloader_fb2_size =
1588                                 PAGE_ALIGN(tegra_bootloader_fb2_size);
1589                 if (memblock_reserve(tegra_bootloader_fb2_start,
1590                                 tegra_bootloader_fb2_size)) {
1591                         pr_err("Failed to reserve bootloader fb2 %08lx@%08lx\n",
1592                                 tegra_bootloader_fb2_size,
1593                                 tegra_bootloader_fb2_start);
1594                         tegra_bootloader_fb2_start = 0;
1595                         tegra_bootloader_fb2_size = 0;
1596                 }
1597         }
1598
1599         pr_info("Tegra reserved memory:\n"
1600                 "LP0:                    %08lx - %08lx\n"
1601                 "Bootloader framebuffer: %08lx - %08lx\n"
1602                 "Bootloader framebuffer2: %08lx - %08lx\n"
1603                 "Framebuffer:            %08lx - %08lx\n"
1604                 "2nd Framebuffer:        %08lx - %08lx\n"
1605                 "Carveout:               %08lx - %08lx\n"
1606                 "Vpr:                    %08lx - %08lx\n"
1607                 "Tsec:                   %08lx - %08lx\n",
1608                 tegra_lp0_vec_start,
1609                 tegra_lp0_vec_size ?
1610                         tegra_lp0_vec_start + tegra_lp0_vec_size - 1 : 0,
1611                 tegra_bootloader_fb_start,
1612                 tegra_bootloader_fb_size ?
1613                  tegra_bootloader_fb_start + tegra_bootloader_fb_size - 1 : 0,
1614                 tegra_bootloader_fb2_start,
1615                 tegra_bootloader_fb2_size ?
1616                  tegra_bootloader_fb2_start + tegra_bootloader_fb2_size - 1 : 0,
1617                 tegra_fb_start,
1618                 tegra_fb_size ?
1619                         tegra_fb_start + tegra_fb_size - 1 : 0,
1620                 tegra_fb2_start,
1621                 tegra_fb2_size ?
1622                         tegra_fb2_start + tegra_fb2_size - 1 : 0,
1623                 tegra_carveout_start,
1624                 tegra_carveout_size ?
1625                         tegra_carveout_start + tegra_carveout_size - 1 : 0,
1626                 tegra_vpr_start,
1627                 tegra_vpr_size ?
1628                         tegra_vpr_start + tegra_vpr_size - 1 : 0,
1629                 tegra_tsec_start,
1630                 tegra_tsec_size ?
1631                         tegra_tsec_start + tegra_tsec_size - 1 : 0);
1632
1633         if (tegra_avp_kernel_size) {
1634                 /* Return excessive memory reserved for AVP kernel */
1635                 if (tegra_avp_kernel_size < avp_kernel_reserve)
1636                         memblock_add(
1637                                 tegra_avp_kernel_start + tegra_avp_kernel_size,
1638                                 avp_kernel_reserve - tegra_avp_kernel_size);
1639                 pr_info(
1640                 "AVP kernel: %08lx - %08lx\n",
1641                         tegra_avp_kernel_start,
1642                         tegra_avp_kernel_start + tegra_avp_kernel_size - 1);
1643         }
1644
1645 #ifdef CONFIG_TEGRA_NVDUMPER
1646         if (nvdumper_reserved) {
1647                 pr_info("Nvdumper:               %08lx - %08lx\n",
1648                         nvdumper_reserved,
1649                         nvdumper_reserved + NVDUMPER_RESERVED_SIZE - 1);
1650         }
1651 #endif
1652 #ifdef CONFIG_TEGRA_USE_NCT
1653         if (tegra_nck_size) {
1654                 pr_info("Nck:                    %08lx - %08lx\n",
1655                         tegra_nck_start,
1656                         tegra_nck_size ?
1657                                 tegra_nck_start + tegra_nck_size - 1 : 0);
1658         }
1659 #endif
1660 }
1661
1662 #ifdef CONFIG_ANDROID_RAM_CONSOLE
1663 static struct persistent_ram_descriptor desc = {
1664         .name = "ram_console",
1665 };
1666
1667 static struct persistent_ram ram = {
1668         .descs = &desc,
1669         .num_descs = 1,
1670 };
1671
1672 void __init tegra_ram_console_debug_reserve(unsigned long ram_console_size)
1673 {
1674         int ret;
1675
1676         ram.start = memblock_end_of_DRAM() - ram_console_size;
1677         ram.size = ram_console_size;
1678         ram.descs->size = ram_console_size;
1679
1680         INIT_LIST_HEAD(&ram.node);
1681
1682         ret = persistent_ram_early_init(&ram);
1683         if (ret)
1684                 goto fail;
1685
1686         return;
1687
1688 fail:
1689         pr_err("Failed to reserve memory block for ram console\n");
1690 }
1691
1692 static struct resource ram_console_resources[] = {
1693         {
1694                 .flags = IORESOURCE_MEM,
1695         },
1696 };
1697
1698 static struct platform_device ram_console_device = {
1699         .name           = "ram_console",
1700         .id             = -1,
1701         .num_resources  = ARRAY_SIZE(ram_console_resources),
1702         .resource       = ram_console_resources,
1703 };
1704
1705 void __init tegra_ram_console_debug_init(void)
1706 {
1707         int err;
1708
1709         err = platform_device_register(&ram_console_device);
1710         if (err)
1711                 pr_err("%s: ram console registration failed (%d)!\n",
1712                         __func__, err);
1713 }
1714 #endif
1715
1716 int __init tegra_register_fuse(void)
1717 {
1718         return platform_device_register(&tegra_fuse_device);
1719 }
1720
1721 void __init tegra_release_bootloader_fb(void)
1722 {
1723         /* Since bootloader fb is reserved in common.c, it is freed here. */
1724         if (tegra_bootloader_fb_size) {
1725                 if (memblock_free(tegra_bootloader_fb_start,
1726                                                 tegra_bootloader_fb_size))
1727                         pr_err("Failed to free bootloader fb.\n");
1728                 else
1729                         free_bootmem_late(tegra_bootloader_fb_start,
1730                                                 tegra_bootloader_fb_size);
1731         }
1732         if (tegra_bootloader_fb2_size) {
1733                 if (memblock_free(tegra_bootloader_fb2_start,
1734                                                 tegra_bootloader_fb2_size))
1735                         pr_err("Failed to free bootloader fb2.\n");
1736                 else
1737                         free_bootmem_late(tegra_bootloader_fb2_start,
1738                                                 tegra_bootloader_fb2_size);
1739         }
1740 }
1741
1742 static struct platform_device *pinmux_devices[] = {
1743         &tegra_gpio_device,
1744         &tegra_pinmux_device,
1745 };
1746
1747 void tegra_enable_pinmux(void)
1748 {
1749         platform_add_devices(pinmux_devices, ARRAY_SIZE(pinmux_devices));
1750 }
1751
1752 static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
1753         [TEGRA_REVISION_UNKNOWN] = "unknown",
1754         [TEGRA_REVISION_A01]     = "A01",
1755         [TEGRA_REVISION_A02]     = "A02",
1756         [TEGRA_REVISION_A03]     = "A03",
1757         [TEGRA_REVISION_A03p]    = "A03 prime",
1758         [TEGRA_REVISION_A04]     = "A04",
1759         [TEGRA_REVISION_A04p]    = "A04 prime",
1760         [TEGRA_REVISION_QT]      = "QT",
1761 };
1762
1763 static const char * __init tegra_get_revision(void)
1764 {
1765         return kasprintf(GFP_KERNEL, "%s", tegra_revision_name[tegra_revision]);
1766 }
1767
1768 static const char * __init tegra_get_family(void)
1769 {
1770         void __iomem *chip_id = IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804;
1771         u32 cid = readl(chip_id);
1772         cid = (cid >> 8) & 0xFF;
1773
1774         switch (cid) {
1775         case TEGRA_CHIPID_TEGRA2:
1776                 cid = 2;
1777                 break;
1778         case TEGRA_CHIPID_TEGRA3:
1779                 cid = 3;
1780                 break;
1781         case TEGRA_CHIPID_TEGRA11:
1782                 cid = 11;
1783                 break;
1784
1785         case TEGRA_CHIPID_UNKNOWN:
1786         default:
1787                 cid = 0;
1788         }
1789         return kasprintf(GFP_KERNEL, "Tegra%d", cid);
1790 }
1791
1792 static const char * __init tegra_get_soc_id(void)
1793 {
1794         int package_id = tegra_package_id();
1795         return kasprintf(GFP_KERNEL, "REV=%s:SKU=0x%x:PID=0x%x",
1796                 tegra_revision_name[tegra_revision], tegra_sku_id, package_id);
1797 }
1798
1799 static void __init tegra_soc_info_populate(struct soc_device_attribute
1800         *soc_dev_attr, const char *machine)
1801 {
1802         soc_dev_attr->soc_id = tegra_get_soc_id();
1803         soc_dev_attr->machine  = machine;
1804         soc_dev_attr->family   = tegra_get_family();
1805         soc_dev_attr->revision = tegra_get_revision();
1806 }
1807
1808 int __init tegra_soc_device_init(const char *machine)
1809 {
1810         struct soc_device *soc_dev;
1811         struct soc_device_attribute *soc_dev_attr;
1812
1813         soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
1814         if (!soc_dev_attr)
1815                 return -ENOMEM;
1816
1817         tegra_soc_info_populate(soc_dev_attr, machine);
1818
1819         soc_dev = soc_device_register(soc_dev_attr);
1820         if (IS_ERR_OR_NULL(soc_dev)) {
1821                 kfree(soc_dev_attr);
1822                 return -1;
1823         }
1824
1825         return 0;
1826 }
1827 struct arm_soc_desc tegra_soc_desc __initdata = {
1828         .name           = "NVIDIA Tegra",
1829         soc_smp_init_ops(tegra_soc_smp_init_ops)
1830         soc_smp_ops(tegra_soc_smp_ops)
1831 };