103634a9cec43de7060e39ff86a4025f25c2087e
[linux-2.6.git] / arch / arm / mach-tegra / common.c
1 /*
2  * arch/arm/mach-tegra/common.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Copyright (C) 2010-2011 NVIDIA Corporation
6  *
7  * Author:
8  *      Colin Cross <ccross@android.com>
9  *
10  * This software is licensed under the terms of the GNU General Public
11  * License version 2, as published by the Free Software Foundation, and
12  * may be copied, distributed, and modified under those terms.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  */
20
21 #include <linux/platform_device.h>
22 #include <linux/console.h>
23 #include <linux/init.h>
24 #include <linux/io.h>
25 #include <linux/clk.h>
26 #include <linux/delay.h>
27 #include <linux/highmem.h>
28 #include <linux/memblock.h>
29 #include <linux/bitops.h>
30 #include <linux/sched.h>
31
32 #include <asm/hardware/cache-l2x0.h>
33 #include <asm/system.h>
34
35 #include <mach/gpio.h>
36 #include <mach/iomap.h>
37 #include <mach/pinmux.h>
38 #include <mach/powergate.h>
39 #include <mach/system.h>
40
41 #include "apbio.h"
42 #include "board.h"
43 #include "clock.h"
44 #include "fuse.h"
45 #include "pm.h"
46 #include "reset.h"
47 #include "tegra_smmu.h"
48
49 #define MC_SECURITY_CFG2        0x7c
50
51 #define AHB_ARBITRATION_PRIORITY_CTRL           0x4
52 #define   AHB_PRIORITY_WEIGHT(x)        (((x) & 0x7) << 29)
53 #define   PRIORITY_SELECT_USB   BIT(6)
54 #define   PRIORITY_SELECT_USB2  BIT(18)
55 #define   PRIORITY_SELECT_USB3  BIT(17)
56
57 #define AHB_GIZMO_AHB_MEM               0xc
58 #define   ENB_FAST_REARBITRATE  BIT(2)
59 #define   DONT_SPLIT_AHB_WR     BIT(7)
60
61 #define AHB_GIZMO_USB           0x1c
62 #define AHB_GIZMO_USB2          0x78
63 #define AHB_GIZMO_USB3          0x7c
64 #define   IMMEDIATE     BIT(18)
65
66 #define AHB_MEM_PREFETCH_CFG3   0xe0
67 #define AHB_MEM_PREFETCH_CFG4   0xe4
68 #define AHB_MEM_PREFETCH_CFG1   0xec
69 #define AHB_MEM_PREFETCH_CFG2   0xf0
70 #define   PREFETCH_ENB  BIT(31)
71 #define   MST_ID(x)     (((x) & 0x1f) << 26)
72 #define   AHBDMA_MST_ID MST_ID(5)
73 #define   USB_MST_ID    MST_ID(6)
74 #define   USB2_MST_ID   MST_ID(18)
75 #define   USB3_MST_ID   MST_ID(17)
76 #define   ADDR_BNDRY(x) (((x) & 0xf) << 21)
77 #define   INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0)
78
79 unsigned long tegra_bootloader_fb_start;
80 unsigned long tegra_bootloader_fb_size;
81 unsigned long tegra_fb_start;
82 unsigned long tegra_fb_size;
83 unsigned long tegra_fb2_start;
84 unsigned long tegra_fb2_size;
85 unsigned long tegra_carveout_start;
86 unsigned long tegra_carveout_size;
87 unsigned long tegra_vpr_start;
88 unsigned long tegra_vpr_size;
89 unsigned long tegra_lp0_vec_start;
90 unsigned long tegra_lp0_vec_size;
91 bool tegra_lp0_vec_relocate;
92 unsigned long tegra_grhost_aperture = ~0ul;
93 static   bool is_tegra_debug_uart_hsport;
94 static struct board_info pmu_board_info;
95 static struct board_info display_board_info;
96 static struct board_info camera_board_info;
97
98 static int pmu_core_edp = 1200; /* default 1.2V EDP limit */
99 static int board_panel_type;
100 static enum power_supply_type pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
101
102 void (*arch_reset)(char mode, const char *cmd) = tegra_assert_system_reset;
103
104 #define NEVER_RESET 0
105
106 void tegra_assert_system_reset(char mode, const char *cmd)
107 {
108 #if defined(CONFIG_TEGRA_FPGA_PLATFORM) || NEVER_RESET
109         printk("tegra_assert_system_reset() ignored.....");
110         do { } while (1);
111 #else
112         void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0x00);
113         u32 reg;
114
115         /* use *_related to avoid spinlock since caches are off */
116         reg = readl_relaxed(reset);
117         reg |= 0x10;
118         writel_relaxed(reg, reset);
119 #endif
120 }
121 static int modem_id;
122 static int debug_uart_port_id;
123 static enum audio_codec_type audio_codec_name;
124 static int max_cpu_current;
125
126 /* WARNING: There is implicit client of pllp_out3 like i2c, uart, dsi
127  * and so this clock (pllp_out3) should never be disabled.
128  */
129 static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
130         /* name         parent          rate            enabled */
131         { "clk_m",      NULL,           0,              true },
132 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
133 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
134         { "pll_p",      NULL,           216000000,      true },
135         { "pll_p_out1", "pll_p",        28800000,       true },
136         { "pll_p_out2", "pll_p",        48000000,       true },
137         { "pll_p_out3", "pll_p",        72000000,       true },
138         { "pll_p_out4", "pll_p",        108000000,      true },
139         { "pll_m",      "clk_m",        0,              true },
140         { "pll_m_out1", "pll_m",        120000000,      true },
141         { "sclk",       "pll_c_out1",   40000000,       true },
142         { "hclk",       "sclk",         40000000,       true },
143         { "pclk",       "hclk",         40000000,       true },
144         { "mpe",        "pll_c",        0,              false },
145         { "epp",        "pll_c",        0,              false },
146         { "vi_sensor",  "pll_c",        0,              false },
147         { "vi",         "pll_c",        0,              false },
148         { "2d",         "pll_c",        0,              false },
149         { "3d",         "pll_c",        0,              false },
150 #else
151         { "pll_p",      NULL,           408000000,      true },
152         { "pll_p_out1", "pll_p",        9600000,        false },
153         { "pll_p_out2", "pll_p",        48000000,       false },
154         { "pll_p_out3", "pll_p",        102000000,      true },
155         { "pll_m_out1", "pll_m",        275000000,      false },
156         { "pll_p_out4", "pll_p",        102000000,      false },
157         { "sclk",       "pll_p_out4",   102000000,      true },
158         { "hclk",       "sclk",         102000000,      true },
159         { "pclk",       "hclk",         51000000,       true },
160 #endif
161 #else
162         { "pll_p",      NULL,           216000000,      true },
163         { "pll_p_out1", "pll_p",        28800000,       false },
164         { "pll_p_out2", "pll_p",        48000000,       false },
165         { "pll_p_out3", "pll_p",        72000000,       true },
166         { "pll_m_out1", "pll_m",        275000000,      true },
167         { "pll_c",      NULL,           ULONG_MAX,      false },
168         { "pll_c_out1", "pll_c",        208000000,      false },
169         { "pll_p_out4", "pll_p",        108000000,      false },
170         { "sclk",       "pll_p_out4",   108000000,      true },
171         { "hclk",       "sclk",         108000000,      true },
172         { "pclk",       "hclk",         54000000,       true },
173 #endif
174         { "csite",      NULL,           0,              true },
175         { "emc",        NULL,           0,              true },
176         { "cpu",        NULL,           0,              true },
177         { "kfuse",      NULL,           0,              true },
178         { "fuse",       NULL,           0,              true },
179         { "pll_u",      NULL,           480000000,      false },
180         { "sdmmc1",     "pll_p",        48000000,       false},
181         { "sdmmc3",     "pll_p",        48000000,       false},
182         { "sdmmc4",     "pll_p",        48000000,       false},
183 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
184         { "cbus",       "pll_c",        416000000,      false },
185         { "pll_c_out1", "pll_c",        208000000,      false },
186 #endif
187         { NULL,         NULL,           0,              0},
188 };
189
190 #if defined(CONFIG_TRUSTED_FOUNDATIONS) && defined(CONFIG_CACHE_L2X0)
191 static void tegra_cache_smc(bool enable, u32 arg)
192 {
193         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
194         bool need_affinity_switch;
195         bool can_switch_affinity;
196         bool l2x0_enabled;
197         cpumask_t local_cpu_mask;
198         cpumask_t saved_cpu_mask;
199         unsigned long flags;
200         long ret;
201
202         /*
203          * ISSUE : Some registers of PL310 controler must be written
204          *              from Secure context (and from CPU0)!
205          *
206          * When called form Normal we obtain an abort or do nothing.
207          * Instructions that must be called in Secure:
208          *      - Write to Control register (L2X0_CTRL==0x100)
209          *      - Write in Auxiliary controler (L2X0_AUX_CTRL==0x104)
210          *      - Invalidate all entries (L2X0_INV_WAY==0x77C),
211          *              mandatory at boot time.
212          *      - Tag and Data RAM Latency Control Registers
213          *              (0x108 & 0x10C) must be written in Secure.
214          */
215         need_affinity_switch = (smp_processor_id() != 0);
216         can_switch_affinity = !irqs_disabled();
217
218         WARN_ON(need_affinity_switch && !can_switch_affinity);
219         if (need_affinity_switch && can_switch_affinity) {
220                 cpu_set(0, local_cpu_mask);
221                 sched_getaffinity(0, &saved_cpu_mask);
222                 ret = sched_setaffinity(0, &local_cpu_mask);
223                 WARN_ON(ret != 0);
224         }
225
226         local_irq_save(flags);
227         l2x0_enabled = readl_relaxed(p + L2X0_CTRL) & 1;
228         if (enable && !l2x0_enabled)
229                 tegra_generic_smc(0xFFFFF100, 0x00000001, arg);
230         else if (!enable && l2x0_enabled)
231                 tegra_generic_smc(0xFFFFF100, 0x00000002, arg);
232         local_irq_restore(flags);
233
234         if (need_affinity_switch && can_switch_affinity) {
235                 ret = sched_setaffinity(0, &saved_cpu_mask);
236                 WARN_ON(ret != 0);
237         }
238 }
239
240 static void tegra_l2x0_disable(void)
241 {
242         unsigned long flags;
243         static u32 l2x0_way_mask;
244
245         if (!l2x0_way_mask) {
246                 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
247                 u32 aux_ctrl;
248                 u32 ways;
249
250                 aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
251                 ways = (aux_ctrl & (1 << 16)) ? 16 : 8;
252                 l2x0_way_mask = (1 << ways) - 1;
253         }
254
255         local_irq_save(flags);
256         tegra_cache_smc(false, l2x0_way_mask);
257         local_irq_restore(flags);
258 }
259 #endif  /* CONFIG_TRUSTED_FOUNDATIONS && defined(CONFIG_CACHE_L2X0) */
260
261 void tegra_init_cache(bool init)
262 {
263 #ifdef CONFIG_CACHE_L2X0
264         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
265         u32 aux_ctrl;
266         u32 speedo;
267         u32 tmp;
268
269 #ifdef CONFIG_TRUSTED_FOUNDATIONS
270         /* issue the SMC to enable the L2 */
271         aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
272         tegra_cache_smc(true, aux_ctrl);
273
274         /* after init, reread aux_ctrl and register handlers */
275         aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
276         l2x0_init(p, aux_ctrl, 0xFFFFFFFF);
277
278         /* override outer_disable() with our disable */
279         outer_cache.disable = tegra_l2x0_disable;
280 #else
281 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
282         writel_relaxed(0x331, p + L2X0_TAG_LATENCY_CTRL);
283         writel_relaxed(0x441, p + L2X0_DATA_LATENCY_CTRL);
284
285 #elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
286 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
287         /* PL310 RAM latency is CPU dependent. NOTE: Changes here
288            must also be reflected in __cortex_a9_l2x0_restart */
289
290         if (is_lp_cluster()) {
291                 writel(0x221, p + L2X0_TAG_LATENCY_CTRL);
292                 writel(0x221, p + L2X0_DATA_LATENCY_CTRL);
293         } else {
294                 /* relax l2-cache latency for speedos 4,5,6 (T33's chips) */
295                 speedo = tegra_cpu_speedo_id();
296                 if (speedo == 4 || speedo == 5 || speedo == 6) {
297                         writel(0x442, p + L2X0_TAG_LATENCY_CTRL);
298                         writel(0x552, p + L2X0_DATA_LATENCY_CTRL);
299                 } else {
300                         writel(0x441, p + L2X0_TAG_LATENCY_CTRL);
301                         writel(0x551, p + L2X0_DATA_LATENCY_CTRL);
302                 }
303         }
304 #else
305         writel(0x770, p + L2X0_TAG_LATENCY_CTRL);
306         writel(0x770, p + L2X0_DATA_LATENCY_CTRL);
307 #endif
308 #endif
309         aux_ctrl = readl(p + L2X0_CACHE_TYPE);
310         aux_ctrl = (aux_ctrl & 0x700) << (17-8);
311         aux_ctrl |= 0x7C000001;
312         if (init) {
313                 l2x0_init(p, aux_ctrl, 0x8200c3fe);
314         } else {
315                 tmp = aux_ctrl;
316                 aux_ctrl = readl(p + L2X0_AUX_CTRL);
317                 aux_ctrl &= 0x8200c3fe;
318                 aux_ctrl |= tmp;
319                 writel(aux_ctrl, p + L2X0_AUX_CTRL);
320         }
321         l2x0_enable();
322 #endif
323 #endif
324 }
325
326 static void __init tegra_init_power(void)
327 {
328 #ifdef CONFIG_ARCH_TEGRA_HAS_SATA
329         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_SATA);
330 #endif
331 #ifdef CONFIG_ARCH_TEGRA_HAS_PCIE
332         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_PCIE);
333 #endif
334 }
335
336 static inline unsigned long gizmo_readl(unsigned long offset)
337 {
338         return readl(IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
339 }
340
341 static inline void gizmo_writel(unsigned long value, unsigned long offset)
342 {
343         writel(value, IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
344 }
345
346 static void __init tegra_init_ahb_gizmo_settings(void)
347 {
348         unsigned long val;
349
350         val = gizmo_readl(AHB_GIZMO_AHB_MEM);
351         val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR;
352         gizmo_writel(val, AHB_GIZMO_AHB_MEM);
353
354         val = gizmo_readl(AHB_GIZMO_USB);
355         val |= IMMEDIATE;
356         gizmo_writel(val, AHB_GIZMO_USB);
357
358         val = gizmo_readl(AHB_GIZMO_USB2);
359         val |= IMMEDIATE;
360         gizmo_writel(val, AHB_GIZMO_USB2);
361
362         val = gizmo_readl(AHB_GIZMO_USB3);
363         val |= IMMEDIATE;
364         gizmo_writel(val, AHB_GIZMO_USB3);
365
366         val = gizmo_readl(AHB_ARBITRATION_PRIORITY_CTRL);
367         val |= PRIORITY_SELECT_USB | PRIORITY_SELECT_USB2 | PRIORITY_SELECT_USB3
368                                 | AHB_PRIORITY_WEIGHT(7);
369         gizmo_writel(val, AHB_ARBITRATION_PRIORITY_CTRL);
370
371         val = gizmo_readl(AHB_MEM_PREFETCH_CFG1);
372         val &= ~MST_ID(~0);
373         val |= PREFETCH_ENB | AHBDMA_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
374         gizmo_writel(val, AHB_MEM_PREFETCH_CFG1);
375
376         val = gizmo_readl(AHB_MEM_PREFETCH_CFG2);
377         val &= ~MST_ID(~0);
378         val |= PREFETCH_ENB | USB_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
379         gizmo_writel(val, AHB_MEM_PREFETCH_CFG2);
380
381         val = gizmo_readl(AHB_MEM_PREFETCH_CFG3);
382         val &= ~MST_ID(~0);
383         val |= PREFETCH_ENB | USB3_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
384         gizmo_writel(val, AHB_MEM_PREFETCH_CFG3);
385
386         val = gizmo_readl(AHB_MEM_PREFETCH_CFG4);
387         val &= ~MST_ID(~0);
388         val |= PREFETCH_ENB | USB2_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
389         gizmo_writel(val, AHB_MEM_PREFETCH_CFG4);
390 }
391
392 static bool console_flushed;
393
394 static void tegra_pm_flush_console(void)
395 {
396         if (console_flushed)
397                 return;
398         console_flushed = true;
399
400         pr_emerg("Restarting %s\n", linux_banner);
401         if (console_trylock()) {
402                 console_unlock();
403                 return;
404         }
405
406         mdelay(50);
407
408         local_irq_disable();
409         if (!console_trylock())
410                 pr_emerg("%s: Console was locked! Busting\n", __func__);
411         else
412                 pr_emerg("%s: Console was locked!\n", __func__);
413         console_unlock();
414 }
415
416 static void tegra_pm_restart(char mode, const char *cmd)
417 {
418         tegra_pm_flush_console();
419         arm_machine_restart(mode, cmd);
420 }
421
422 void __init tegra_init_early(void)
423 {
424         arm_pm_restart = tegra_pm_restart;
425 #ifndef CONFIG_SMP
426         /* For SMP system, initializing the reset handler here is too
427            late. For non-SMP systems, the function that calls the reset
428            handler initializer is not called, so do it here for non-SMP. */
429         tegra_cpu_reset_handler_init();
430 #endif
431         tegra_init_fuse();
432         tegra_gpio_resume_init();
433         tegra_init_clock();
434         tegra_init_pinmux();
435         tegra_clk_init_from_table(common_clk_init_table);
436         tegra_init_power();
437         tegra_init_cache(true);
438         tegra_init_ahb_gizmo_settings();
439 }
440
441 static int __init tegra_lp0_vec_arg(char *options)
442 {
443         char *p = options;
444
445         tegra_lp0_vec_size = memparse(p, &p);
446         if (*p == '@')
447                 tegra_lp0_vec_start = memparse(p+1, &p);
448         if (!tegra_lp0_vec_size || !tegra_lp0_vec_start) {
449                 tegra_lp0_vec_size = 0;
450                 tegra_lp0_vec_start = 0;
451         }
452
453         return 0;
454 }
455 early_param("lp0_vec", tegra_lp0_vec_arg);
456
457 static int __init tegra_bootloader_fb_arg(char *options)
458 {
459         char *p = options;
460
461         tegra_bootloader_fb_size = memparse(p, &p);
462         if (*p == '@')
463                 tegra_bootloader_fb_start = memparse(p+1, &p);
464
465         pr_info("Found tegra_fbmem: %08lx@%08lx\n",
466                 tegra_bootloader_fb_size, tegra_bootloader_fb_start);
467
468         return 0;
469 }
470 early_param("tegra_fbmem", tegra_bootloader_fb_arg);
471
472 static int __init tegra_vpr_arg(char *options)
473 {
474         char *p = options;
475
476         tegra_vpr_size = memparse(p, &p);
477         if (*p == '@')
478                 tegra_vpr_start = memparse(p+1, &p);
479         pr_info("Found vpr, start=0x%lx size=%lx",
480                 tegra_vpr_start, tegra_vpr_size);
481         return 0;
482 }
483 early_param("vpr", tegra_vpr_arg);
484
485 enum panel_type get_panel_type(void)
486 {
487         return board_panel_type;
488 }
489 static int __init tegra_board_panel_type(char *options)
490 {
491         if (!strcmp(options, "lvds"))
492                 board_panel_type = panel_type_lvds;
493         else if (!strcmp(options, "dsi"))
494                 board_panel_type = panel_type_dsi;
495         else
496                 return 0;
497         return 1;
498 }
499 __setup("panel=", tegra_board_panel_type);
500
501 enum power_supply_type get_power_supply_type(void)
502 {
503         return pow_supply_type;
504 }
505 static int __init tegra_board_power_supply_type(char *options)
506 {
507         if (!strcmp(options, "Adapter"))
508                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
509         if (!strcmp(options, "Mains"))
510                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
511         else if (!strcmp(options, "Battery"))
512                 pow_supply_type = POWER_SUPPLY_TYPE_BATTERY;
513         else
514                 return 0;
515         return 1;
516 }
517 __setup("power_supply=", tegra_board_power_supply_type);
518
519 int get_core_edp(void)
520 {
521         return pmu_core_edp;
522 }
523 static int __init tegra_pmu_core_edp(char *options)
524 {
525         char *p = options;
526         int core_edp = memparse(p, &p);
527         if (core_edp != 0)
528                 pmu_core_edp = core_edp;
529         return 0;
530 }
531 early_param("core_edp_mv", tegra_pmu_core_edp);
532
533 int get_maximum_cpu_current_supported(void)
534 {
535         return max_cpu_current;
536 }
537 static int __init tegra_max_cpu_current(char *options)
538 {
539         char *p = options;
540         max_cpu_current = memparse(p, &p);
541         return 1;
542 }
543 __setup("max_cpu_cur_ma=", tegra_max_cpu_current);
544
545 static int __init tegra_debug_uartport(char *info)
546 {
547         char *p = info;
548         unsigned long long port_id;
549         if (!strncmp(p, "hsport", 6))
550                 is_tegra_debug_uart_hsport = true;
551         else if (!strncmp(p, "lsport", 6))
552                 is_tegra_debug_uart_hsport = false;
553
554         if (p[6] == ',') {
555                 if (p[7] == '-') {
556                         debug_uart_port_id = -1;
557                 } else {
558                         port_id = memparse(p + 7, &p);
559                         debug_uart_port_id = (int) port_id;
560                 }
561         } else {
562                 debug_uart_port_id = -1;
563         }
564
565         return 1;
566 }
567
568 bool is_tegra_debug_uartport_hs(void)
569 {
570         return is_tegra_debug_uart_hsport;
571 }
572
573 int get_tegra_uart_debug_port_id(void)
574 {
575         return debug_uart_port_id;
576 }
577 __setup("debug_uartport=", tegra_debug_uartport);
578
579 static int __init tegra_audio_codec_type(char *info)
580 {
581         char *p = info;
582         if (!strncmp(p, "wm8903", 6))
583                 audio_codec_name = audio_codec_wm8903;
584         else
585                 audio_codec_name = audio_codec_none;
586
587         return 1;
588 }
589
590 enum audio_codec_type get_audio_codec_type(void)
591 {
592         return audio_codec_name;
593 }
594 __setup("audio_codec=", tegra_audio_codec_type);
595
596
597 void tegra_get_board_info(struct board_info *bi)
598 {
599         bi->board_id = (system_serial_high >> 16) & 0xFFFF;
600         bi->sku = (system_serial_high) & 0xFFFF;
601         bi->fab = (system_serial_low >> 24) & 0xFF;
602         bi->major_revision = (system_serial_low >> 16) & 0xFF;
603         bi->minor_revision = (system_serial_low >> 8) & 0xFF;
604 }
605
606 static int __init tegra_pmu_board_info(char *info)
607 {
608         char *p = info;
609         pmu_board_info.board_id = memparse(p, &p);
610         pmu_board_info.sku = memparse(p+1, &p);
611         pmu_board_info.fab = memparse(p+1, &p);
612         pmu_board_info.major_revision = memparse(p+1, &p);
613         pmu_board_info.minor_revision = memparse(p+1, &p);
614         return 1;
615 }
616
617 void tegra_get_pmu_board_info(struct board_info *bi)
618 {
619         memcpy(bi, &pmu_board_info, sizeof(struct board_info));
620 }
621
622 __setup("pmuboard=", tegra_pmu_board_info);
623
624 static int __init tegra_display_board_info(char *info)
625 {
626         char *p = info;
627         display_board_info.board_id = memparse(p, &p);
628         display_board_info.sku = memparse(p+1, &p);
629         display_board_info.fab = memparse(p+1, &p);
630         display_board_info.major_revision = memparse(p+1, &p);
631         display_board_info.minor_revision = memparse(p+1, &p);
632         return 1;
633 }
634
635 void tegra_get_display_board_info(struct board_info *bi)
636 {
637         memcpy(bi, &display_board_info, sizeof(struct board_info));
638 }
639
640 __setup("displayboard=", tegra_display_board_info);
641
642 static int __init tegra_camera_board_info(char *info)
643 {
644         char *p = info;
645         camera_board_info.board_id = memparse(p, &p);
646         camera_board_info.sku = memparse(p+1, &p);
647         camera_board_info.fab = memparse(p+1, &p);
648         camera_board_info.major_revision = memparse(p+1, &p);
649         camera_board_info.minor_revision = memparse(p+1, &p);
650         return 1;
651 }
652
653 void tegra_get_camera_board_info(struct board_info *bi)
654 {
655         memcpy(bi, &camera_board_info, sizeof(struct board_info));
656 }
657
658 __setup("cameraboard=", tegra_camera_board_info);
659
660 static int __init tegra_modem_id(char *id)
661 {
662         char *p = id;
663
664         modem_id = memparse(p, &p);
665         return 1;
666 }
667
668 int tegra_get_modem_id(void)
669 {
670         return modem_id;
671 }
672
673 __setup("modem_id=", tegra_modem_id);
674
675
676
677 /*
678  * Tegra has a protected aperture that prevents access by most non-CPU
679  * memory masters to addresses above the aperture value.  Enabling it
680  * secures the CPU's memory from the GPU, except through the GART.
681  */
682 void __init tegra_protected_aperture_init(unsigned long aperture)
683 {
684 #ifndef CONFIG_NVMAP_ALLOW_SYSMEM
685         void __iomem *mc_base = IO_ADDRESS(TEGRA_MC_BASE);
686         pr_info("Enabling Tegra protected aperture at 0x%08lx\n", aperture);
687         writel(aperture, mc_base + MC_SECURITY_CFG2);
688 #else
689         pr_err("Tegra protected aperture disabled because nvmap is using "
690                 "system memory\n");
691 #endif
692 }
693
694 /*
695  * Due to conflicting restrictions on the placement of the framebuffer,
696  * the bootloader is likely to leave the framebuffer pointed at a location
697  * in memory that is outside the grhost aperture.  This function will move
698  * the framebuffer contents from a physical address that is anywher (lowmem,
699  * highmem, or outside the memory map) to a physical address that is outside
700  * the memory map.
701  */
702 void tegra_move_framebuffer(unsigned long to, unsigned long from,
703         unsigned long size)
704 {
705         struct page *page;
706         void __iomem *to_io;
707         void *from_virt;
708         unsigned long i;
709
710         BUG_ON(PAGE_ALIGN((unsigned long)to) != (unsigned long)to);
711         BUG_ON(PAGE_ALIGN(from) != from);
712         BUG_ON(PAGE_ALIGN(size) != size);
713
714         to_io = ioremap(to, size);
715         if (!to_io) {
716                 pr_err("%s: Failed to map target framebuffer\n", __func__);
717                 return;
718         }
719
720         if (pfn_valid(page_to_pfn(phys_to_page(from)))) {
721                 for (i = 0 ; i < size; i += PAGE_SIZE) {
722                         page = phys_to_page(from + i);
723                         from_virt = kmap(page);
724                         memcpy(to_io + i, from_virt, PAGE_SIZE);
725                         kunmap(page);
726                 }
727         } else {
728                 void __iomem *from_io = ioremap(from, size);
729                 if (!from_io) {
730                         pr_err("%s: Failed to map source framebuffer\n",
731                                 __func__);
732                         goto out;
733                 }
734
735                 for (i = 0; i < size; i += 4)
736                         writel(readl(from_io + i), to_io + i);
737
738                 iounmap(from_io);
739         }
740 out:
741         iounmap(to_io);
742 }
743
744 #ifdef CONFIG_TEGRA_SMMU_BASE_AT_E0000000
745 #define FORCE_SMMU_BASE_FOR_TEGRA3_A01 1
746 #else
747 #define FORCE_SMMU_BASE_FOR_TEGRA3_A01 0
748 #endif
749 #if FORCE_SMMU_BASE_FOR_TEGRA3_A01 ||  \
750         (defined(CONFIG_TEGRA_IOVMM_SMMU) && defined(CONFIG_ARCH_TEGRA_3x_SOC))
751 /* Support for Tegra3 A01 chip mask that needs to have SMMU IOVA reside in
752  * the upper half of 4GB IOVA space. A02 and after use the bottom 1GB and
753  * do not need to reserve memory.
754  */
755 #define SUPPORT_SMMU_BASE_FOR_TEGRA3_A01
756 #endif
757
758 void __init tegra_reserve(unsigned long carveout_size, unsigned long fb_size,
759         unsigned long fb2_size)
760 {
761 #ifdef SUPPORT_SMMU_BASE_FOR_TEGRA3_A01
762         int smmu_reserved = 0;
763         struct tegra_smmu_window *smmu_window = tegra_smmu_window(0);
764 #endif
765
766         if (carveout_size) {
767                 tegra_carveout_start = memblock_end_of_DRAM() - carveout_size;
768                 if (memblock_remove(tegra_carveout_start, carveout_size)) {
769                         pr_err("Failed to remove carveout %08lx@%08lx "
770                                 "from memory map\n",
771                                 carveout_size, tegra_carveout_start);
772                         tegra_carveout_start = 0;
773                         tegra_carveout_size = 0;
774                 } else
775                         tegra_carveout_size = carveout_size;
776         }
777
778         if (fb2_size) {
779                 tegra_fb2_start = memblock_end_of_DRAM() - fb2_size;
780                 if (memblock_remove(tegra_fb2_start, fb2_size)) {
781                         pr_err("Failed to remove second framebuffer "
782                                 "%08lx@%08lx from memory map\n",
783                                 fb2_size, tegra_fb2_start);
784                         tegra_fb2_start = 0;
785                         tegra_fb2_size = 0;
786                 } else
787                         tegra_fb2_size = fb2_size;
788         }
789
790         if (fb_size) {
791                 tegra_fb_start = memblock_end_of_DRAM() - fb_size;
792                 if (memblock_remove(tegra_fb_start, fb_size)) {
793                         pr_err("Failed to remove framebuffer %08lx@%08lx "
794                                 "from memory map\n",
795                                 fb_size, tegra_fb_start);
796                         tegra_fb_start = 0;
797                         tegra_fb_size = 0;
798                 } else
799                         tegra_fb_size = fb_size;
800         }
801
802         if (tegra_fb_size)
803                 tegra_grhost_aperture = tegra_fb_start;
804
805         if (tegra_fb2_size && tegra_fb2_start < tegra_grhost_aperture)
806                 tegra_grhost_aperture = tegra_fb2_start;
807
808         if (tegra_carveout_size && tegra_carveout_start < tegra_grhost_aperture)
809                 tegra_grhost_aperture = tegra_carveout_start;
810
811 #ifdef SUPPORT_SMMU_BASE_FOR_TEGRA3_A01
812         if (!smmu_window) {
813                 pr_err("No SMMU resource\n");
814         } else {
815                 size_t smmu_window_size;
816
817                 if (FORCE_SMMU_BASE_FOR_TEGRA3_A01 ||
818                         (tegra_get_chipid() == TEGRA_CHIPID_TEGRA3 &&
819                         tegra_get_revision() == TEGRA_REVISION_A01)) {
820                         smmu_window->start = TEGRA_SMMU_BASE_TEGRA3_A01;
821                         smmu_window->end   = TEGRA_SMMU_BASE_TEGRA3_A01 +
822                                                 TEGRA_SMMU_SIZE_TEGRA3_A01 - 1;
823                 }
824                 smmu_window_size = smmu_window->end + 1 - smmu_window->start;
825                 if (smmu_window->start >= 0x80000000) {
826                         if (memblock_reserve(smmu_window->start,
827                                                 smmu_window_size))
828                                 pr_err(
829                         "Failed to reserve SMMU I/O VA window %08lx@%08lx\n",
830                                 (unsigned long)smmu_window_size,
831                                 (unsigned long)smmu_window->start);
832                         else
833                                 smmu_reserved = 1;
834                 }
835         }
836 #endif
837
838         if (tegra_lp0_vec_size &&
839            (tegra_lp0_vec_start < memblock_end_of_DRAM())) {
840                 if (memblock_reserve(tegra_lp0_vec_start, tegra_lp0_vec_size)) {
841                         pr_err("Failed to reserve lp0_vec %08lx@%08lx\n",
842                                 tegra_lp0_vec_size, tegra_lp0_vec_start);
843                         tegra_lp0_vec_start = 0;
844                         tegra_lp0_vec_size = 0;
845                 }
846                 tegra_lp0_vec_relocate = false;
847         } else
848                 tegra_lp0_vec_relocate = true;
849
850         /*
851          * We copy the bootloader's framebuffer to the framebuffer allocated
852          * above, and then free this one.
853          * */
854         if (tegra_bootloader_fb_size) {
855                 tegra_bootloader_fb_size = PAGE_ALIGN(tegra_bootloader_fb_size);
856                 if (memblock_reserve(tegra_bootloader_fb_start,
857                                 tegra_bootloader_fb_size)) {
858                         pr_err("Failed to reserve bootloader frame buffer "
859                                 "%08lx@%08lx\n", tegra_bootloader_fb_size,
860                                 tegra_bootloader_fb_start);
861                         tegra_bootloader_fb_start = 0;
862                         tegra_bootloader_fb_size = 0;
863                 }
864         }
865
866         pr_info("Tegra reserved memory:\n"
867                 "LP0:                    %08lx - %08lx\n"
868                 "Bootloader framebuffer: %08lx - %08lx\n"
869                 "Framebuffer:            %08lx - %08lx\n"
870                 "2nd Framebuffer:        %08lx - %08lx\n"
871                 "Carveout:               %08lx - %08lx\n"
872                 "Vpr:                    %08lx - %08lx\n",
873                 tegra_lp0_vec_start,
874                 tegra_lp0_vec_size ?
875                         tegra_lp0_vec_start + tegra_lp0_vec_size - 1 : 0,
876                 tegra_bootloader_fb_start,
877                 tegra_bootloader_fb_size ?
878                         tegra_bootloader_fb_start + tegra_bootloader_fb_size - 1 : 0,
879                 tegra_fb_start,
880                 tegra_fb_size ?
881                         tegra_fb_start + tegra_fb_size - 1 : 0,
882                 tegra_fb2_start,
883                 tegra_fb2_size ?
884                         tegra_fb2_start + tegra_fb2_size - 1 : 0,
885                 tegra_carveout_start,
886                 tegra_carveout_size ?
887                         tegra_carveout_start + tegra_carveout_size - 1 : 0,
888                 tegra_vpr_start,
889                 tegra_vpr_size ?
890                         tegra_vpr_start + tegra_vpr_size - 1 : 0);
891
892 #ifdef SUPPORT_SMMU_BASE_FOR_TEGRA3_A01
893         if (smmu_reserved)
894                 pr_info("SMMU:                   %08lx - %08lx\n",
895                         smmu_window->start, smmu_window->end);
896 #endif
897 }
898
899 void __init tegra_release_bootloader_fb(void)
900 {
901         /* Since bootloader fb is reserved in common.c, it is freed here. */
902         if (tegra_bootloader_fb_size)
903                 if (memblock_free(tegra_bootloader_fb_start,
904                                                 tegra_bootloader_fb_size))
905                         pr_err("Failed to free bootloader fb.\n");
906 }
907
908 #ifdef CONFIG_TEGRA_CONVSERVATIVE_GOV_ON_EARLYSUPSEND
909 static char cpufreq_gov_default[32];
910 static char *cpufreq_gov_conservative = "conservative";
911 static char *cpufreq_sysfs_place_holder="/sys/devices/system/cpu/cpu%i/cpufreq/scaling_governor";
912 static char *cpufreq_gov_conservative_param="/sys/devices/system/cpu/cpufreq/conservative/%s";
913
914 static void cpufreq_set_governor(char *governor)
915 {
916         struct file *scaling_gov = NULL;
917         mm_segment_t old_fs;
918         char    buf[128];
919         int i = 0;
920         loff_t offset = 0;
921
922         if (governor == NULL)
923                 return;
924
925         /* change to KERNEL_DS address limit */
926         old_fs = get_fs();
927         set_fs(KERNEL_DS);
928 #ifndef CONFIG_TEGRA_AUTO_HOTPLUG
929         for_each_online_cpu(i)
930 #endif
931         {
932                 sprintf(buf, cpufreq_sysfs_place_holder, i);
933                 scaling_gov = filp_open(buf, O_RDWR, 0);
934                 if (IS_ERR_OR_NULL(scaling_gov)) {
935                         pr_err("%s. Can't open %s\n", __func__, buf);
936                 } else {
937                         if (scaling_gov->f_op != NULL &&
938                                 scaling_gov->f_op->write != NULL)
939                                 scaling_gov->f_op->write(scaling_gov,
940                                                 governor,
941                                                 strlen(governor),
942                                                 &offset);
943                         else
944                                 pr_err("f_op might be null\n");
945
946                         filp_close(scaling_gov, NULL);
947                 }
948         }
949         set_fs(old_fs);
950 }
951
952 void cpufreq_save_default_governor(void)
953 {
954         struct file *scaling_gov = NULL;
955         mm_segment_t old_fs;
956         char    buf[128];
957         loff_t offset = 0;
958
959         /* change to KERNEL_DS address limit */
960         old_fs = get_fs();
961         set_fs(KERNEL_DS);
962
963         buf[127] = 0;
964         sprintf(buf, cpufreq_sysfs_place_holder,0);
965         scaling_gov = filp_open(buf, O_RDONLY, 0);
966         if (IS_ERR_OR_NULL(scaling_gov)) {
967                 pr_err("%s. Can't open %s\n", __func__, buf);
968         } else {
969                 if (scaling_gov->f_op != NULL &&
970                         scaling_gov->f_op->read != NULL)
971                         scaling_gov->f_op->read(scaling_gov,
972                                         cpufreq_gov_default,
973                                         32,
974                                         &offset);
975                 else
976                         pr_err("f_op might be null\n");
977
978                 filp_close(scaling_gov, NULL);
979         }
980         set_fs(old_fs);
981 }
982
983 void cpufreq_restore_default_governor(void)
984 {
985         cpufreq_set_governor(cpufreq_gov_default);
986 }
987
988 void cpufreq_set_conservative_governor_param(int up_th, int down_th)
989 {
990         struct file *gov_param = NULL;
991         static char buf[128],parm[8];
992         loff_t offset = 0;
993         mm_segment_t old_fs;
994
995         if (up_th <= down_th) {
996                 printk(KERN_ERR "%s: up_th(%d) is lesser than down_th(%d)\n",
997                         __func__, up_th, down_th);
998                 return;
999         }
1000
1001         /* change to KERNEL_DS address limit */
1002         old_fs = get_fs();
1003         set_fs(KERNEL_DS);
1004
1005         sprintf(parm, "%d", up_th);
1006         sprintf(buf, cpufreq_gov_conservative_param ,"up_threshold");
1007         gov_param = filp_open(buf, O_RDONLY, 0);
1008         if (IS_ERR_OR_NULL(gov_param)) {
1009                 pr_err("%s. Can't open %s\n", __func__, buf);
1010         } else {
1011                 if (gov_param->f_op != NULL &&
1012                         gov_param->f_op->write != NULL)
1013                         gov_param->f_op->write(gov_param,
1014                                         parm,
1015                                         strlen(parm),
1016                                         &offset);
1017                 else
1018                         pr_err("f_op might be null\n");
1019
1020                 filp_close(gov_param, NULL);
1021         }
1022
1023         sprintf(parm, "%d", down_th);
1024         sprintf(buf, cpufreq_gov_conservative_param ,"down_threshold");
1025         gov_param = filp_open(buf, O_RDONLY, 0);
1026         if (IS_ERR_OR_NULL(gov_param)) {
1027                 pr_err("%s. Can't open %s\n", __func__, buf);
1028         } else {
1029                 if (gov_param->f_op != NULL &&
1030                         gov_param->f_op->write != NULL)
1031                         gov_param->f_op->write(gov_param,
1032                                         parm,
1033                                         strlen(parm),
1034                                         &offset);
1035                 else
1036                         pr_err("f_op might be null\n");
1037
1038                 filp_close(gov_param, NULL);
1039         }
1040         set_fs(old_fs);
1041 }
1042
1043 void cpufreq_set_conservative_governor(void)
1044 {
1045         cpufreq_set_governor(cpufreq_gov_conservative);
1046 }
1047 #endif /* CONFIG_TEGRA_CONVSERVATIVE_GOV_ON_EARLYSUPSEND */