Ventana: KBC: Removing the KBC usage on ventana
[linux-2.6.git] / arch / arm / mach-tegra / board-whistler-memory.c
1 /*
2  * Copyright (C) 2011 NVIDIA, Inc.
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope that it will be useful,
9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11  * GNU General Public License for more details.
12  *
13  * You should have received a copy of the GNU General Public License
14  * along with this program; if not, write to the Free Software
15  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
16  * 02111-1307, USA
17  */
18
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21
22 #include "board-whistler.h"
23 #include "tegra2_emc.h"
24 #include "board.h"
25
26 static const struct tegra_emc_table whistler_emc_tables_elpida_300Mhz[] = {
27         {
28                 .rate = 25000,   /* SDRAM frquency */
29                 .regs = {
30                         0x00000002,   /* RC */
31                         0x00000006,   /* RFC */
32                         0x00000003,   /* RAS */
33                         0x00000003,   /* RP */
34                         0x00000006,   /* R2W */
35                         0x00000004,   /* W2R */
36                         0x00000002,   /* R2P */
37                         0x00000009,   /* W2P */
38                         0x00000003,   /* RD_RCD */
39                         0x00000003,   /* WR_RCD */
40                         0x00000002,   /* RRD */
41                         0x00000002,   /* REXT */
42                         0x00000002,   /* WDV */
43                         0x00000004,   /* QUSE */
44                         0x00000003,   /* QRST */
45                         0x00000008,   /* QSAFE */
46                         0x0000000b,   /* RDV */
47                         0x0000004d,   /* REFRESH */
48                         0x00000000,   /* BURST_REFRESH_NUM */
49                         0x00000003,   /* PDEX2WR */
50                         0x00000003,   /* PDEX2RD */
51                         0x00000003,   /* PCHG2PDEN */
52                         0x00000008,   /* ACT2PDEN */
53                         0x00000001,   /* AR2PDEN */
54                         0x0000000a,   /* RW2PDEN */
55                         0x00000004,   /* TXSR */
56                         0x00000003,   /* TCKE */
57                         0x00000008,   /* TFAW */
58                         0x00000004,   /* TRPAB */
59                         0x00000006,   /* TCLKSTABLE */
60                         0x00000002,   /* TCLKSTOP */
61                         0x00000068,   /* TREFBW */
62                         0x00000003,   /* QUSE_EXTRA */
63                         0x00000003,   /* FBIO_CFG6 */
64                         0x00000000,   /* ODT_WRITE */
65                         0x00000000,   /* ODT_READ */
66                         0x00000082,   /* FBIO_CFG5 */
67                         0xa06a04ae,   /* CFG_DIG_DLL */
68                         0x0001f000,   /* DLL_XFORM_DQS */
69                         0x00000000,   /* DLL_XFORM_QUSE */
70                         0x00000000,   /* ZCAL_REF_CNT */
71                         0x00000003,   /* ZCAL_WAIT_CNT */
72                         0x00000000,   /* AUTO_CAL_INTERVAL */
73                         0x00000000,   /* CFG_CLKTRIM_0 */
74                         0x00000000,   /* CFG_CLKTRIM_1 */
75                         0x00000000,   /* CFG_CLKTRIM_2 */
76                 }
77         },
78         {
79                 .rate = 50000,   /* SDRAM frequency */
80                 .regs = {
81                         0x00000003,   /* RC */
82                         0x00000007,   /* RFC */
83                         0x00000003,   /* RAS */
84                         0x00000003,   /* RP */
85                         0x00000006,   /* R2W */
86                         0x00000004,   /* W2R */
87                         0x00000002,   /* R2P */
88                         0x00000009,   /* W2P */
89                         0x00000003,   /* RD_RCD */
90                         0x00000003,   /* WR_RCD */
91                         0x00000002,   /* RRD */
92                         0x00000002,   /* REXT */
93                         0x00000002,   /* WDV */
94                         0x00000005,   /* QUSE */
95                         0x00000003,   /* QRST */
96                         0x00000008,   /* QSAFE */
97                         0x0000000b,   /* RDV */
98                         0x0000009f,   /* REFRESH */
99                         0x00000000,   /* BURST_REFRESH_NUM */
100                         0x00000003,   /* PDEX2WR */
101                         0x00000003,   /* PDEX2RD */
102                         0x00000003,   /* PCHG2PDEN */
103                         0x00000008,   /* ACT2PDEN */
104                         0x00000001,   /* AR2PDEN */
105                         0x0000000a,   /* RW2PDEN */
106                         0x00000007,   /* TXSR */
107                         0x00000003,   /* TCKE */
108                         0x00000008,   /* TFAW */
109                         0x00000004,   /* TRPAB */
110                         0x00000006,   /* TCLKSTABLE */
111                         0x00000002,   /* TCLKSTOP */
112                         0x000000d0,   /* TREFBW */
113                         0x00000004,   /* QUSE_EXTRA */
114                         0x00000000,   /* FBIO_CFG6 */
115                         0x00000000,   /* ODT_WRITE */
116                         0x00000000,   /* ODT_READ */
117                         0x00000082,   /* FBIO_CFG5 */
118                         0xa06a04ae,   /* CFG_DIG_DLL */
119                         0x0001f000,   /* DLL_XFORM_DQS */
120                         0x00000000,   /* DLL_XFORM_QUSE */
121                         0x00000000,   /* ZCAL_REF_CNT */
122                         0x00000005,   /* ZCAL_WAIT_CNT */
123                         0x00000000,   /* AUTO_CAL_INTERVAL */
124                         0x00000000,   /* CFG_CLKTRIM_0 */
125                         0x00000000,   /* CFG_CLKTRIM_1 */
126                         0x00000000,   /* CFG_CLKTRIM_2 */
127                 }
128         },
129         {
130                 .rate = 75000,   /* SDRAM frequency */
131                 .regs = {
132                         0x00000005,   /* RC */
133                         0x0000000a,   /* RFC */
134                         0x00000004,   /* RAS */
135                         0x00000003,   /* RP */
136                         0x00000006,   /* R2W */
137                         0x00000004,   /* W2R */
138                         0x00000002,   /* R2P */
139                         0x00000009,   /* W2P */
140                         0x00000003,   /* RD_RCD */
141                         0x00000003,   /* WR_RCD */
142                         0x00000002,   /* RRD */
143                         0x00000002,   /* REXT */
144                         0x00000002,   /* WDV */
145                         0x00000005,   /* QUSE */
146                         0x00000003,   /* QRST */
147                         0x00000008,   /* QSAFE */
148                         0x0000000b,   /* RDV */
149                         0x000000ff,   /* REFRESH */
150                         0x00000000,   /* BURST_REFRESH_NUM */
151                         0x00000003,   /* PDEX2WR */
152                         0x00000003,   /* PDEX2RD */
153                         0x00000003,   /* PCHG2PDEN */
154                         0x00000008,   /* ACT2PDEN */
155                         0x00000001,   /* AR2PDEN */
156                         0x0000000a,   /* RW2PDEN */
157                         0x0000000b,   /* TXSR */
158                         0x00000003,   /* TCKE */
159                         0x00000008,   /* TFAW */
160                         0x00000004,   /* TRPAB */
161                         0x00000006,   /* TCLKSTABLE */
162                         0x00000002,   /* TCLKSTOP */
163                         0x00000138,   /* TREFBW */
164                         0x00000004,   /* QUSE_EXTRA */
165                         0x00000000,   /* FBIO_CFG6 */
166                         0x00000000,   /* ODT_WRITE */
167                         0x00000000,   /* ODT_READ */
168                         0x00000082,   /* FBIO_CFG5 */
169                         0xa06a04ae,   /* CFG_DIG_DLL */
170                         0x0001f000,   /* DLL_XFORM_DQS */
171                         0x00000000,   /* DLL_XFORM_QUSE */
172                         0x00000000,   /* ZCAL_REF_CNT */
173                         0x00000007,   /* ZCAL_WAIT_CNT */
174                         0x00000000,   /* AUTO_CAL_INTERVAL */
175                         0x00000000,   /* CFG_CLKTRIM_0 */
176                         0x00000000,   /* CFG_CLKTRIM_1 */
177                         0x00000000,   /* CFG_CLKTRIM_2 */
178                 }
179         },
180         {
181                 .rate = 150000,   /* SDRAM frequency */
182                 .regs = {
183                         0x00000009,   /* RC */
184                         0x00000014,   /* RFC */
185                         0x00000007,   /* RAS */
186                         0x00000004,   /* RP */
187                         0x00000006,   /* R2W */
188                         0x00000004,   /* W2R */
189                         0x00000002,   /* R2P */
190                         0x00000009,   /* W2P */
191                         0x00000003,   /* RD_RCD */
192                         0x00000003,   /* WR_RCD */
193                         0x00000002,   /* RRD */
194                         0x00000002,   /* REXT */
195                         0x00000002,   /* WDV */
196                         0x00000005,   /* QUSE */
197                         0x00000003,   /* QRST */
198                         0x00000008,   /* QSAFE */
199                         0x0000000b,   /* RDV */
200                         0x0000021f,   /* REFRESH */
201                         0x00000000,   /* BURST_REFRESH_NUM */
202                         0x00000003,   /* PDEX2WR */
203                         0x00000003,   /* PDEX2RD */
204                         0x00000004,   /* PCHG2PDEN */
205                         0x00000008,   /* ACT2PDEN */
206                         0x00000001,   /* AR2PDEN */
207                         0x0000000a,   /* RW2PDEN */
208                         0x00000015,   /* TXSR */
209                         0x00000003,   /* TCKE */
210                         0x00000008,   /* TFAW */
211                         0x00000004,   /* TRPAB */
212                         0x00000006,   /* TCLKSTABLE */
213                         0x00000002,   /* TCLKSTOP */
214                         0x00000270,   /* TREFBW */
215                         0x00000000,   /* QUSE_EXTRA */
216                         0x00000001,   /* FBIO_CFG6 */
217                         0x00000000,   /* ODT_WRITE */
218                         0x00000000,   /* ODT_READ */
219                         0x00000082,   /* FBIO_CFG5 */
220                         0xA04C04AE,   /* CFG_DIG_DLL */
221                         0x007FC010,   /* DLL_XFORM_DQS */
222                         0x00000000,   /* DLL_XFORM_QUSE */
223                         0x00000000,   /* ZCAL_REF_CNT */
224                         0x0000000e,   /* ZCAL_WAIT_CNT */
225                         0x00000000,   /* AUTO_CAL_INTERVAL */
226                         0x00000000,   /* CFG_CLKTRIM_0 */
227                         0x00000000,   /* CFG_CLKTRIM_1 */
228                         0x00000000,   /* CFG_CLKTRIM_2 */
229                 }
230         },
231         {
232                 .rate = 300000,   /* SDRAM frequency */
233                 .regs = {
234                         0x00000012,   /* RC */
235                         0x00000027,   /* RFC */
236                         0x0000000D,   /* RAS */
237                         0x00000007,   /* RP */
238                         0x00000007,   /* R2W */
239                         0x00000005,   /* W2R */
240                         0x00000003,   /* R2P */
241                         0x00000009,   /* W2P */
242                         0x00000006,   /* RD_RCD */
243                         0x00000006,   /* WR_RCD */
244                         0x00000003,   /* RRD */
245                         0x00000003,   /* REXT */
246                         0x00000002,   /* WDV */
247                         0x00000006,   /* QUSE */
248                         0x00000003,   /* QRST */
249                         0x00000009,   /* QSAFE */
250                         0x0000000c,   /* RDV */
251                         0x0000045f,   /* REFRESH */
252                         0x00000000,   /* BURST_REFRESH_NUM */
253                         0x00000004,   /* PDEX2WR */
254                         0x00000004,   /* PDEX2RD */
255                         0x00000007,   /* PCHG2PDEN */
256                         0x00000008,   /* ACT2PDEN */
257                         0x00000001,   /* AR2PDEN */
258                         0x0000000e,   /* RW2PDEN */
259                         0x0000002A,   /* TXSR */
260                         0x00000003,   /* TCKE */
261                         0x0000000F,   /* TFAW */
262                         0x00000008,   /* TRPAB */
263                         0x00000005,   /* TCLKSTABLE */
264                         0x00000002,   /* TCLKSTOP */
265                         0x000004E1,   /* TREFBW */
266                         0x00000005,   /* QUSE_EXTRA */
267                         0x00000002,   /* FBIO_CFG6 */
268                         0x00000000,   /* ODT_WRITE */
269                         0x00000000,   /* ODT_READ */
270                         0x00000282,   /* FBIO_CFG5 */
271                         0xE03C048B,   /* CFG_DIG_DLL */
272                         0x007FC010,   /* DLL_XFORM_DQS */
273                         0x00000000,   /* DLL_XFORM_QUSE */
274                         0x00000000,   /* ZCAL_REF_CNT */
275                         0x0000001B,   /* ZCAL_WAIT_CNT */
276                         0x00000000,   /* AUTO_CAL_INTERVAL */
277                         0x00000000,   /* CFG_CLKTRIM_0 */
278                         0x00000000,   /* CFG_CLKTRIM_1 */
279                         0x00000000,   /* CFG_CLKTRIM_2 */
280                 }
281         }
282 };
283
284 static const struct tegra_emc_table whistler_emc_tables_elpida_400Mhz[] = {
285         {
286                 .rate = 23750,   /* SDRAM frquency */
287                 .regs = {
288                         0x00000002,   /* RC */
289                         0x00000006,   /* RFC */
290                         0x00000003,   /* RAS */
291                         0x00000003,   /* RP */
292                         0x00000006,   /* R2W */
293                         0x00000004,   /* W2R */
294                         0x00000002,   /* R2P */
295                         0x0000000b,   /* W2P */
296                         0x00000003,   /* RD_RCD */
297                         0x00000003,   /* WR_RCD */
298                         0x00000002,   /* RRD */
299                         0x00000002,   /* REXT */
300                         0x00000003,   /* WDV */
301                         0x00000005,   /* QUSE */
302                         0x00000004,   /* QRST */
303                         0x00000008,   /* QSAFE */
304                         0x0000000c,   /* RDV */
305                         0x00000047,   /* REFRESH */
306                         0x00000000,   /* BURST_REFRESH_NUM */
307                         0x00000003,   /* PDEX2WR */
308                         0x00000003,   /* PDEX2RD */
309                         0x00000003,   /* PCHG2PDEN */
310                         0x00000008,   /* ACT2PDEN */
311                         0x00000001,   /* AR2PDEN */
312                         0x0000000b,   /* RW2PDEN */
313                         0x00000004,   /* TXSR */
314                         0x00000003,   /* TCKE */
315                         0x00000008,   /* TFAW */
316                         0x00000004,   /* TRPAB */
317                         0x00000008,   /* TCLKSTABLE */
318                         0x00000002,   /* TCLKSTOP */
319                         0x00000060,   /* TREFBW */
320                         0x00000004,   /* QUSE_EXTRA */
321                         0x00000003,   /* FBIO_CFG6 */
322                         0x00000000,   /* ODT_WRITE */
323                         0x00000000,   /* ODT_READ */
324                         0x00000082,   /* FBIO_CFG5 */
325                         0xa0ae04ae,   /* CFG_DIG_DLL */
326                         0x0001f800,   /* DLL_XFORM_DQS */
327                         0x00000000,   /* DLL_XFORM_QUSE */
328                         0x00000000,   /* ZCAL_REF_CNT */
329                         0x00000003,   /* ZCAL_WAIT_CNT */
330                         0x00000000,   /* AUTO_CAL_INTERVAL */
331                         0x00000000,   /* CFG_CLKTRIM_0 */
332                         0x00000000,   /* CFG_CLKTRIM_1 */
333                         0x00000000,   /* CFG_CLKTRIM_2 */
334                 }
335         },
336         {
337                 .rate = 63333,   /* SDRAM frquency */
338                 .regs = {
339                         0x00000004,   /* RC */
340                         0x00000009,   /* RFC */
341                         0x00000003,   /* RAS */
342                         0x00000003,   /* RP */
343                         0x00000006,   /* R2W */
344                         0x00000004,   /* W2R */
345                         0x00000002,   /* R2P */
346                         0x0000000b,   /* W2P */
347                         0x00000003,   /* RD_RCD */
348                         0x00000003,   /* WR_RCD */
349                         0x00000002,   /* RRD */
350                         0x00000002,   /* REXT */
351                         0x00000003,   /* WDV */
352                         0x00000006,   /* QUSE */
353                         0x00000004,   /* QRST */
354                         0x00000008,   /* QSAFE */
355                         0x0000000c,   /* RDV */
356                         0x000000c4,   /* REFRESH */
357                         0x00000000,   /* BURST_REFRESH_NUM */
358                         0x00000003,   /* PDEX2WR */
359                         0x00000003,   /* PDEX2RD */
360                         0x00000003,   /* PCHG2PDEN */
361                         0x00000008,   /* ACT2PDEN */
362                         0x00000001,   /* AR2PDEN */
363                         0x0000000b,   /* RW2PDEN */
364                         0x00000009,   /* TXSR */
365                         0x00000003,   /* TCKE */
366                         0x00000008,   /* TFAW */
367                         0x00000004,   /* TRPAB */
368                         0x00000008,   /* TCLKSTABLE */
369                         0x00000002,   /* TCLKSTOP */
370                         0x00000107,   /* TREFBW */
371                         0x00000005,   /* QUSE_EXTRA */
372                         0x00000000,   /* FBIO_CFG6 */
373                         0x00000000,   /* ODT_WRITE */
374                         0x00000000,   /* ODT_READ */
375                         0x00000082,   /* FBIO_CFG5 */
376                         0xa0ae04ae,   /* CFG_DIG_DLL */
377                         0x0001f800,   /* DLL_XFORM_DQS */
378                         0x00000000,   /* DLL_XFORM_QUSE */
379                         0x00000000,   /* ZCAL_REF_CNT */
380                         0x00000006,   /* ZCAL_WAIT_CNT */
381                         0x00000000,   /* AUTO_CAL_INTERVAL */
382                         0x00000000,   /* CFG_CLKTRIM_0 */
383                         0x00000000,   /* CFG_CLKTRIM_1 */
384                         0x00000000,   /* CFG_CLKTRIM_2 */
385                 }
386         },
387         {
388                 .rate = 95000,   /* SDRAM frquency */
389                 .regs = {
390                         0x00000006,   /* RC */
391                         0x0000000d,   /* RFC */
392                         0x00000004,   /* RAS */
393                         0x00000003,   /* RP */
394                         0x00000006,   /* R2W */
395                         0x00000004,   /* W2R */
396                         0x00000002,   /* R2P */
397                         0x0000000b,   /* W2P */
398                         0x00000003,   /* RD_RCD */
399                         0x00000003,   /* WR_RCD */
400                         0x00000002,   /* RRD */
401                         0x00000002,   /* REXT */
402                         0x00000003,   /* WDV */
403                         0x00000006,   /* QUSE */
404                         0x00000004,   /* QRST */
405                         0x00000008,   /* QSAFE */
406                         0x0000000c,   /* RDV */
407                         0x0000013f,   /* REFRESH */
408                         0x00000000,   /* BURST_REFRESH_NUM */
409                         0x00000003,   /* PDEX2WR */
410                         0x00000003,   /* PDEX2RD */
411                         0x00000003,   /* PCHG2PDEN */
412                         0x00000008,   /* ACT2PDEN */
413                         0x00000001,   /* AR2PDEN */
414                         0x0000000b,   /* RW2PDEN */
415                         0x0000000e,   /* TXSR */
416                         0x00000003,   /* TCKE */
417                         0x00000008,   /* TFAW */
418                         0x00000004,   /* TRPAB */
419                         0x00000008,   /* TCLKSTABLE */
420                         0x00000002,   /* TCLKSTOP */
421                         0x0000018c,   /* TREFBW */
422                         0x00000005,   /* QUSE_EXTRA */
423                         0x00000001,   /* FBIO_CFG6 */
424                         0x00000000,   /* ODT_WRITE */
425                         0x00000000,   /* ODT_READ */
426                         0x00000082,   /* FBIO_CFG5 */
427                         0xa0ae04ae,   /* CFG_DIG_DLL */
428                         0x0001f000,   /* DLL_XFORM_DQS */
429                         0x00000000,   /* DLL_XFORM_QUSE */
430                         0x00000000,   /* ZCAL_REF_CNT */
431                         0x00000009,   /* ZCAL_WAIT_CNT */
432                         0x00000000,   /* AUTO_CAL_INTERVAL */
433                         0x00000000,   /* CFG_CLKTRIM_0 */
434                         0x00000000,   /* CFG_CLKTRIM_1 */
435                         0x00000000,   /* CFG_CLKTRIM_2 */
436                 }
437         },
438         {
439                 .rate = 190000,   /* SDRAM frquency */
440                 .regs = {
441                         0x0000000c,   /* RC */
442                         0x00000019,   /* RFC */
443                         0x00000008,   /* RAS */
444                         0x00000004,   /* RP */
445                         0x00000007,   /* R2W */
446                         0x00000004,   /* W2R */
447                         0x00000002,   /* R2P */
448                         0x0000000b,   /* W2P */
449                         0x00000004,   /* RD_RCD */
450                         0x00000004,   /* WR_RCD */
451                         0x00000002,   /* RRD */
452                         0x00000003,   /* REXT */
453                         0x00000003,   /* WDV */
454                         0x00000006,   /* QUSE */
455                         0x00000004,   /* QRST */
456                         0x00000009,   /* QSAFE */
457                         0x0000000d,   /* RDV */
458                         0x000002bf,   /* REFRESH */
459                         0x00000000,   /* BURST_REFRESH_NUM */
460                         0x00000003,   /* PDEX2WR */
461                         0x00000003,   /* PDEX2RD */
462                         0x00000004,   /* PCHG2PDEN */
463                         0x00000008,   /* ACT2PDEN */
464                         0x00000001,   /* AR2PDEN */
465                         0x0000000c,   /* RW2PDEN */
466                         0x0000001b,   /* TXSR */
467                         0x00000003,   /* TCKE */
468                         0x0000000a,   /* TFAW */
469                         0x00000004,   /* TRPAB */
470                         0x00000008,   /* TCLKSTABLE */
471                         0x00000002,   /* TCLKSTOP */
472                         0x00000317,   /* TREFBW */
473                         0x00000005,   /* QUSE_EXTRA */
474                         0x00000002,   /* FBIO_CFG6 */
475                         0x00000000,   /* ODT_WRITE */
476                         0x00000000,   /* ODT_READ */
477                         0x00000082,   /* FBIO_CFG5 */
478                         0xa06204ae,   /* CFG_DIG_DLL */
479                         0x007f7010,   /* DLL_XFORM_DQS */
480                         0x00000000,   /* DLL_XFORM_QUSE */
481                         0x00000000,   /* ZCAL_REF_CNT */
482                         0x00000012,   /* ZCAL_WAIT_CNT */
483                         0x00000000,   /* AUTO_CAL_INTERVAL */
484                         0x00000000,   /* CFG_CLKTRIM_0 */
485                         0x00000000,   /* CFG_CLKTRIM_1 */
486                         0x00000000,   /* CFG_CLKTRIM_2 */
487                 }
488         },
489         {
490                 .rate = 380000,   /* SDRAM frquency */
491                 .regs = {
492                         0x00000017,   /* RC */
493                         0x00000032,   /* RFC */
494                         0x00000010,   /* RAS */
495                         0x00000007,   /* RP */
496                         0x00000008,   /* R2W */
497                         0x00000005,   /* W2R */
498                         0x00000003,   /* R2P */
499                         0x0000000b,   /* W2P */
500                         0x00000007,   /* RD_RCD */
501                         0x00000007,   /* WR_RCD */
502                         0x00000004,   /* RRD */
503                         0x00000003,   /* REXT */
504                         0x00000003,   /* WDV */
505                         0x00000007,   /* QUSE */
506                         0x00000004,   /* QRST */
507                         0x0000000a,   /* QSAFE */
508                         0x0000000e,   /* RDV */
509                         0x0000059f,   /* REFRESH */
510                         0x00000000,   /* BURST_REFRESH_NUM */
511                         0x00000004,   /* PDEX2WR */
512                         0x00000004,   /* PDEX2RD */
513                         0x00000007,   /* PCHG2PDEN */
514                         0x00000008,   /* ACT2PDEN */
515                         0x00000001,   /* AR2PDEN */
516                         0x00000011,   /* RW2PDEN */
517                         0x00000036,   /* TXSR */
518                         0x00000003,   /* TCKE */
519                         0x00000013,   /* TFAW */
520                         0x00000008,   /* TRPAB */
521                         0x00000007,   /* TCLKSTABLE */
522                         0x00000002,   /* TCLKSTOP */
523                         0x0000062d,   /* TREFBW */
524                         0x00000006,   /* QUSE_EXTRA */
525                         0x00000003,   /* FBIO_CFG6 */
526                         0x00000000,   /* ODT_WRITE */
527                         0x00000000,   /* ODT_READ */
528                         0x00000282,   /* FBIO_CFG5 */
529                         0xe044048b,   /* CFG_DIG_DLL */
530                         0x007fb010,   /* DLL_XFORM_DQS */
531                         0x00000000,   /* DLL_XFORM_QUSE */
532                         0x00000000,   /* ZCAL_REF_CNT */
533                         0x00000023,   /* ZCAL_WAIT_CNT */
534                         0x00000000,   /* AUTO_CAL_INTERVAL */
535                         0x00000000,   /* CFG_CLKTRIM_0 */
536                         0x00000000,   /* CFG_CLKTRIM_1 */
537                         0x00000000,   /* CFG_CLKTRIM_2 */
538                 }
539         }
540 };
541
542 static const struct tegra_emc_chip whistler_emc_chips[] = {
543         {
544                 .description = "Elpida 300MHz",
545                 .mem_manufacturer_id = 0x0303,
546                 .mem_revision_id1 = 0,
547                 .mem_revision_id2 = 0,
548                 .mem_pid = 0x1414,
549                 .table = whistler_emc_tables_elpida_300Mhz,
550                 .table_size = ARRAY_SIZE(whistler_emc_tables_elpida_300Mhz)
551         },
552         {
553                 .description = "Elpida 300MHz",
554                 .mem_manufacturer_id = 0x0303,
555                 .mem_revision_id1 = 0,
556                 .mem_revision_id2 = 0,
557                 .mem_pid = 0x5454,
558                 .table = whistler_emc_tables_elpida_300Mhz,
559                 .table_size = ARRAY_SIZE(whistler_emc_tables_elpida_300Mhz)
560         },
561 };
562
563 int __init whistler_emc_init(void)
564 {
565         tegra_init_emc(whistler_emc_chips,
566                 ARRAY_SIZE(whistler_emc_chips));
567
568         return 0;
569 }