ARM: Tegra: fix compilation warnings
[linux-2.6.git] / arch / arm / mach-tegra / board-ventana-memory.c
1 /*
2  * Copyright (C) 2010-2011 NVIDIA, Inc.
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope that it will be useful,
9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11  * GNU General Public License for more details.
12  *
13  * You should have received a copy of the GNU General Public License
14  * along with this program; if not, write to the Free Software
15  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
16  * 02111-1307, USA
17  */
18
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/platform_data/tegra_emc.h>
22
23 #include "board-ventana.h"
24 #include "tegra2_emc.h"
25 #include "board.h"
26 #include "devices.h"
27
28 static const struct tegra_emc_table ventana_emc_tables_elpida_300Mhz[] = {
29         {
30                 .rate = 25000,   /* SDRAM frquency */
31                 .regs = {
32                         0x00000002,   /* RC */
33                         0x00000006,   /* RFC */
34                         0x00000003,   /* RAS */
35                         0x00000003,   /* RP */
36                         0x00000006,   /* R2W */
37                         0x00000004,   /* W2R */
38                         0x00000002,   /* R2P */
39                         0x00000009,   /* W2P */
40                         0x00000003,   /* RD_RCD */
41                         0x00000003,   /* WR_RCD */
42                         0x00000002,   /* RRD */
43                         0x00000002,   /* REXT */
44                         0x00000002,   /* WDV */
45                         0x00000004,   /* QUSE */
46                         0x00000003,   /* QRST */
47                         0x00000008,   /* QSAFE */
48                         0x0000000b,   /* RDV */
49                         0x0000004d,   /* REFRESH */
50                         0x00000000,   /* BURST_REFRESH_NUM */
51                         0x00000003,   /* PDEX2WR */
52                         0x00000003,   /* PDEX2RD */
53                         0x00000003,   /* PCHG2PDEN */
54                         0x00000008,   /* ACT2PDEN */
55                         0x00000001,   /* AR2PDEN */
56                         0x0000000a,   /* RW2PDEN */
57                         0x00000004,   /* TXSR */
58                         0x00000003,   /* TCKE */
59                         0x00000008,   /* TFAW */
60                         0x00000004,   /* TRPAB */
61                         0x00000006,   /* TCLKSTABLE */
62                         0x00000002,   /* TCLKSTOP */
63                         0x00000068,   /* TREFBW */
64                         0x00000003,   /* QUSE_EXTRA */
65                         0x00000003,   /* FBIO_CFG6 */
66                         0x00000000,   /* ODT_WRITE */
67                         0x00000000,   /* ODT_READ */
68                         0x00000082,   /* FBIO_CFG5 */
69                         0xa06a04ae,   /* CFG_DIG_DLL */
70                         0x0001f000,   /* DLL_XFORM_DQS */
71                         0x00000000,   /* DLL_XFORM_QUSE */
72                         0x00000000,   /* ZCAL_REF_CNT */
73                         0x00000003,   /* ZCAL_WAIT_CNT */
74                         0x00000000,   /* AUTO_CAL_INTERVAL */
75                         0x00000000,   /* CFG_CLKTRIM_0 */
76                         0x00000000,   /* CFG_CLKTRIM_1 */
77                         0x00000000,   /* CFG_CLKTRIM_2 */
78                 }
79         },
80         {
81                 .rate = 50000,   /* SDRAM frequency */
82                 .regs = {
83                         0x00000003,   /* RC */
84                         0x00000007,   /* RFC */
85                         0x00000003,   /* RAS */
86                         0x00000003,   /* RP */
87                         0x00000006,   /* R2W */
88                         0x00000004,   /* W2R */
89                         0x00000002,   /* R2P */
90                         0x00000009,   /* W2P */
91                         0x00000003,   /* RD_RCD */
92                         0x00000003,   /* WR_RCD */
93                         0x00000002,   /* RRD */
94                         0x00000002,   /* REXT */
95                         0x00000002,   /* WDV */
96                         0x00000005,   /* QUSE */
97                         0x00000003,   /* QRST */
98                         0x00000008,   /* QSAFE */
99                         0x0000000b,   /* RDV */
100                         0x0000009f,   /* REFRESH */
101                         0x00000000,   /* BURST_REFRESH_NUM */
102                         0x00000003,   /* PDEX2WR */
103                         0x00000003,   /* PDEX2RD */
104                         0x00000003,   /* PCHG2PDEN */
105                         0x00000008,   /* ACT2PDEN */
106                         0x00000001,   /* AR2PDEN */
107                         0x0000000a,   /* RW2PDEN */
108                         0x00000007,   /* TXSR */
109                         0x00000003,   /* TCKE */
110                         0x00000008,   /* TFAW */
111                         0x00000004,   /* TRPAB */
112                         0x00000006,   /* TCLKSTABLE */
113                         0x00000002,   /* TCLKSTOP */
114                         0x000000d0,   /* TREFBW */
115                         0x00000004,   /* QUSE_EXTRA */
116                         0x00000000,   /* FBIO_CFG6 */
117                         0x00000000,   /* ODT_WRITE */
118                         0x00000000,   /* ODT_READ */
119                         0x00000082,   /* FBIO_CFG5 */
120                         0xa06a04ae,   /* CFG_DIG_DLL */
121                         0x0001f000,   /* DLL_XFORM_DQS */
122                         0x00000000,   /* DLL_XFORM_QUSE */
123                         0x00000000,   /* ZCAL_REF_CNT */
124                         0x00000005,   /* ZCAL_WAIT_CNT */
125                         0x00000000,   /* AUTO_CAL_INTERVAL */
126                         0x00000000,   /* CFG_CLKTRIM_0 */
127                         0x00000000,   /* CFG_CLKTRIM_1 */
128                         0x00000000,   /* CFG_CLKTRIM_2 */
129                 }
130         },
131         {
132                 .rate = 75000,   /* SDRAM frequency */
133                 .regs = {
134                         0x00000005,   /* RC */
135                         0x0000000a,   /* RFC */
136                         0x00000004,   /* RAS */
137                         0x00000003,   /* RP */
138                         0x00000006,   /* R2W */
139                         0x00000004,   /* W2R */
140                         0x00000002,   /* R2P */
141                         0x00000009,   /* W2P */
142                         0x00000003,   /* RD_RCD */
143                         0x00000003,   /* WR_RCD */
144                         0x00000002,   /* RRD */
145                         0x00000002,   /* REXT */
146                         0x00000002,   /* WDV */
147                         0x00000005,   /* QUSE */
148                         0x00000003,   /* QRST */
149                         0x00000008,   /* QSAFE */
150                         0x0000000b,   /* RDV */
151                         0x000000ff,   /* REFRESH */
152                         0x00000000,   /* BURST_REFRESH_NUM */
153                         0x00000003,   /* PDEX2WR */
154                         0x00000003,   /* PDEX2RD */
155                         0x00000003,   /* PCHG2PDEN */
156                         0x00000008,   /* ACT2PDEN */
157                         0x00000001,   /* AR2PDEN */
158                         0x0000000a,   /* RW2PDEN */
159                         0x0000000b,   /* TXSR */
160                         0x00000003,   /* TCKE */
161                         0x00000008,   /* TFAW */
162                         0x00000004,   /* TRPAB */
163                         0x00000006,   /* TCLKSTABLE */
164                         0x00000002,   /* TCLKSTOP */
165                         0x00000138,   /* TREFBW */
166                         0x00000004,   /* QUSE_EXTRA */
167                         0x00000000,   /* FBIO_CFG6 */
168                         0x00000000,   /* ODT_WRITE */
169                         0x00000000,   /* ODT_READ */
170                         0x00000082,   /* FBIO_CFG5 */
171                         0xa06a04ae,   /* CFG_DIG_DLL */
172                         0x0001f000,   /* DLL_XFORM_DQS */
173                         0x00000000,   /* DLL_XFORM_QUSE */
174                         0x00000000,   /* ZCAL_REF_CNT */
175                         0x00000007,   /* ZCAL_WAIT_CNT */
176                         0x00000000,   /* AUTO_CAL_INTERVAL */
177                         0x00000000,   /* CFG_CLKTRIM_0 */
178                         0x00000000,   /* CFG_CLKTRIM_1 */
179                         0x00000000,   /* CFG_CLKTRIM_2 */
180                 }
181         },
182         {
183                 .rate = 150000,   /* SDRAM frequency */
184                 .regs = {
185                         0x00000009,   /* RC */
186                         0x00000014,   /* RFC */
187                         0x00000007,   /* RAS */
188                         0x00000004,   /* RP */
189                         0x00000006,   /* R2W */
190                         0x00000004,   /* W2R */
191                         0x00000002,   /* R2P */
192                         0x00000009,   /* W2P */
193                         0x00000003,   /* RD_RCD */
194                         0x00000003,   /* WR_RCD */
195                         0x00000002,   /* RRD */
196                         0x00000002,   /* REXT */
197                         0x00000002,   /* WDV */
198                         0x00000005,   /* QUSE */
199                         0x00000003,   /* QRST */
200                         0x00000008,   /* QSAFE */
201                         0x0000000b,   /* RDV */
202                         0x0000021f,   /* REFRESH */
203                         0x00000000,   /* BURST_REFRESH_NUM */
204                         0x00000003,   /* PDEX2WR */
205                         0x00000003,   /* PDEX2RD */
206                         0x00000004,   /* PCHG2PDEN */
207                         0x00000008,   /* ACT2PDEN */
208                         0x00000001,   /* AR2PDEN */
209                         0x0000000a,   /* RW2PDEN */
210                         0x00000015,   /* TXSR */
211                         0x00000003,   /* TCKE */
212                         0x00000008,   /* TFAW */
213                         0x00000004,   /* TRPAB */
214                         0x00000006,   /* TCLKSTABLE */
215                         0x00000002,   /* TCLKSTOP */
216                         0x00000270,   /* TREFBW */
217                         0x00000000,   /* QUSE_EXTRA */
218                         0x00000001,   /* FBIO_CFG6 */
219                         0x00000000,   /* ODT_WRITE */
220                         0x00000000,   /* ODT_READ */
221                         0x00000082,   /* FBIO_CFG5 */
222                         0xA04C04AE,   /* CFG_DIG_DLL */
223                         0x007FC010,   /* DLL_XFORM_DQS */
224                         0x00000000,   /* DLL_XFORM_QUSE */
225                         0x00000000,   /* ZCAL_REF_CNT */
226                         0x0000000e,   /* ZCAL_WAIT_CNT */
227                         0x00000000,   /* AUTO_CAL_INTERVAL */
228                         0x00000000,   /* CFG_CLKTRIM_0 */
229                         0x00000000,   /* CFG_CLKTRIM_1 */
230                         0x00000000,   /* CFG_CLKTRIM_2 */
231                 }
232         },
233         {
234                 .rate = 300000,   /* SDRAM frequency */
235                 .regs = {
236                         0x00000012,   /* RC */
237                         0x00000027,   /* RFC */
238                         0x0000000D,   /* RAS */
239                         0x00000007,   /* RP */
240                         0x00000007,   /* R2W */
241                         0x00000005,   /* W2R */
242                         0x00000003,   /* R2P */
243                         0x00000009,   /* W2P */
244                         0x00000006,   /* RD_RCD */
245                         0x00000006,   /* WR_RCD */
246                         0x00000003,   /* RRD */
247                         0x00000003,   /* REXT */
248                         0x00000002,   /* WDV */
249                         0x00000006,   /* QUSE */
250                         0x00000003,   /* QRST */
251                         0x00000009,   /* QSAFE */
252                         0x0000000c,   /* RDV */
253                         0x0000045f,   /* REFRESH */
254                         0x00000000,   /* BURST_REFRESH_NUM */
255                         0x00000004,   /* PDEX2WR */
256                         0x00000004,   /* PDEX2RD */
257                         0x00000007,   /* PCHG2PDEN */
258                         0x00000008,   /* ACT2PDEN */
259                         0x00000001,   /* AR2PDEN */
260                         0x0000000e,   /* RW2PDEN */
261                         0x0000002A,   /* TXSR */
262                         0x00000003,   /* TCKE */
263                         0x0000000F,   /* TFAW */
264                         0x00000008,   /* TRPAB */
265                         0x00000005,   /* TCLKSTABLE */
266                         0x00000002,   /* TCLKSTOP */
267                         0x000004E1,   /* TREFBW */
268                         0x00000005,   /* QUSE_EXTRA */
269                         0x00000002,   /* FBIO_CFG6 */
270                         0x00000000,   /* ODT_WRITE */
271                         0x00000000,   /* ODT_READ */
272                         0x00000282,   /* FBIO_CFG5 */
273                         0xE03C048B,   /* CFG_DIG_DLL */
274                         0x007FC010,   /* DLL_XFORM_DQS */
275                         0x00000000,   /* DLL_XFORM_QUSE */
276                         0x00000000,   /* ZCAL_REF_CNT */
277                         0x0000001B,   /* ZCAL_WAIT_CNT */
278                         0x00000000,   /* AUTO_CAL_INTERVAL */
279                         0x00000000,   /* CFG_CLKTRIM_0 */
280                         0x00000000,   /* CFG_CLKTRIM_1 */
281                         0x00000000,   /* CFG_CLKTRIM_2 */
282                 }
283         }
284 };
285
286 static const struct tegra_emc_table ventana_emc_tables_elpida_400Mhz[] = {
287         {
288                 .rate = 23750,   /* SDRAM frquency */
289                 .regs = {
290                         0x00000002,   /* RC */
291                         0x00000006,   /* RFC */
292                         0x00000003,   /* RAS */
293                         0x00000003,   /* RP */
294                         0x00000006,   /* R2W */
295                         0x00000004,   /* W2R */
296                         0x00000002,   /* R2P */
297                         0x0000000b,   /* W2P */
298                         0x00000003,   /* RD_RCD */
299                         0x00000003,   /* WR_RCD */
300                         0x00000002,   /* RRD */
301                         0x00000002,   /* REXT */
302                         0x00000003,   /* WDV */
303                         0x00000005,   /* QUSE */
304                         0x00000004,   /* QRST */
305                         0x00000008,   /* QSAFE */
306                         0x0000000c,   /* RDV */
307                         0x00000047,   /* REFRESH */
308                         0x00000000,   /* BURST_REFRESH_NUM */
309                         0x00000003,   /* PDEX2WR */
310                         0x00000003,   /* PDEX2RD */
311                         0x00000003,   /* PCHG2PDEN */
312                         0x00000008,   /* ACT2PDEN */
313                         0x00000001,   /* AR2PDEN */
314                         0x0000000b,   /* RW2PDEN */
315                         0x00000004,   /* TXSR */
316                         0x00000003,   /* TCKE */
317                         0x00000008,   /* TFAW */
318                         0x00000004,   /* TRPAB */
319                         0x00000008,   /* TCLKSTABLE */
320                         0x00000002,   /* TCLKSTOP */
321                         0x00000060,   /* TREFBW */
322                         0x00000004,   /* QUSE_EXTRA */
323                         0x00000003,   /* FBIO_CFG6 */
324                         0x00000000,   /* ODT_WRITE */
325                         0x00000000,   /* ODT_READ */
326                         0x00000082,   /* FBIO_CFG5 */
327                         0xa0ae04ae,   /* CFG_DIG_DLL */
328                         0x0001f800,   /* DLL_XFORM_DQS */
329                         0x00000000,   /* DLL_XFORM_QUSE */
330                         0x00000000,   /* ZCAL_REF_CNT */
331                         0x00000003,   /* ZCAL_WAIT_CNT */
332                         0x00000000,   /* AUTO_CAL_INTERVAL */
333                         0x00000000,   /* CFG_CLKTRIM_0 */
334                         0x00000000,   /* CFG_CLKTRIM_1 */
335                         0x00000000,   /* CFG_CLKTRIM_2 */
336                 }
337         },
338         {
339                 .rate = 63333,   /* SDRAM frquency */
340                 .regs = {
341                         0x00000004,   /* RC */
342                         0x00000009,   /* RFC */
343                         0x00000003,   /* RAS */
344                         0x00000003,   /* RP */
345                         0x00000006,   /* R2W */
346                         0x00000004,   /* W2R */
347                         0x00000002,   /* R2P */
348                         0x0000000b,   /* W2P */
349                         0x00000003,   /* RD_RCD */
350                         0x00000003,   /* WR_RCD */
351                         0x00000002,   /* RRD */
352                         0x00000002,   /* REXT */
353                         0x00000003,   /* WDV */
354                         0x00000006,   /* QUSE */
355                         0x00000004,   /* QRST */
356                         0x00000008,   /* QSAFE */
357                         0x0000000c,   /* RDV */
358                         0x000000c4,   /* REFRESH */
359                         0x00000000,   /* BURST_REFRESH_NUM */
360                         0x00000003,   /* PDEX2WR */
361                         0x00000003,   /* PDEX2RD */
362                         0x00000003,   /* PCHG2PDEN */
363                         0x00000008,   /* ACT2PDEN */
364                         0x00000001,   /* AR2PDEN */
365                         0x0000000b,   /* RW2PDEN */
366                         0x00000009,   /* TXSR */
367                         0x00000003,   /* TCKE */
368                         0x00000008,   /* TFAW */
369                         0x00000004,   /* TRPAB */
370                         0x00000008,   /* TCLKSTABLE */
371                         0x00000002,   /* TCLKSTOP */
372                         0x00000107,   /* TREFBW */
373                         0x00000005,   /* QUSE_EXTRA */
374                         0x00000000,   /* FBIO_CFG6 */
375                         0x00000000,   /* ODT_WRITE */
376                         0x00000000,   /* ODT_READ */
377                         0x00000082,   /* FBIO_CFG5 */
378                         0xa0ae04ae,   /* CFG_DIG_DLL */
379                         0x0001f800,   /* DLL_XFORM_DQS */
380                         0x00000000,   /* DLL_XFORM_QUSE */
381                         0x00000000,   /* ZCAL_REF_CNT */
382                         0x00000006,   /* ZCAL_WAIT_CNT */
383                         0x00000000,   /* AUTO_CAL_INTERVAL */
384                         0x00000000,   /* CFG_CLKTRIM_0 */
385                         0x00000000,   /* CFG_CLKTRIM_1 */
386                         0x00000000,   /* CFG_CLKTRIM_2 */
387                 }
388         },
389         {
390                 .rate = 95000,   /* SDRAM frquency */
391                 .regs = {
392                         0x00000006,   /* RC */
393                         0x0000000d,   /* RFC */
394                         0x00000004,   /* RAS */
395                         0x00000003,   /* RP */
396                         0x00000006,   /* R2W */
397                         0x00000004,   /* W2R */
398                         0x00000002,   /* R2P */
399                         0x0000000b,   /* W2P */
400                         0x00000003,   /* RD_RCD */
401                         0x00000003,   /* WR_RCD */
402                         0x00000002,   /* RRD */
403                         0x00000002,   /* REXT */
404                         0x00000003,   /* WDV */
405                         0x00000006,   /* QUSE */
406                         0x00000004,   /* QRST */
407                         0x00000008,   /* QSAFE */
408                         0x0000000c,   /* RDV */
409                         0x0000013f,   /* REFRESH */
410                         0x00000000,   /* BURST_REFRESH_NUM */
411                         0x00000003,   /* PDEX2WR */
412                         0x00000003,   /* PDEX2RD */
413                         0x00000003,   /* PCHG2PDEN */
414                         0x00000008,   /* ACT2PDEN */
415                         0x00000001,   /* AR2PDEN */
416                         0x0000000b,   /* RW2PDEN */
417                         0x0000000e,   /* TXSR */
418                         0x00000003,   /* TCKE */
419                         0x00000008,   /* TFAW */
420                         0x00000004,   /* TRPAB */
421                         0x00000008,   /* TCLKSTABLE */
422                         0x00000002,   /* TCLKSTOP */
423                         0x0000018c,   /* TREFBW */
424                         0x00000005,   /* QUSE_EXTRA */
425                         0x00000001,   /* FBIO_CFG6 */
426                         0x00000000,   /* ODT_WRITE */
427                         0x00000000,   /* ODT_READ */
428                         0x00000082,   /* FBIO_CFG5 */
429                         0xa0ae04ae,   /* CFG_DIG_DLL */
430                         0x0001f000,   /* DLL_XFORM_DQS */
431                         0x00000000,   /* DLL_XFORM_QUSE */
432                         0x00000000,   /* ZCAL_REF_CNT */
433                         0x00000009,   /* ZCAL_WAIT_CNT */
434                         0x00000000,   /* AUTO_CAL_INTERVAL */
435                         0x00000000,   /* CFG_CLKTRIM_0 */
436                         0x00000000,   /* CFG_CLKTRIM_1 */
437                         0x00000000,   /* CFG_CLKTRIM_2 */
438                 }
439         },
440         {
441                 .rate = 190000,   /* SDRAM frquency */
442                 .regs = {
443                         0x0000000c,   /* RC */
444                         0x00000019,   /* RFC */
445                         0x00000008,   /* RAS */
446                         0x00000004,   /* RP */
447                         0x00000007,   /* R2W */
448                         0x00000004,   /* W2R */
449                         0x00000002,   /* R2P */
450                         0x0000000b,   /* W2P */
451                         0x00000004,   /* RD_RCD */
452                         0x00000004,   /* WR_RCD */
453                         0x00000002,   /* RRD */
454                         0x00000003,   /* REXT */
455                         0x00000003,   /* WDV */
456                         0x00000006,   /* QUSE */
457                         0x00000004,   /* QRST */
458                         0x00000009,   /* QSAFE */
459                         0x0000000d,   /* RDV */
460                         0x000002bf,   /* REFRESH */
461                         0x00000000,   /* BURST_REFRESH_NUM */
462                         0x00000003,   /* PDEX2WR */
463                         0x00000003,   /* PDEX2RD */
464                         0x00000004,   /* PCHG2PDEN */
465                         0x00000008,   /* ACT2PDEN */
466                         0x00000001,   /* AR2PDEN */
467                         0x0000000c,   /* RW2PDEN */
468                         0x0000001b,   /* TXSR */
469                         0x00000003,   /* TCKE */
470                         0x0000000a,   /* TFAW */
471                         0x00000004,   /* TRPAB */
472                         0x00000008,   /* TCLKSTABLE */
473                         0x00000002,   /* TCLKSTOP */
474                         0x00000317,   /* TREFBW */
475                         0x00000005,   /* QUSE_EXTRA */
476                         0x00000002,   /* FBIO_CFG6 */
477                         0x00000000,   /* ODT_WRITE */
478                         0x00000000,   /* ODT_READ */
479                         0x00000082,   /* FBIO_CFG5 */
480                         0xa06204ae,   /* CFG_DIG_DLL */
481                         0x007f7010,   /* DLL_XFORM_DQS */
482                         0x00000000,   /* DLL_XFORM_QUSE */
483                         0x00000000,   /* ZCAL_REF_CNT */
484                         0x00000012,   /* ZCAL_WAIT_CNT */
485                         0x00000000,   /* AUTO_CAL_INTERVAL */
486                         0x00000000,   /* CFG_CLKTRIM_0 */
487                         0x00000000,   /* CFG_CLKTRIM_1 */
488                         0x00000000,   /* CFG_CLKTRIM_2 */
489                 }
490         },
491         {
492                 .rate = 380000,   /* SDRAM frquency */
493                 .regs = {
494                         0x00000017,   /* RC */
495                         0x00000032,   /* RFC */
496                         0x00000010,   /* RAS */
497                         0x00000007,   /* RP */
498                         0x00000008,   /* R2W */
499                         0x00000005,   /* W2R */
500                         0x00000003,   /* R2P */
501                         0x0000000b,   /* W2P */
502                         0x00000007,   /* RD_RCD */
503                         0x00000007,   /* WR_RCD */
504                         0x00000004,   /* RRD */
505                         0x00000003,   /* REXT */
506                         0x00000003,   /* WDV */
507                         0x00000007,   /* QUSE */
508                         0x00000004,   /* QRST */
509                         0x0000000a,   /* QSAFE */
510                         0x0000000e,   /* RDV */
511                         0x0000059f,   /* REFRESH */
512                         0x00000000,   /* BURST_REFRESH_NUM */
513                         0x00000004,   /* PDEX2WR */
514                         0x00000004,   /* PDEX2RD */
515                         0x00000007,   /* PCHG2PDEN */
516                         0x00000008,   /* ACT2PDEN */
517                         0x00000001,   /* AR2PDEN */
518                         0x00000011,   /* RW2PDEN */
519                         0x00000036,   /* TXSR */
520                         0x00000003,   /* TCKE */
521                         0x00000013,   /* TFAW */
522                         0x00000008,   /* TRPAB */
523                         0x00000007,   /* TCLKSTABLE */
524                         0x00000002,   /* TCLKSTOP */
525                         0x0000062d,   /* TREFBW */
526                         0x00000006,   /* QUSE_EXTRA */
527                         0x00000003,   /* FBIO_CFG6 */
528                         0x00000000,   /* ODT_WRITE */
529                         0x00000000,   /* ODT_READ */
530                         0x00000282,   /* FBIO_CFG5 */
531                         0xe044048b,   /* CFG_DIG_DLL */
532                         0x007fb010,   /* DLL_XFORM_DQS */
533                         0x00000000,   /* DLL_XFORM_QUSE */
534                         0x00000000,   /* ZCAL_REF_CNT */
535                         0x00000023,   /* ZCAL_WAIT_CNT */
536                         0x00000000,   /* AUTO_CAL_INTERVAL */
537                         0x00000000,   /* CFG_CLKTRIM_0 */
538                         0x00000000,   /* CFG_CLKTRIM_1 */
539                         0x00000000,   /* CFG_CLKTRIM_2 */
540                 }
541         }
542 };
543
544 static struct tegra_emc_pdata ventana_emc_chip = {
545         .description = "Elpida 300MHz",
546         .mem_manufacturer_id = 0x0303,
547         .mem_revision_id1 = -1,
548         .mem_revision_id2 = -1,
549         .mem_pid = -1,
550         .tables = (struct tegra_emc_table *)ventana_emc_tables_elpida_300Mhz,
551         .num_tables = ARRAY_SIZE(ventana_emc_tables_elpida_300Mhz)
552 };
553
554 static struct tegra_emc_pdata ventana_t25_emc_chip = {
555         .description = "Elpida 400MHz",
556         .mem_manufacturer_id = 0x0303,
557         .mem_revision_id1 = -1,
558         .mem_revision_id2 = -1,
559         .mem_pid = -1,
560         .tables = (struct tegra_emc_table *)ventana_emc_tables_elpida_400Mhz,
561         .num_tables = ARRAY_SIZE(ventana_emc_tables_elpida_400Mhz)
562 };
563
564 static struct tegra_emc_pdata ventana_siblings_emc_chip = {
565 };
566
567 #define TEGRA25_SKU             0x0B00
568
569 int ventana_emc_init(void)
570 {
571         struct board_info BoardInfo;
572         struct tegra_emc_pdata *emc_platdata;
573
574         tegra_get_board_info(&BoardInfo);
575
576         if (BoardInfo.board_id == 0x24b || BoardInfo.board_id == 0x252) {
577                 if (BoardInfo.sku == TEGRA25_SKU)
578                         emc_platdata = &ventana_t25_emc_chip;
579                 else
580                         emc_platdata = &ventana_emc_chip;
581         } else {
582                 pr_info("ventana_emc_init: using ventana_siblings_emc_chips\n");
583                 emc_platdata = &ventana_siblings_emc_chip;
584         }
585
586         tegra_emc_device.dev.platform_data = emc_platdata;
587         platform_device_register(&tegra_emc_device);
588
589         tegra_emc_init();
590
591         return 0;
592 }