ARM: tegra: tegratab: Enable Tboard temp shutdown per board revision
[linux-2.6.git] / arch / arm / mach-tegra / board-tegratab-power.c
1 /*
2  * arch/arm/mach-tegra/board-tegratab-power.c
3  *
4  * Copyright (C) 2012-2013 NVIDIA Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
24 #include <linux/io.h>
25 #include <linux/regulator/machine.h>
26 #include <linux/regulator/driver.h>
27 #include <linux/regulator/fixed.h>
28 #include <linux/mfd/palmas.h>
29 #include <linux/power/bq2419x-charger.h>
30 #include <linux/max17048_battery.h>
31 #include <linux/power/power_supply_extcon.h>
32 #include <linux/gpio.h>
33 #include <linux/interrupt.h>
34 #include <linux/regulator/userspace-consumer.h>
35 #include <linux/platform_data/tegra_edp.h>
36 #include <linux/platform_data/ina230.h>
37
38 #include <asm/mach-types.h>
39 #include <linux/power/sbs-battery.h>
40
41 #include <mach/iomap.h>
42 #include <mach/irqs.h>
43 #include <mach/hardware.h>
44 #include <mach/edp.h>
45 #include <mach/gpio-tegra.h>
46
47 #include "cpu-tegra.h"
48 #include "pm.h"
49 #include "tegra-board-id.h"
50 #include "board-pmu-defines.h"
51 #include "board.h"
52 #include "fuse.h"
53 #include "gpio-names.h"
54 #include "board-common.h"
55 #include "board-tegratab.h"
56 #include "tegra_cl_dvfs.h"
57 #include "devices.h"
58 #include "tegra11_soctherm.h"
59 #include "tegra3_tsensor.h"
60
61 #define PMC_CTRL                0x0
62 #define PMC_CTRL_INTR_LOW       (1 << 17)
63
64 /* BQ2419X VBUS regulator */
65 static struct regulator_consumer_supply tegratab_bq2419x_vbus_supply[] = {
66         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
67         REGULATOR_SUPPLY("usb_vbus", "tegra-otg"),
68 };
69
70 static struct regulator_consumer_supply tegratab_bq2419x_batt_supply[] = {
71         REGULATOR_SUPPLY("usb_bat_chg", "tegra-udc.0"),
72 };
73
74 static struct bq2419x_vbus_platform_data tegratab_bq2419x_vbus_pdata = {
75         .gpio_otg_iusb = TEGRA_GPIO_PI4,
76         .num_consumer_supplies = ARRAY_SIZE(tegratab_bq2419x_vbus_supply),
77         .consumer_supplies = tegratab_bq2419x_vbus_supply,
78 };
79
80 struct bq2419x_charger_platform_data tegratab_bq2419x_charger_pdata = {
81         .update_status = max17048_battery_status,
82         .battery_check = max17048_check_battery,
83         .soc_check = max17048_check_soc,
84         .vcell_check = max17048_check_vcell,
85         .current_check = ina230_get_current,
86         .max_charge_current_mA = 3000,
87         .charging_term_current_mA = 100,
88         .consumer_supplies = tegratab_bq2419x_batt_supply,
89         .num_consumer_supplies = ARRAY_SIZE(tegratab_bq2419x_batt_supply),
90         .wdt_timeout = 40,
91         .chg_restart_time = 1800,       /* 30 min */
92         .chg_complete_soc = 100,
93 };
94
95 #ifndef CONFIG_OF
96 struct max17048_battery_model tegratab_max17048_mdata = {
97         .rcomp          = 105,
98         .soccheck_A     = 233,
99         .soccheck_B     = 235,
100         .bits           = 19,
101         .alert_threshold = 0x01,        /* 1% SOC */
102         .one_percent_alerts = 0x40,
103         .alert_on_reset = 0x00,         /* not use */
104         .rcomp_seg      = 0x0080,
105         .hibernate      = 0x3080,
106         .vreset         = 0x3c96,
107         .valert         = 0xA2FF,       /*VALRT.MIN 3.24V, VALRT.MAX 5.1V*/
108         .ocvtest        = 55824,
109         .t_co_hot       = -1125,        /* -1.125 */
110         .t_co_cold      = -7625,        /* -7.625 */
111         .data_tbl = {
112                 0xAA, 0x30, 0xB7, 0x80, 0xB8, 0xD0, 0xBA, 0xC0,
113                 0xBB, 0xC0, 0xBC, 0x30, 0xBC, 0xB0, 0xBD, 0x60,
114                 0xBE, 0x10, 0xBF, 0x40, 0xC0, 0x30, 0xC3, 0x80,
115                 0xC5, 0x00, 0xC7, 0x60, 0xCB, 0x50, 0xD0, 0x10,
116                 0x03, 0x00, 0x30, 0xC0, 0x1C, 0x40, 0x2C, 0x00,
117                 0x70, 0xC0, 0x51, 0x40, 0x43, 0xE0, 0x43, 0xC0,
118                 0x29, 0xC0, 0x2F, 0xC0, 0x17, 0xE0, 0x12, 0xE0,
119                 0x1C, 0x20, 0x13, 0x80, 0x0E, 0x00, 0x0E, 0x00,
120         },
121 };
122
123 struct max17048_platform_data tegratab_max17048_pdata = {
124         .model_data = &tegratab_max17048_mdata,
125         .read_batt_id = 1;
126         .set_current_threshold = ina230_set_current_threshold,
127         .current_normal = TEGRATAB_BATTERY_MAX_CURRENT,
128         .current_threshold_num = 2,
129         .current_threshold_soc = {4, 8},
130         .current_threshold = {1800, 2500},
131         .sysedp_throttle = sysedp_lite_throttle,
132         .sysedp_throttle_num = 2,
133         .sysedp_throttle_soc = {4, 8},
134         .sysedp_throttle_power = {10000, 10500},
135 };
136
137 static struct i2c_board_info __initdata tegratab_max17048_boardinfo[] = {
138         {
139                 I2C_BOARD_INFO("max17048", 0x36),
140                 .platform_data  = &tegratab_max17048_pdata,
141         },
142 };
143 #endif
144
145 struct bq2419x_platform_data tegratab_bq2419x_pdata = {
146         .vbus_pdata = &tegratab_bq2419x_vbus_pdata,
147         .bcharger_pdata = &tegratab_bq2419x_charger_pdata,
148 };
149
150 static struct i2c_board_info __initdata tegratab_bq2419x_boardinfo[] = {
151         {
152                 I2C_BOARD_INFO("bq2419x", 0x6b),
153                 .platform_data = &tegratab_bq2419x_pdata,
154         },
155 };
156
157 static struct power_supply_extcon_plat_data psy_extcon_pdata = {
158         .extcon_name = "tegra-udc",
159 };
160
161 static struct platform_device psy_extcon_device = {
162         .name = "power-supply-extcon",
163         .id = -1,
164         .dev = {
165                 .platform_data = &psy_extcon_pdata,
166         },
167 };
168
169 /************************ Tegratab based regulator ****************/
170 static struct regulator_consumer_supply palmas_smps123_supply[] = {
171         REGULATOR_SUPPLY("vdd_cpu", NULL),
172 };
173
174 static struct regulator_consumer_supply palmas_smps45_supply[] = {
175         REGULATOR_SUPPLY("vdd_core", NULL),
176         REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.0"),
177         REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.3"),
178 };
179
180 static struct regulator_consumer_supply palmas_smps6_supply[] = {
181         REGULATOR_SUPPLY("vdd_lcd_hv", NULL),
182         REGULATOR_SUPPLY("avdd_lcd", NULL),
183 };
184
185 static struct regulator_consumer_supply palmas_smps7_supply[] = {
186         REGULATOR_SUPPLY("vddio_ddr", NULL),
187 };
188
189 static struct regulator_consumer_supply palmas_smps8_supply[] = {
190         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
191         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
192         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
193         REGULATOR_SUPPLY("avdd_osc", NULL),
194         REGULATOR_SUPPLY("vddio_sys", NULL),
195         REGULATOR_SUPPLY("vddio_bb", NULL),
196         REGULATOR_SUPPLY("pwrdet_bb", NULL),
197         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
198         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
199         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
200         REGULATOR_SUPPLY("vdd_emmc", "sdhci-tegra.3"),
201         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
202         REGULATOR_SUPPLY("vddio_audio", NULL),
203         REGULATOR_SUPPLY("pwrdet_audio", NULL),
204         REGULATOR_SUPPLY("vddio_uart", NULL),
205         REGULATOR_SUPPLY("pwrdet_uart", NULL),
206         REGULATOR_SUPPLY("vddio_gmi", NULL),
207         REGULATOR_SUPPLY("pwrdet_nand", NULL),
208         REGULATOR_SUPPLY("vlogic", "0-0069"),
209         REGULATOR_SUPPLY("vid", "0-000d"),
210         REGULATOR_SUPPLY("vddio", "0-0078"),
211         REGULATOR_SUPPLY("vdd", "0-004c"),
212 };
213
214 static struct regulator_consumer_supply palmas_smps9_supply[] = {
215         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
216         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
217         REGULATOR_SUPPLY("pwrdet_hv", NULL),
218 };
219
220 static struct regulator_consumer_supply palmas_smps10_supply[] = {
221 };
222
223 static struct regulator_consumer_supply palmas_ldo1_supply[] = {
224         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
225         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
226         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
227         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "vi"),
228         REGULATOR_SUPPLY("avdd_pllm", NULL),
229         REGULATOR_SUPPLY("avdd_pllu", NULL),
230         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
231         REGULATOR_SUPPLY("avdd_pllx", NULL),
232         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
233         REGULATOR_SUPPLY("avdd_plle", NULL),
234 };
235
236 static struct regulator_consumer_supply palmas_ldo2_supply[] = {
237         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
238         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
239         REGULATOR_SUPPLY("avdd_dsi_csi", "vi"),
240         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
241         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
242         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
243 };
244
245 static struct regulator_consumer_supply palmas_ldo3_supply[] = {
246         REGULATOR_SUPPLY("vpp_fuse", NULL),
247 };
248
249 static struct regulator_consumer_supply palmas_ldo4_supply[] = {
250         REGULATOR_SUPPLY("avdd", "spi0.0"),
251 };
252
253 static struct regulator_consumer_supply palmas_ldo5_supply[] = {
254 #ifdef CONFIG_USE_OF
255         REGULATOR_SUPPLY("ext_vcm_vdd", "2-0010"),
256 #else
257         REGULATOR_SUPPLY("vdd_af_cam1", NULL),
258 #endif
259         REGULATOR_SUPPLY("vdd", "2-000c"),
260         REGULATOR_SUPPLY("vana", "2-0048"),
261         REGULATOR_SUPPLY("vana", "2-0021"),
262 };
263
264 static struct regulator_consumer_supply palmas_ldo6_supply[] = {
265         REGULATOR_SUPPLY("vdd", "0-0069"),
266         REGULATOR_SUPPLY("vdd", "0-0010"),
267         REGULATOR_SUPPLY("vdd", "0-000d"),
268         REGULATOR_SUPPLY("vdd", "0-0078"),
269 };
270
271 static struct regulator_consumer_supply palmas_ldo7_supply[] = {
272         REGULATOR_SUPPLY("avdd", "2-0010"),
273 };
274 static struct regulator_consumer_supply palmas_ldo8_supply[] = {
275         REGULATOR_SUPPLY("vdd_rtc", NULL),
276 };
277 static struct regulator_consumer_supply palmas_ldo9_supply[] = {
278         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
279         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
280 };
281 static struct regulator_consumer_supply palmas_ldoln_supply[] = {
282         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
283 };
284
285 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
286         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
287         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
288         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
289         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
290         REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
291
292 };
293
294 static struct regulator_consumer_supply palmas_regen1_supply[] = {
295 };
296
297 static struct regulator_consumer_supply palmas_regen2_supply[] = {
298 };
299
300 PALMAS_REGS_PDATA(smps123, 900,  1350, NULL, 0, 0, 0, 0,
301         0, PALMAS_EXT_CONTROL_ENABLE1, 0, 3, 0);
302 PALMAS_REGS_PDATA(smps45, 900,  1400, NULL, 0, 0, 0, 0,
303         0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
304 PALMAS_REGS_PDATA(smps6, 3160,  3160, NULL, 0, 0, 1, NORMAL,
305         0, 0, 0, 0, 0);
306 PALMAS_REGS_PDATA(smps7, 1350,  1350, NULL, 0, 0, 1, NORMAL,
307         0, 0, 0, 0, 0);
308 PALMAS_REGS_PDATA(smps8, 1800,  1800, NULL, 1, 1, 1, NORMAL,
309         0, 0, 0, 0, 0);
310 PALMAS_REGS_PDATA(smps9, 2900,  2900, NULL, 0, 0, 1, NORMAL,
311         0, 0, 0, 0, 0);
312 PALMAS_REGS_PDATA(smps10, 5000,  5000, NULL, 0, 0, 0, 0,
313         0, 0, 0, 0, 0);
314 PALMAS_REGS_PDATA(ldo1, 1050,  1050, palmas_rails(smps7), 1, 0, 1, 0,
315         0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
316 PALMAS_REGS_PDATA(ldo2, 1200,  1200, palmas_rails(smps7), 0, 1, 1, 0,
317         0, 0, 0, 0, 0);
318 PALMAS_REGS_PDATA(ldo3, 1800,  1800, NULL, 0, 0, 1, 0,
319         0, 0, 0, 0, 0);
320 PALMAS_REGS_PDATA(ldo4, 3000,  3000, NULL, 0, 0, 1, 0,
321         0, 0, 0, 0, 0);
322 PALMAS_REGS_PDATA(ldo5, 2800,  2800, palmas_rails(smps9), 0, 0, 1, 0,
323         0, 0, 0, 0, 0);
324 PALMAS_REGS_PDATA(ldo6, 2850,  2850, palmas_rails(smps9), 0, 1, 1, 0,
325         0, 0, 0, 0, 0);
326 PALMAS_REGS_PDATA(ldo7, 2700,  2700, palmas_rails(smps9), 0, 0, 1, 0,
327         0, 0, 0, 0, 0);
328 PALMAS_REGS_PDATA(ldo8, 950,  950, NULL, 1, 1, 1, 0,
329         0, 0, 0, 0, 0);
330 PALMAS_REGS_PDATA(ldo9, 1800,  2900, palmas_rails(smps9), 0, 0, 1, 0,
331         0, 0, 0, 0, 0);
332 PALMAS_REGS_PDATA(ldoln, 3300,   3300, NULL, 0, 0, 1, 0,
333         0, 0, 0, 0, 0);
334 PALMAS_REGS_PDATA(ldousb, 3300,  3300, NULL, 0, 0, 1, 0,
335         0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
336 PALMAS_REGS_PDATA(regen1, 4200,  4200, NULL, 0, 0, 0, 0,
337         0, 0, 0, 0, 0);
338 PALMAS_REGS_PDATA(regen2, 4200,  4200, palmas_rails(smps8), 0, 0, 0, 0,
339         0, 0, 0, 0, 0);
340
341 #define PALMAS_REG_PDATA(_sname) (&reg_idata_##_sname)
342 static struct regulator_init_data *tegratab_reg_data[PALMAS_NUM_REGS] = {
343         NULL,
344         PALMAS_REG_PDATA(smps123),
345         NULL,
346         PALMAS_REG_PDATA(smps45),
347         NULL,
348         PALMAS_REG_PDATA(smps6),
349         PALMAS_REG_PDATA(smps7),
350         PALMAS_REG_PDATA(smps8),
351         PALMAS_REG_PDATA(smps9),
352         PALMAS_REG_PDATA(smps10),
353         PALMAS_REG_PDATA(ldo1),
354         PALMAS_REG_PDATA(ldo2),
355         PALMAS_REG_PDATA(ldo3),
356         PALMAS_REG_PDATA(ldo4),
357         PALMAS_REG_PDATA(ldo5),
358         PALMAS_REG_PDATA(ldo6),
359         PALMAS_REG_PDATA(ldo7),
360         PALMAS_REG_PDATA(ldo8),
361         PALMAS_REG_PDATA(ldo9),
362         PALMAS_REG_PDATA(ldoln),
363         PALMAS_REG_PDATA(ldousb),
364         PALMAS_REG_PDATA(regen1),
365         PALMAS_REG_PDATA(regen2),
366         NULL,
367         NULL,
368         NULL,
369 };
370
371 #define PALMAS_REG_INIT_DATA(_sname) (&reg_init_data_##_sname)
372 static struct palmas_reg_init *tegratab_reg_init[PALMAS_NUM_REGS] = {
373         NULL,
374         PALMAS_REG_INIT_DATA(smps123),
375         NULL,
376         PALMAS_REG_INIT_DATA(smps45),
377         NULL,
378         PALMAS_REG_INIT_DATA(smps6),
379         PALMAS_REG_INIT_DATA(smps7),
380         PALMAS_REG_INIT_DATA(smps8),
381         PALMAS_REG_INIT_DATA(smps9),
382         PALMAS_REG_INIT_DATA(smps10),
383         PALMAS_REG_INIT_DATA(ldo1),
384         PALMAS_REG_INIT_DATA(ldo2),
385         PALMAS_REG_INIT_DATA(ldo3),
386         PALMAS_REG_INIT_DATA(ldo4),
387         PALMAS_REG_INIT_DATA(ldo5),
388         PALMAS_REG_INIT_DATA(ldo6),
389         PALMAS_REG_INIT_DATA(ldo7),
390         PALMAS_REG_INIT_DATA(ldo8),
391         PALMAS_REG_INIT_DATA(ldo9),
392         PALMAS_REG_INIT_DATA(ldoln),
393         PALMAS_REG_INIT_DATA(ldousb),
394         PALMAS_REG_INIT_DATA(regen1),
395         PALMAS_REG_INIT_DATA(regen2),
396         NULL,
397         NULL,
398         NULL,
399 };
400
401 static struct palmas_pmic_platform_data pmic_platform = {
402         .enable_ldo8_tracking = true,
403         .disabe_ldo8_tracking_suspend = true,
404         .disable_smps10_boost_suspend = true,
405 };
406
407
408 #define PALMAS_GPADC_IIO_MAP(_ch, _dev_name, _name)             \
409         {                                                       \
410                 .adc_channel_label = _ch,                       \
411                 .consumer_dev_name = _dev_name,                 \
412                 .consumer_channel = _name,                      \
413         }
414
415 static struct iio_map palmas_adc_iio_maps[] = {
416         PALMAS_GPADC_IIO_MAP("IN0", "0-0036", "batt_id"),
417         PALMAS_GPADC_IIO_MAP("IN1", "generic-adc-thermal.0", "thermistor"),
418         PALMAS_GPADC_IIO_MAP("IN3", "generic-adc-thermal.1", "tdiode"),
419         PALMAS_GPADC_IIO_MAP(NULL, NULL, NULL),
420 };
421
422 struct palmas_adc_auto_conv_property palmas_adc_auto_conv1_data = {
423         .adc_channel_number = PALMAS_ADC_CH_IN1, /* NTC thermistor(Tboard) */
424         /* Shutdown if ADC auto conversion is below 168(>95C). */
425         .adc_low_threshold = 168, /* 95C */
426         .adc_shutdown = true,
427 };
428
429 static struct palmas_gpadc_platform_data palmas_adc_pdata = {
430         .ch0_current_uA = 5,
431         /* If ch3_dual_current is true, it will measure ch3 input signal with
432          * ch3_current and the next current of ch3_current.
433          * So this system will use 400uA and 800uA for ch3 measurement. */
434         .ch3_current_uA = 400,  /* 0uA, 10uA, 400uA, 800uA */
435         .ch3_dual_current = true,
436         .extended_delay = true,
437         .iio_maps = palmas_adc_iio_maps,
438 };
439
440 static struct palmas_pinctrl_config palmas_pincfg[] = {
441         PALMAS_PINMUX(POWERGOOD, POWERGOOD, DEFAULT, DEFAULT),
442         PALMAS_PINMUX(VAC, VAC, DEFAULT, DEFAULT),
443         PALMAS_PINMUX(GPIO0, GPIO, DEFAULT, DEFAULT),
444         PALMAS_PINMUX(GPIO1, GPIO, DEFAULT, DEFAULT),
445         PALMAS_PINMUX(GPIO2, GPIO, DEFAULT, DEFAULT),
446         PALMAS_PINMUX(GPIO3, GPIO, DEFAULT, DEFAULT),
447         PALMAS_PINMUX(GPIO4, GPIO, DEFAULT, DEFAULT),
448         PALMAS_PINMUX(GPIO5, GPIO, DEFAULT, DEFAULT),
449         PALMAS_PINMUX(GPIO6, GPIO, DEFAULT, DEFAULT),
450         PALMAS_PINMUX(GPIO7, GPIO, DEFAULT, DEFAULT),
451 };
452
453 static struct palmas_pinctrl_platform_data palmas_pinctrl_pdata = {
454         .pincfg = palmas_pincfg,
455         .num_pinctrl = ARRAY_SIZE(palmas_pincfg),
456         .dvfs1_enable = true,
457         .dvfs2_enable = false,
458 };
459
460 static struct palmas_extcon_platform_data palmas_extcon_pdata = {
461         .connection_name = "palmas-extcon",
462         .enable_vbus_detection = true,
463         .enable_id_pin_detection = true,
464 };
465
466 static struct palmas_platform_data palmas_pdata = {
467         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
468         .irq_base = PALMAS_TEGRA_IRQ_BASE,
469         .pmic_pdata = &pmic_platform,
470         .adc_pdata = &palmas_adc_pdata,
471         .use_power_off = true,
472         .pinctrl_pdata = &palmas_pinctrl_pdata,
473         .extcon_pdata = &palmas_extcon_pdata,
474         .long_press_delay = PALMAS_LONG_PRESS_KEY_TIME_8SECONDS,
475         .poweron_lpk = PALMAS_SWOFF_COLDRST_PWRON_LPK_RESTART,
476 };
477
478 struct palmas_clk32k_init_data tegratab_palmas_clk32k_idata[] = {
479         {
480                 .clk32k_id = PALMAS_CLOCK32KG,
481                 .enable = true,
482         }
483 };
484
485 static struct i2c_board_info palma_device[] = {
486         {
487                 I2C_BOARD_INFO("tps65913", 0x58),
488                 .irq            = INT_EXTERNAL_PMU,
489                 .platform_data  = &palmas_pdata,
490         },
491 };
492
493 static struct regulator_consumer_supply fixed_reg_dvdd_lcd_1v8_supply[] = {
494         REGULATOR_SUPPLY("dvdd_lcd", NULL),
495 };
496
497 static struct regulator_consumer_supply fixed_reg_vdd_lcd_bl_en_supply[] = {
498         REGULATOR_SUPPLY("vdd_lcd_bl_en", NULL),
499 };
500
501 /* EN_1V8_TS From TEGRA_GPIO_PH4 */
502 static struct regulator_consumer_supply fixed_reg_dvdd_ts_supply[] = {
503         REGULATOR_SUPPLY("dvdd", "spi0.0"),
504 };
505
506 /* ENABLE 5v0 for HDMI */
507 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = {
508         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
509 };
510
511 static struct regulator_consumer_supply fixed_reg_vddio_sd_slot_supply[] = {
512         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
513 };
514
515 static struct regulator_consumer_supply fixed_reg_vd_cam_1v8_supply[] = {
516         REGULATOR_SUPPLY("dovdd", "2-0010"),
517         REGULATOR_SUPPLY("vif2", "2-0048"),
518         REGULATOR_SUPPLY("vif2", "2-0021"),
519         REGULATOR_SUPPLY("vddio_cam", "vi"),
520         REGULATOR_SUPPLY("pwrdet_cam", NULL),
521 };
522
523 static struct regulator_consumer_supply fixed_reg_en_lcd_1v8_supply[] = {
524         REGULATOR_SUPPLY("dvdd_lcd", NULL),
525         REGULATOR_SUPPLY("dvdd", "spi0.0"),
526 };
527
528 /* Macro for defining fixed regulator sub device data */
529 #define FIXED_SUPPLY(_name) "fixed_reg_"#_name
530 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,   \
531         _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts)  \
532         static struct regulator_init_data ri_data_##_var =              \
533         {                                                               \
534                 .supply_regulator = _in_supply,                         \
535                 .num_consumer_supplies =                                \
536                         ARRAY_SIZE(fixed_reg_##_name##_supply),         \
537                 .consumer_supplies = fixed_reg_##_name##_supply,        \
538                 .constraints = {                                        \
539                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
540                                         REGULATOR_MODE_STANDBY),        \
541                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
542                                         REGULATOR_CHANGE_STATUS |       \
543                                         REGULATOR_CHANGE_VOLTAGE),      \
544                         .always_on = _always_on,                        \
545                         .boot_on = _boot_on,                            \
546                 },                                                      \
547         };                                                              \
548         static struct fixed_voltage_config fixed_reg_##_var##_pdata =   \
549         {                                                               \
550                 .supply_name = FIXED_SUPPLY(_name),                     \
551                 .microvolts = _millivolts * 1000,                       \
552                 .gpio = _gpio_nr,                                       \
553                 .gpio_is_open_drain = _open_drain,                      \
554                 .enable_high = _active_high,                            \
555                 .enabled_at_boot = _boot_state,                         \
556                 .init_data = &ri_data_##_var,                           \
557         };                                                              \
558         static struct platform_device fixed_reg_##_var##_dev = {        \
559                 .name = "reg-fixed-voltage",                            \
560                 .id = _id,                                              \
561                 .dev = {                                                \
562                         .platform_data = &fixed_reg_##_var##_pdata,     \
563                 },                                                      \
564         }
565
566 /*
567  * Creating the fixed regulator device table
568  */
569
570 FIXED_REG(1,    dvdd_lcd_1v8,   dvdd_lcd_1v8,
571         palmas_rails(smps8),    0,      1,
572         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO4,  false,  true,   1,      1800);
573
574 FIXED_REG(2,    vdd_lcd_bl_en,  vdd_lcd_bl_en,
575         NULL,   0,      1,
576         TEGRA_GPIO_PH2, false,  true,   1,      3700);
577
578 FIXED_REG(3,    dvdd_ts,        dvdd_ts,
579         palmas_rails(smps8),    0,      0,
580         TEGRA_GPIO_PH4, false,  false,  1,      1800);
581
582 FIXED_REG(4,    vdd_hdmi_5v0,   vdd_hdmi_5v0,
583         palmas_rails(smps10),   0,      0,
584         TEGRA_GPIO_PK6, true,   true,   0,      5000);
585
586 FIXED_REG(5,    vddio_sd_slot,  vddio_sd_slot,
587         palmas_rails(smps9),    0,      0,
588         TEGRA_GPIO_PK1, false,  true,   0,      2900);
589
590 FIXED_REG(6,    vd_cam_1v8,     vd_cam_1v8,
591         palmas_rails(smps8),    0,      0,
592         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO6,  false,  true,   0,      1800);
593
594 FIXED_REG(7,    en_lcd_1v8,     en_lcd_1v8,
595         palmas_rails(smps8),    0,      1,
596         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO4,  false,  true,   1,      1800);
597
598 /*
599  * Creating the fixed regulator device tables
600  */
601 #define ADD_FIXED_REG(_name)    (&fixed_reg_##_name##_dev)
602
603 #define TEGRATAB_COMMON_FIXED_REG               \
604         ADD_FIXED_REG(vdd_lcd_bl_en),           \
605         ADD_FIXED_REG(vdd_hdmi_5v0),            \
606         ADD_FIXED_REG(vddio_sd_slot),           \
607         ADD_FIXED_REG(vd_cam_1v8),
608
609 #define E1569_FIXED_REG                         \
610         ADD_FIXED_REG(dvdd_lcd_1v8),            \
611         ADD_FIXED_REG(dvdd_ts),
612
613 #define P1640_FIXED_REG                         \
614         ADD_FIXED_REG(en_lcd_1v8),
615
616 /* Gpio switch regulator platform data for Tegratab E1569 */
617 static struct platform_device *fixed_reg_devs_e1569[] = {
618         TEGRATAB_COMMON_FIXED_REG
619         E1569_FIXED_REG
620 };
621
622 /* Gpio switch regulator platform data for Tegratab P1640 */
623 static struct platform_device *fixed_reg_devs_p1640[] = {
624         TEGRATAB_COMMON_FIXED_REG
625         P1640_FIXED_REG
626 };
627
628 int __init tegratab_palmas_regulator_init(void)
629 {
630         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
631         u32 pmc_ctrl;
632         int i;
633         struct board_info board_info;
634
635         /* TPS65913: Normal state of INT request line is LOW.
636          * configure the power management controller to trigger PMU
637          * interrupts when HIGH.
638          */
639         pmc_ctrl = readl(pmc + PMC_CTRL);
640         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
641         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
642                 pmic_platform.reg_data[i] = tegratab_reg_data[i];
643                 pmic_platform.reg_init[i] = tegratab_reg_init[i];
644         }
645
646         tegra_get_board_info(&board_info);
647
648         if (board_info.board_id == BOARD_P1640 &&
649                         ((board_info.fab < BOARD_FAB_A04) ||
650                         (board_info.fab >= BOARD_FAB_A04 &&
651                         tegra_bct_strapping != 1))) {
652                 /* Boot strapping 0, 2, 3 indicate Micron 1GB MT41K128M16-125
653                  * and it requires VDDIO_DDR 1.38V for stability.
654                  * Boot strapping 1 indicates Hynix 1GB H5TC2G63FFR-PBA and
655                  * it requires VDDIO_DDR 1.35V.
656                  */
657                 tegratab_reg_data[PALMAS_REG_SMPS7]->constraints.min_uV =
658                                                                         1380000;
659                 tegratab_reg_data[PALMAS_REG_SMPS7]->constraints.max_uV =
660                                                                         1380000;
661         }
662
663         if (board_info.board_id == BOARD_P1640 &&
664                                 board_info.fab >= BOARD_FAB_A01) {
665                 palmas_pdata.clk32k_init_data = tegratab_palmas_clk32k_idata;
666                 palmas_pdata.clk32k_init_data_size =
667                                 ARRAY_SIZE(tegratab_palmas_clk32k_idata);
668         }
669
670         if (board_info.board_id != BOARD_E1569 &&
671                         (board_info.board_id == BOARD_P1640 &&
672                         (board_info.fab != BOARD_FAB_A00 &&
673                         board_info.fab != BOARD_FAB_A01))) {
674                 palmas_adc_pdata.auto_conversion_period_ms = 1000;
675                 palmas_adc_pdata.adc_auto_conv1_data =
676                                 &palmas_adc_auto_conv1_data;
677         }
678
679         if (get_androidboot_mode_charger())
680                 palmas_pdata.long_press_delay =
681                                 PALMAS_LONG_PRESS_KEY_TIME_12SECONDS;
682
683         i2c_register_board_info(4, palma_device,
684                         ARRAY_SIZE(palma_device));
685         return 0;
686 }
687
688 static int ac_online(void)
689 {
690         return 1;
691 }
692
693 static struct resource tegratab_pda_resources[] = {
694         [0] = {
695                 .name   = "ac",
696         },
697 };
698
699 static struct pda_power_pdata tegratab_pda_data = {
700         .is_ac_online   = ac_online,
701 };
702
703 static struct platform_device tegratab_pda_power_device = {
704         .name           = "pda-power",
705         .id             = -1,
706         .resource       = tegratab_pda_resources,
707         .num_resources  = ARRAY_SIZE(tegratab_pda_resources),
708         .dev    = {
709                 .platform_data  = &tegratab_pda_data,
710         },
711 };
712
713 static struct tegra_suspend_platform_data tegratab_suspend_data = {
714         .cpu_timer      = 300,
715         .cpu_off_timer  = 300,
716         .suspend_mode   = TEGRA_SUSPEND_LP0,
717         .core_timer     = 0x157e,
718         .core_off_timer = 2000,
719         .corereq_high   = true,
720         .sysclkreq_high = true,
721         .cpu_lp2_min_residency = 1000,
722         .min_residency_crail = 20000,
723 #ifdef CONFIG_TEGRA_LP1_LOW_COREVOLTAGE
724         .lp1_lowvolt_support = false,
725         .i2c_base_addr = 0,
726         .pmuslave_addr = 0,
727         .core_reg_addr = 0,
728         .lp1_core_volt_low = 0,
729         .lp1_core_volt_high = 0,
730 #endif
731 };
732 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
733 /* board parameters for cpu dfll */
734 static struct tegra_cl_dvfs_cfg_param tegratab_cl_dvfs_param = {
735         .sample_rate = 11500,
736
737         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
738         .cf = 10,
739         .ci = 0,
740         .cg = 2,
741
742         .droop_cut_value = 0xF,
743         .droop_restore_ramp = 0x0,
744         .scale_out_ramp = 0x0,
745 };
746 #endif
747
748 /* palmas: fixed 10mV steps from 600mV to 1400mV, with offset 0x10 */
749 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
750 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
751 static inline void fill_reg_map(void)
752 {
753         int i;
754         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
755                 pmu_cpu_vdd_map[i].reg_value = i + 0x10;
756                 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
757         }
758 }
759
760 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
761 static struct tegra_cl_dvfs_platform_data tegratab_cl_dvfs_data = {
762         .dfll_clk_name = "dfll_cpu",
763         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
764         .u.pmu_i2c = {
765                 .fs_rate = 400000,
766                 .slave_addr = 0xb0,
767                 .reg = 0x23,
768         },
769         .vdd_map = pmu_cpu_vdd_map,
770         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
771         .pmu_undershoot_gb = 100,
772
773         .cfg_param = &tegratab_cl_dvfs_param,
774 };
775
776 static int __init tegratab_cl_dvfs_init(void)
777 {
778         fill_reg_map();
779         if (tegra_revision < TEGRA_REVISION_A02)
780                 tegratab_cl_dvfs_data.flags =
781                         TEGRA_CL_DVFS_FLAGS_I2C_WAIT_QUIET;
782         tegra_cl_dvfs_device.dev.platform_data = &tegratab_cl_dvfs_data;
783         platform_device_register(&tegra_cl_dvfs_device);
784
785         return 0;
786 }
787 #endif
788
789 static int __init tegratab_fixed_regulator_init(void)
790 {
791         struct board_info board_info;
792         int ret;
793
794         if (!machine_is_tegratab())
795                 return 0;
796
797         tegra_get_board_info(&board_info);
798
799         if (board_info.board_id == BOARD_P1640)
800                 ret = platform_add_devices(fixed_reg_devs_p1640,
801                                            ARRAY_SIZE(fixed_reg_devs_p1640));
802         else
803                 ret = platform_add_devices(fixed_reg_devs_e1569,
804                                            ARRAY_SIZE(fixed_reg_devs_e1569));
805
806         return ret;
807 }
808 subsys_initcall_sync(tegratab_fixed_regulator_init);
809
810
811 int __init tegratab_regulator_init(void)
812 {
813
814 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
815         tegratab_cl_dvfs_init();
816 #endif
817         tegratab_palmas_regulator_init();
818 #ifndef CONFIG_OF
819         tegratab_max17048_boardinfo[0].irq = gpio_to_irq(TEGRA_GPIO_PQ5);
820         i2c_register_board_info(0, tegratab_max17048_boardinfo, 1);
821 #endif
822         /* Disable charger when adapter is power source. */
823         if (get_power_supply_type() != POWER_SUPPLY_TYPE_BATTERY)
824                 tegratab_bq2419x_pdata.bcharger_pdata = NULL;
825
826         tegratab_bq2419x_boardinfo[0].irq = gpio_to_irq(TEGRA_GPIO_PJ0);
827         i2c_register_board_info(0, tegratab_bq2419x_boardinfo, 1);
828
829         regulator_has_full_constraints();
830         platform_device_register(&psy_extcon_device);
831         platform_device_register(&tegratab_pda_power_device);
832
833         return 0;
834 }
835
836 int __init tegratab_power_off_init(void)
837 {
838         /* Use PMU reset only when battery is exist. */
839         if (get_power_supply_type() == POWER_SUPPLY_TYPE_BATTERY)
840                 pm_power_off = palmas_reset;
841
842         return 0;
843 }
844
845 int __init tegratab_suspend_init(void)
846 {
847         tegra_init_suspend(&tegratab_suspend_data);
848         return 0;
849 }
850
851 int __init tegratab_edp_init(void)
852 {
853         unsigned int regulator_mA;
854
855         regulator_mA = get_maximum_cpu_current_supported();
856         if (!regulator_mA)
857                 regulator_mA = 9000;
858
859         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
860         tegra_init_cpu_edp_limits(regulator_mA);
861
862         regulator_mA = get_maximum_core_current_supported();
863         if (!regulator_mA)
864                 regulator_mA = 4000;
865
866         pr_info("%s: core regulator %d mA\n", __func__, regulator_mA);
867         tegra_init_core_edp_limits(regulator_mA);
868
869         return 0;
870 }
871
872 static struct thermal_zone_params tegratab_soctherm_therm_cpu_tzp = {
873         .governor_name = "pid_thermal_gov",
874 };
875
876 static struct tegra_tsensor_pmu_data tpdata_palmas = {
877         .reset_tegra = 1,
878         .pmu_16bit_ops = 0,
879         .controller_type = 0,
880         .pmu_i2c_addr = 0x58,
881         .i2c_controller_id = 4,
882         .poweroff_reg_addr = 0xa0,
883         .poweroff_reg_data = 0x0,
884 };
885
886 static struct soctherm_platform_data tegratab_soctherm_data = {
887         .oc_irq_base = TEGRA_SOC_OC_IRQ_BASE,
888         .num_oc_irqs = TEGRA_SOC_OC_NUM_IRQ,
889         .therm = {
890                 [THERM_CPU] = {
891                         .zone_enable = true,
892                         .passive_delay = 1000,
893                         .hotspot_offset = 6000,
894                         .num_trips = 3,
895                         .trips = {
896                                 {
897                                         .cdev_type = "tegra-balanced",
898                                         .trip_temp = 90000,
899                                         .trip_type = THERMAL_TRIP_PASSIVE,
900                                         .upper = THERMAL_NO_LIMIT,
901                                         .lower = THERMAL_NO_LIMIT,
902                                 },
903                                 {
904                                         .cdev_type = "tegra-heavy",
905                                         .trip_temp = 100000,
906                                         .trip_type = THERMAL_TRIP_HOT,
907                                         .upper = THERMAL_NO_LIMIT,
908                                         .lower = THERMAL_NO_LIMIT,
909                                 },
910                                 {
911                                         .cdev_type = "tegra-shutdown",
912                                         .trip_temp = 102000,
913                                         .trip_type = THERMAL_TRIP_CRITICAL,
914                                         .upper = THERMAL_NO_LIMIT,
915                                         .lower = THERMAL_NO_LIMIT,
916                                 },
917                         },
918                         .tzp = &tegratab_soctherm_therm_cpu_tzp,
919                 },
920                 [THERM_GPU] = {
921                         .zone_enable = true,
922                         .passive_delay = 1000,
923                         .hotspot_offset = 6000,
924                         .num_trips = 3,
925                         .trips = {
926                                 {
927                                         .cdev_type = "tegra-balanced",
928                                         .trip_temp = 90000,
929                                         .trip_type = THERMAL_TRIP_PASSIVE,
930                                         .upper = THERMAL_NO_LIMIT,
931                                         .lower = THERMAL_NO_LIMIT,
932                                 },
933                                 {
934                                         .cdev_type = "tegra-heavy",
935                                         .trip_temp = 100000,
936                                         .trip_type = THERMAL_TRIP_HOT,
937                                         .upper = THERMAL_NO_LIMIT,
938                                         .lower = THERMAL_NO_LIMIT,
939                                 },
940                                 {
941                                         .cdev_type = "tegra-shutdown",
942                                         .trip_temp = 102000,
943                                         .trip_type = THERMAL_TRIP_CRITICAL,
944                                         .upper = THERMAL_NO_LIMIT,
945                                         .lower = THERMAL_NO_LIMIT,
946                                 },
947                         },
948                         .tzp = &tegratab_soctherm_therm_cpu_tzp,
949                 },
950                 [THERM_PLL] = {
951                         .zone_enable = true,
952                 },
953         },
954         .throttle = {
955                 [THROTTLE_HEAVY] = {
956                         .devs = {
957                                 [THROTTLE_DEV_CPU] = {
958                                         .enable = 1,
959                                 },
960                         },
961                 },
962                 [THROTTLE_OC4] = {
963                         .throt_mode = BRIEF,
964                         .polarity = 1,
965                         .intr = true,
966                         .devs = {
967                                 [THROTTLE_DEV_CPU] = {
968                                         .enable = true,
969                                         .depth = 50,
970                                 },
971                                 [THROTTLE_DEV_GPU] = {
972                                         .enable = true,
973                                         .depth = 50,
974                                 },
975                         },
976                 },
977         },
978         .tshut_pmu_trip_data = &tpdata_palmas,
979 };
980
981 int __init tegratab_soctherm_init(void)
982 {
983         struct board_info board_info;
984
985         tegra_get_board_info(&board_info);
986
987         /*
988          * P1640 has oc4 from ina230. E1569 has oc4 from pmic powergood
989          * Disable oc4 throttle for E1569
990          */
991         if (board_info.board_id == BOARD_E1569) {
992                 tegratab_soctherm_data.throttle[THROTTLE_OC4]
993                         .devs[THROTTLE_DEV_CPU].enable = false;
994                 tegratab_soctherm_data.throttle[THROTTLE_OC4]
995                         .devs[THROTTLE_DEV_GPU].enable = false;
996         }
997
998         tegra_platform_edp_init(tegratab_soctherm_data.therm[THERM_CPU].trips,
999                         &tegratab_soctherm_data.therm[THERM_CPU].num_trips,
1000                         6000); /* edp temperature margin */
1001         tegra_add_tj_trips(tegratab_soctherm_data.therm[THERM_CPU].trips,
1002                         &tegratab_soctherm_data.therm[THERM_CPU].num_trips);
1003         tegra_add_vc_trips(tegratab_soctherm_data.therm[THERM_CPU].trips,
1004                         &tegratab_soctherm_data.therm[THERM_CPU].num_trips);
1005
1006         if (board_info.board_id != BOARD_E1569 &&
1007                         (board_info.board_id == BOARD_P1640 &&
1008                         (board_info.fab != BOARD_FAB_A00 &&
1009                         board_info.fab != BOARD_FAB_A01))) {
1010                 tegra_add_cdev_trips(
1011                         tegratab_soctherm_data.therm[THERM_CPU].trips,
1012                         &tegratab_soctherm_data.therm[THERM_CPU].num_trips);
1013         }
1014
1015         return tegra11_soctherm_init(&tegratab_soctherm_data);
1016 }
1017
1018 #define NO_CAP  (ULONG_MAX)
1019 static struct tegra_sysedp_corecap tegratab_sysedp_lite_corecap[] = {
1020         {   9100, {   3943,    240,    624 }, {   2706,    420,    792 } },
1021         {  10000, {   4565,    240,    792 }, {   3398,    528,    792 } },
1022         {  10500, {   5065,    240,    792 }, {   3898,    528,    792 } },
1023         {  11000, {   5565,    240,    792 }, {   4398,    528,    792 } },
1024         {  12000, {   6565,    240,    792 }, {   4277,    600,    792 } },
1025         {  13000, {   7565,    240,    792 }, {   5277,    600,    792 } },
1026         {  14000, {   8565,    240,    792 }, {   6277,    600,    792 } },
1027         {  15000, {   9565,    384,    792 }, {   7277,    600,    792 } },
1028         {  16000, {  10565,    468,    792 }, {   8277,    600,    792 } },
1029         { NO_CAP, { NO_CAP, NO_CAP, NO_CAP }, { NO_CAP, NO_CAP, NO_CAP } },
1030 };
1031
1032 static struct tegra_sysedp_platform_data tegratab_sysedp_lite_platdata = {
1033         .corecap = tegratab_sysedp_lite_corecap,
1034         .corecap_size = ARRAY_SIZE(tegratab_sysedp_lite_corecap),
1035 };
1036
1037 static struct platform_device tegratab_sysedp_lite_device = {
1038         .name = "tegra_sysedp_lite",
1039         .id = -1,
1040         .dev = { .platform_data = &tegratab_sysedp_lite_platdata }
1041 };
1042
1043 void __init tegratab_sysedp_core_init(void)
1044 {
1045         int r;
1046
1047         tegratab_sysedp_lite_platdata.cpufreq_lim =
1048                 tegra_get_system_edp_entries(
1049                         &tegratab_sysedp_lite_platdata.cpufreq_lim_size);
1050         if (!tegratab_sysedp_lite_platdata.cpufreq_lim) {
1051                 WARN_ON(1);
1052                 return;
1053         }
1054
1055         r = platform_device_register(&tegratab_sysedp_lite_device);
1056         WARN_ON(r);
1057 }