4a92a00f76aa1133d046c3bd7d4bb8618015e6d5
[linux-2.6.git] / arch / arm / mach-tegra / board-tegratab-power.c
1 /*
2  * arch/arm/mach-tegra/board-tegratab-power.c
3  *
4  * Copyright (C) 2012-2013 NVIDIA Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
24 #include <linux/io.h>
25 #include <linux/regulator/machine.h>
26 #include <linux/regulator/driver.h>
27 #include <linux/regulator/fixed.h>
28 #include <linux/mfd/palmas.h>
29 #include <linux/power/bq2419x-charger.h>
30 #include <linux/max17048_battery.h>
31 #include <linux/gpio.h>
32 #include <linux/interrupt.h>
33 #include <linux/regulator/userspace-consumer.h>
34
35 #include <asm/mach-types.h>
36 #include <linux/power/sbs-battery.h>
37
38 #include <mach/iomap.h>
39 #include <mach/irqs.h>
40 #include <mach/hardware.h>
41 #include <mach/edp.h>
42 #include <mach/gpio-tegra.h>
43
44 #include "cpu-tegra.h"
45 #include "pm.h"
46 #include "tegra-board-id.h"
47 #include "board-pmu-defines.h"
48 #include "board.h"
49 #include "gpio-names.h"
50 #include "board-common.h"
51 #include "board-tegratab.h"
52 #include "tegra_cl_dvfs.h"
53 #include "devices.h"
54 #include "tegra11_soctherm.h"
55 #include "tegra3_tsensor.h"
56
57 #define PMC_CTRL                0x0
58 #define PMC_CTRL_INTR_LOW       (1 << 17)
59
60 /* BQ2419X VBUS regulator */
61 static struct regulator_consumer_supply tegratab_bq2419x_vbus_supply[] = {
62         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
63 };
64
65 static struct regulator_consumer_supply tegratab_bq2419x_batt_supply[] = {
66         REGULATOR_SUPPLY("usb_bat_chg", "tegra-udc.0"),
67 };
68
69 static struct bq2419x_vbus_platform_data tegratab_bq2419x_vbus_pdata = {
70         .gpio_otg_iusb = TEGRA_GPIO_PI4,
71         .num_consumer_supplies = ARRAY_SIZE(tegratab_bq2419x_vbus_supply),
72         .consumer_supplies = tegratab_bq2419x_vbus_supply,
73 };
74
75 struct bq2419x_charger_platform_data tegratab_bq2419x_charger_pdata = {
76         .use_usb = 1,
77         .use_mains = 1,
78         .update_status = max17048_battery_status,
79         .battery_check = max17048_check_battery,
80         .max_charge_current_mA = 3000,
81         .charging_term_current_mA = 100,
82         .consumer_supplies = tegratab_bq2419x_batt_supply,
83         .num_consumer_supplies = ARRAY_SIZE(tegratab_bq2419x_batt_supply),
84         .wdt_timeout    = 40,
85 };
86
87 #ifndef CONFIG_OF
88 struct max17048_battery_model tegratab_max17048_mdata = {
89         .rcomp          = 57,
90         .soccheck_A     = 119,
91         .soccheck_B     = 121,
92         .bits           = 18,
93         .alert_threshold = 0x01,        /* 1% SOC */
94         .one_percent_alerts = 0x40,
95         .alert_on_reset = 0x00,         /* not use */
96         .rcomp_seg      = 0x0200,
97         .hibernate      = 0x3080,
98         .vreset         = 0x3c96,
99         .valert         = 0x00FF,       /* not use */
100         .ocvtest        = 55952,
101         .data_tbl = {
102                 0x98, 0x80, 0xB3, 0x50, 0xB7, 0x90, 0xB9, 0x00,
103                 0xBA, 0x70, 0xBC, 0x10, 0xBC, 0x50, 0xBC, 0xA0,
104                 0xBD, 0x20, 0xBE, 0x30, 0xBF, 0x40, 0xC2, 0xF0,
105                 0xC4, 0x20, 0xC7, 0xE0, 0xCB, 0xF0, 0xD0, 0x90,
106                 0x00, 0x40, 0x06, 0x70, 0x0E, 0x50, 0x12, 0x00,
107                 0x18, 0xD0, 0x33, 0x10, 0x31, 0x40, 0x35, 0xD0,
108                 0x18, 0xD0, 0x19, 0x00, 0x0B, 0xF0, 0x0C, 0x10,
109                 0x0D, 0x10, 0x07, 0x90, 0x08, 0x00, 0x08, 0x00,
110         },
111 };
112
113 struct max17048_platform_data tegratab_max17048_pdata = {
114         .use_ac = 0,
115         .use_usb = 0,
116         .model_data = &tegratab_max17048_mdata,
117 };
118
119 static struct i2c_board_info __initdata tegratab_max17048_boardinfo[] = {
120         {
121                 I2C_BOARD_INFO("max17048", 0x36),
122                 .platform_data  = &tegratab_max17048_pdata,
123         },
124 };
125 #endif
126
127 struct bq2419x_platform_data tegratab_bq2419x_pdata = {
128         .vbus_pdata = &tegratab_bq2419x_vbus_pdata,
129         .bcharger_pdata = &tegratab_bq2419x_charger_pdata,
130 };
131
132 static struct i2c_board_info __initdata tegratab_bq2419x_boardinfo[] = {
133         {
134                 I2C_BOARD_INFO("bq2419x", 0x6b),
135                 .platform_data = &tegratab_bq2419x_pdata,
136         },
137 };
138
139 /************************ Tegratab based regulator ****************/
140 static struct regulator_consumer_supply palmas_smps123_supply[] = {
141         REGULATOR_SUPPLY("vdd_cpu", NULL),
142 };
143
144 static struct regulator_consumer_supply palmas_smps45_supply[] = {
145         REGULATOR_SUPPLY("vdd_core", NULL),
146         REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.0"),
147         REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.3"),
148 };
149
150 static struct regulator_consumer_supply palmas_smps6_supply[] = {
151         REGULATOR_SUPPLY("vdd_lcd_hv", NULL),
152         REGULATOR_SUPPLY("avdd_lcd", NULL),
153         REGULATOR_SUPPLY("avdd", "spi0.0"),
154 };
155
156 static struct regulator_consumer_supply palmas_smps7_supply[] = {
157         REGULATOR_SUPPLY("vddio_ddr", NULL),
158 };
159
160 static struct regulator_consumer_supply palmas_smps8_supply[] = {
161         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
162         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
163         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
164         REGULATOR_SUPPLY("avdd_osc", NULL),
165         REGULATOR_SUPPLY("vddio_sys", NULL),
166         REGULATOR_SUPPLY("vddio_bb", NULL),
167         REGULATOR_SUPPLY("pwrdet_bb", NULL),
168         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
169         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
170         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
171         REGULATOR_SUPPLY("vdd_emmc", "sdhci-tegra.3"),
172         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
173         REGULATOR_SUPPLY("vddio_audio", NULL),
174         REGULATOR_SUPPLY("pwrdet_audio", NULL),
175         REGULATOR_SUPPLY("vddio_uart", NULL),
176         REGULATOR_SUPPLY("pwrdet_uart", NULL),
177         REGULATOR_SUPPLY("vddio_gmi", NULL),
178         REGULATOR_SUPPLY("pwrdet_nand", NULL),
179         REGULATOR_SUPPLY("vlogic", "0-0069"),
180         REGULATOR_SUPPLY("vid", "0-000d"),
181         REGULATOR_SUPPLY("vddio", "0-0078"),
182         REGULATOR_SUPPLY("vdd", "0-004c"),
183 };
184
185 static struct regulator_consumer_supply palmas_smps9_supply[] = {
186         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
187         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
188         REGULATOR_SUPPLY("pwrdet_hv", NULL),
189 };
190
191 static struct regulator_consumer_supply palmas_smps10_supply[] = {
192 };
193
194 static struct regulator_consumer_supply palmas_ldo1_supply[] = {
195         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
196         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
197         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
198         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "vi"),
199         REGULATOR_SUPPLY("avdd_pllm", NULL),
200         REGULATOR_SUPPLY("avdd_pllu", NULL),
201         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
202         REGULATOR_SUPPLY("avdd_pllx", NULL),
203         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
204         REGULATOR_SUPPLY("avdd_plle", NULL),
205 };
206
207 static struct regulator_consumer_supply palmas_ldo2_supply[] = {
208         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
209         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
210         REGULATOR_SUPPLY("avdd_dsi_csi", "vi"),
211         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
212         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
213         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
214 };
215
216 static struct regulator_consumer_supply palmas_ldo3_supply[] = {
217         REGULATOR_SUPPLY("vpp_fuse", NULL),
218 };
219
220 static struct regulator_consumer_supply palmas_ldo4_supply[] = {
221         REGULATOR_SUPPLY("dvdd", "2-0010"),
222 };
223
224 static struct regulator_consumer_supply palmas_ldo5_supply[] = {
225 #ifdef CONFIG_USE_OF
226         REGULATOR_SUPPLY("ext_vcm_vdd", "2-0010"),
227 #else
228         REGULATOR_SUPPLY("vdd_af_cam1", NULL),
229 #endif
230         REGULATOR_SUPPLY("vdd", "2-000c"),
231         REGULATOR_SUPPLY("vana", "2-0048"),
232         REGULATOR_SUPPLY("vana", "2-0021"),
233 };
234
235 static struct regulator_consumer_supply palmas_ldo6_supply[] = {
236         REGULATOR_SUPPLY("vdd", "0-0069"),
237         REGULATOR_SUPPLY("vdd", "0-000d"),
238         REGULATOR_SUPPLY("vdd", "0-0078"),
239 };
240
241 static struct regulator_consumer_supply palmas_ldo7_supply[] = {
242         REGULATOR_SUPPLY("avdd", "2-0010"),
243 };
244 static struct regulator_consumer_supply palmas_ldo8_supply[] = {
245         REGULATOR_SUPPLY("vdd_rtc", NULL),
246 };
247 static struct regulator_consumer_supply palmas_ldo9_supply[] = {
248         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
249         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
250 };
251 static struct regulator_consumer_supply palmas_ldoln_supply[] = {
252         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
253 };
254
255 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
256         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
257         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
258         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
259         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
260         REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
261
262 };
263
264 static struct regulator_consumer_supply palmas_regen1_supply[] = {
265 };
266
267 static struct regulator_consumer_supply palmas_regen2_supply[] = {
268 };
269
270 PALMAS_REGS_PDATA(smps123, 900,  1300, NULL, 0, 0, 0, 0,
271         0, PALMAS_EXT_CONTROL_ENABLE1, 0, 3, 0);
272 PALMAS_REGS_PDATA(smps45, 900,  1400, NULL, 0, 0, 0, 0,
273         0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
274 PALMAS_REGS_PDATA(smps6, 3200,  3200, NULL, 0, 0, 1, NORMAL,
275         0, 0, 0, 0, 0);
276 PALMAS_REGS_PDATA(smps7, 1350,  1350, NULL, 0, 0, 1, NORMAL,
277         0, 0, 0, 0, 0);
278 PALMAS_REGS_PDATA(smps8, 1800,  1800, NULL, 1, 1, 1, NORMAL,
279         0, 0, 0, 0, 0);
280 PALMAS_REGS_PDATA(smps9, 2900,  2900, NULL, 1, 0, 1, NORMAL,
281         0, 0, 0, 0, 0);
282 PALMAS_REGS_PDATA(smps10, 5000,  5000, NULL, 0, 0, 0, 0,
283         0, 0, 0, 0, 0);
284 PALMAS_REGS_PDATA(ldo1, 1050,  1050, palmas_rails(smps7), 1, 0, 1, 0,
285         0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
286 PALMAS_REGS_PDATA(ldo2, 1200,  1200, palmas_rails(smps7), 0, 1, 1, 0,
287         0, 0, 0, 0, 0);
288 PALMAS_REGS_PDATA(ldo3, 1800,  1800, NULL, 0, 0, 1, 0,
289         0, 0, 0, 0, 0);
290 PALMAS_REGS_PDATA(ldo4, 1200,  1200, palmas_rails(smps8), 0, 0, 1, 0,
291         0, 0, 0, 0, 0);
292 PALMAS_REGS_PDATA(ldo5, 2700,  2700, palmas_rails(smps9), 0, 0, 1, 0,
293         0, 0, 0, 0, 0);
294 PALMAS_REGS_PDATA(ldo6, 2850,  2850, palmas_rails(smps9), 0, 1, 1, 0,
295         0, 0, 0, 0, 0);
296 PALMAS_REGS_PDATA(ldo7, 2700,  2700, palmas_rails(smps9), 0, 0, 1, 0,
297         0, 0, 0, 0, 0);
298 PALMAS_REGS_PDATA(ldo8, 950,  950, NULL, 1, 1, 1, 0,
299         0, 0, 0, 0, 0);
300 PALMAS_REGS_PDATA(ldo9, 1800,  2900, palmas_rails(smps9), 0, 0, 1, 0,
301         0, 0, 0, 0, 0);
302 PALMAS_REGS_PDATA(ldoln, 3300,   3300, NULL, 0, 0, 1, 0,
303         0, 0, 0, 0, 0);
304 PALMAS_REGS_PDATA(ldousb, 3300,  3300, NULL, 0, 0, 1, 0,
305         0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
306 PALMAS_REGS_PDATA(regen1, 4200,  4200, NULL, 0, 0, 0, 0,
307         0, 0, 0, 0, 0);
308 PALMAS_REGS_PDATA(regen2, 4200,  4200, palmas_rails(smps8), 0, 0, 0, 0,
309         0, 0, 0, 0, 0);
310
311 #define PALMAS_REG_PDATA(_sname) (&reg_idata_##_sname)
312 static struct regulator_init_data *tegratab_reg_data[PALMAS_NUM_REGS] = {
313         NULL,
314         PALMAS_REG_PDATA(smps123),
315         NULL,
316         PALMAS_REG_PDATA(smps45),
317         NULL,
318         PALMAS_REG_PDATA(smps6),
319         PALMAS_REG_PDATA(smps7),
320         PALMAS_REG_PDATA(smps8),
321         PALMAS_REG_PDATA(smps9),
322         PALMAS_REG_PDATA(smps10),
323         PALMAS_REG_PDATA(ldo1),
324         PALMAS_REG_PDATA(ldo2),
325         PALMAS_REG_PDATA(ldo3),
326         PALMAS_REG_PDATA(ldo4),
327         PALMAS_REG_PDATA(ldo5),
328         PALMAS_REG_PDATA(ldo6),
329         PALMAS_REG_PDATA(ldo7),
330         PALMAS_REG_PDATA(ldo8),
331         PALMAS_REG_PDATA(ldo9),
332         PALMAS_REG_PDATA(ldoln),
333         PALMAS_REG_PDATA(ldousb),
334         PALMAS_REG_PDATA(regen1),
335         PALMAS_REG_PDATA(regen2),
336         NULL,
337         NULL,
338         NULL,
339 };
340
341 #define PALMAS_REG_INIT_DATA(_sname) (&reg_init_data_##_sname)
342 static struct palmas_reg_init *tegratab_reg_init[PALMAS_NUM_REGS] = {
343         NULL,
344         PALMAS_REG_INIT_DATA(smps123),
345         NULL,
346         PALMAS_REG_INIT_DATA(smps45),
347         NULL,
348         PALMAS_REG_INIT_DATA(smps6),
349         PALMAS_REG_INIT_DATA(smps7),
350         PALMAS_REG_INIT_DATA(smps8),
351         PALMAS_REG_INIT_DATA(smps9),
352         PALMAS_REG_INIT_DATA(smps10),
353         PALMAS_REG_INIT_DATA(ldo1),
354         PALMAS_REG_INIT_DATA(ldo2),
355         PALMAS_REG_INIT_DATA(ldo3),
356         PALMAS_REG_INIT_DATA(ldo4),
357         PALMAS_REG_INIT_DATA(ldo5),
358         PALMAS_REG_INIT_DATA(ldo6),
359         PALMAS_REG_INIT_DATA(ldo7),
360         PALMAS_REG_INIT_DATA(ldo8),
361         PALMAS_REG_INIT_DATA(ldo9),
362         PALMAS_REG_INIT_DATA(ldoln),
363         PALMAS_REG_INIT_DATA(ldousb),
364         PALMAS_REG_INIT_DATA(regen1),
365         PALMAS_REG_INIT_DATA(regen2),
366         NULL,
367         NULL,
368         NULL,
369 };
370
371 static struct palmas_pmic_platform_data pmic_platform = {
372         .enable_ldo8_tracking = true,
373         .disabe_ldo8_tracking_suspend = true,
374         .disable_smps10_boost_suspend = true,
375 };
376
377 static struct palmas_pinctrl_config palmas_pincfg[] = {
378         PALMAS_PINMUX(POWERGOOD, POWERGOOD, DEFAULT, DEFAULT),
379         PALMAS_PINMUX(VAC, VAC, DEFAULT, DEFAULT),
380         PALMAS_PINMUX(GPIO0, GPIO, DEFAULT, DEFAULT),
381         PALMAS_PINMUX(GPIO1, GPIO, DEFAULT, DEFAULT),
382         PALMAS_PINMUX(GPIO2, GPIO, DEFAULT, DEFAULT),
383         PALMAS_PINMUX(GPIO3, GPIO, DEFAULT, DEFAULT),
384         PALMAS_PINMUX(GPIO4, GPIO, DEFAULT, DEFAULT),
385         PALMAS_PINMUX(GPIO5, GPIO, DEFAULT, DEFAULT),
386         PALMAS_PINMUX(GPIO6, GPIO, DEFAULT, DEFAULT),
387         PALMAS_PINMUX(GPIO7, GPIO, DEFAULT, DEFAULT),
388 };
389
390 static struct palmas_pinctrl_platform_data palmas_pinctrl_pdata = {
391         .pincfg = palmas_pincfg,
392         .num_pinctrl = ARRAY_SIZE(palmas_pincfg),
393         .dvfs1_enable = true,
394         .dvfs2_enable = false,
395 };
396
397 static struct palmas_extcon_platform_data palmas_extcon_pdata = {
398         .connection_name = "palmas-extcon",
399         .enable_vbus_detection = true,
400         .enable_id_pin_detection = true,
401 };
402
403 static struct palmas_platform_data palmas_pdata = {
404         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
405         .irq_base = PALMAS_TEGRA_IRQ_BASE,
406         .pmic_pdata = &pmic_platform,
407         .use_power_off = true,
408         .pinctrl_pdata = &palmas_pinctrl_pdata,
409         .extcon_pdata = &palmas_extcon_pdata,
410 };
411
412 static struct i2c_board_info palma_device[] = {
413         {
414                 I2C_BOARD_INFO("tps65913", 0x58),
415                 .irq            = INT_EXTERNAL_PMU,
416                 .platform_data  = &palmas_pdata,
417         },
418 };
419
420 static struct regulator_consumer_supply fixed_reg_dvdd_lcd_1v8_supply[] = {
421         REGULATOR_SUPPLY("dvdd_lcd", NULL),
422 };
423
424 static struct regulator_consumer_supply fixed_reg_vdd_lcd_bl_en_supply[] = {
425         REGULATOR_SUPPLY("vdd_lcd_bl_en", NULL),
426 };
427
428 /* EN_1V8_TS From TEGRA_GPIO_PH4 */
429 static struct regulator_consumer_supply fixed_reg_dvdd_ts_supply[] = {
430         REGULATOR_SUPPLY("dvdd", "spi0.0"),
431 };
432
433 /* ENABLE 5v0 for HDMI */
434 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = {
435         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
436 };
437
438 static struct regulator_consumer_supply fixed_reg_vddio_sd_slot_supply[] = {
439         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
440 };
441
442 static struct regulator_consumer_supply fixed_reg_vd_cam_1v8_supply[] = {
443         REGULATOR_SUPPLY("dovdd", "2-0010"),
444         REGULATOR_SUPPLY("vif2", "2-0048"),
445         REGULATOR_SUPPLY("vif2", "2-0021"),
446         REGULATOR_SUPPLY("vddio_cam", "vi"),
447         REGULATOR_SUPPLY("pwrdet_cam", NULL),
448 };
449
450 static struct regulator_consumer_supply fixed_reg_en_lcd_1v8_supply[] = {
451         REGULATOR_SUPPLY("dvdd_lcd", NULL),
452         REGULATOR_SUPPLY("dvdd", "spi0.0"),
453 };
454
455 /* Macro for defining fixed regulator sub device data */
456 #define FIXED_SUPPLY(_name) "fixed_reg_"#_name
457 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,   \
458         _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts)  \
459         static struct regulator_init_data ri_data_##_var =              \
460         {                                                               \
461                 .supply_regulator = _in_supply,                         \
462                 .num_consumer_supplies =                                \
463                         ARRAY_SIZE(fixed_reg_##_name##_supply),         \
464                 .consumer_supplies = fixed_reg_##_name##_supply,        \
465                 .constraints = {                                        \
466                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
467                                         REGULATOR_MODE_STANDBY),        \
468                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
469                                         REGULATOR_CHANGE_STATUS |       \
470                                         REGULATOR_CHANGE_VOLTAGE),      \
471                         .always_on = _always_on,                        \
472                         .boot_on = _boot_on,                            \
473                 },                                                      \
474         };                                                              \
475         static struct fixed_voltage_config fixed_reg_##_var##_pdata =   \
476         {                                                               \
477                 .supply_name = FIXED_SUPPLY(_name),                     \
478                 .microvolts = _millivolts * 1000,                       \
479                 .gpio = _gpio_nr,                                       \
480                 .gpio_is_open_drain = _open_drain,                      \
481                 .enable_high = _active_high,                            \
482                 .enabled_at_boot = _boot_state,                         \
483                 .init_data = &ri_data_##_var,                           \
484         };                                                              \
485         static struct platform_device fixed_reg_##_var##_dev = {        \
486                 .name = "reg-fixed-voltage",                            \
487                 .id = _id,                                              \
488                 .dev = {                                                \
489                         .platform_data = &fixed_reg_##_var##_pdata,     \
490                 },                                                      \
491         }
492
493 /*
494  * Creating the fixed regulator device table
495  */
496
497 FIXED_REG(1,    dvdd_lcd_1v8,   dvdd_lcd_1v8,
498         palmas_rails(smps8),    0,      1,
499         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO4,  false,  true,   1,      1800);
500
501 FIXED_REG(2,    vdd_lcd_bl_en,  vdd_lcd_bl_en,
502         NULL,   0,      1,
503         TEGRA_GPIO_PH2, false,  true,   1,      3700);
504
505 FIXED_REG(3,    dvdd_ts,        dvdd_ts,
506         palmas_rails(smps8),    0,      0,
507         TEGRA_GPIO_PH4, false,  false,  1,      1800);
508
509 FIXED_REG(4,    vdd_hdmi_5v0,   vdd_hdmi_5v0,
510         palmas_rails(smps10),   0,      0,
511         TEGRA_GPIO_PK6, true,   true,   0,      5000);
512
513 FIXED_REG(5,    vddio_sd_slot,  vddio_sd_slot,
514         palmas_rails(smps9),    0,      0,
515         TEGRA_GPIO_PK1, false,  true,   0,      2900);
516
517 FIXED_REG(6,    vd_cam_1v8,     vd_cam_1v8,
518         palmas_rails(smps8),    0,      0,
519         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO6,  false,  true,   0,      1800);
520
521 FIXED_REG(7,    en_lcd_1v8,     en_lcd_1v8,
522         palmas_rails(smps8),    0,      1,
523         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO4,  false,  true,   1,      1800);
524
525 /*
526  * Creating the fixed regulator device tables
527  */
528 #define ADD_FIXED_REG(_name)    (&fixed_reg_##_name##_dev)
529
530 #define TEGRATAB_COMMON_FIXED_REG               \
531         ADD_FIXED_REG(vdd_lcd_bl_en),           \
532         ADD_FIXED_REG(vdd_hdmi_5v0),            \
533         ADD_FIXED_REG(vddio_sd_slot),           \
534         ADD_FIXED_REG(vd_cam_1v8),
535
536 #define E1569_FIXED_REG                         \
537         ADD_FIXED_REG(dvdd_lcd_1v8),            \
538         ADD_FIXED_REG(dvdd_ts),
539
540 #define P1640_FIXED_REG                         \
541         ADD_FIXED_REG(en_lcd_1v8),
542
543 /* Gpio switch regulator platform data for Tegratab E1569 */
544 static struct platform_device *fixed_reg_devs_e1569[] = {
545         TEGRATAB_COMMON_FIXED_REG
546         E1569_FIXED_REG
547 };
548
549 /* Gpio switch regulator platform data for Tegratab P1640 */
550 static struct platform_device *fixed_reg_devs_p1640[] = {
551         TEGRATAB_COMMON_FIXED_REG
552         P1640_FIXED_REG
553 };
554
555 int __init tegratab_palmas_regulator_init(void)
556 {
557         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
558         u32 pmc_ctrl;
559         int i;
560
561         /* TPS65913: Normal state of INT request line is LOW.
562          * configure the power management controller to trigger PMU
563          * interrupts when HIGH.
564          */
565         pmc_ctrl = readl(pmc + PMC_CTRL);
566         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
567         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
568                 pmic_platform.reg_data[i] = tegratab_reg_data[i];
569                 pmic_platform.reg_init[i] = tegratab_reg_init[i];
570         }
571
572         i2c_register_board_info(4, palma_device,
573                         ARRAY_SIZE(palma_device));
574         return 0;
575 }
576
577 static int ac_online(void)
578 {
579         return 1;
580 }
581
582 static struct resource tegratab_pda_resources[] = {
583         [0] = {
584                 .name   = "ac",
585         },
586 };
587
588 static struct pda_power_pdata tegratab_pda_data = {
589         .is_ac_online   = ac_online,
590 };
591
592 static struct platform_device tegratab_pda_power_device = {
593         .name           = "pda-power",
594         .id             = -1,
595         .resource       = tegratab_pda_resources,
596         .num_resources  = ARRAY_SIZE(tegratab_pda_resources),
597         .dev    = {
598                 .platform_data  = &tegratab_pda_data,
599         },
600 };
601
602 static struct tegra_suspend_platform_data tegratab_suspend_data = {
603         .cpu_timer      = 300,
604         .cpu_off_timer  = 300,
605         .suspend_mode   = TEGRA_SUSPEND_LP0,
606         .core_timer     = 0x157e,
607         .core_off_timer = 2000,
608         .corereq_high   = true,
609         .sysclkreq_high = true,
610         .cpu_lp2_min_residency = 1000,
611         .min_residency_crail = 20000,
612 #ifdef CONFIG_TEGRA_LP1_LOW_COREVOLTAGE
613         .lp1_lowvolt_support = false,
614         .i2c_base_addr = 0,
615         .pmuslave_addr = 0,
616         .core_reg_addr = 0,
617         .lp1_core_volt_low = 0,
618         .lp1_core_volt_high = 0,
619 #endif
620 };
621 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
622 /* board parameters for cpu dfll */
623 static struct tegra_cl_dvfs_cfg_param tegratab_cl_dvfs_param = {
624         .sample_rate = 11500,
625
626         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
627         .cf = 10,
628         .ci = 0,
629         .cg = 2,
630
631         .droop_cut_value = 0xF,
632         .droop_restore_ramp = 0x0,
633         .scale_out_ramp = 0x0,
634 };
635 #endif
636
637 /* palmas: fixed 10mV steps from 600mV to 1400mV, with offset 0x10 */
638 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
639 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
640 static inline void fill_reg_map(void)
641 {
642         int i;
643         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
644                 pmu_cpu_vdd_map[i].reg_value = i + 0x10;
645                 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
646         }
647 }
648
649 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
650 static struct tegra_cl_dvfs_platform_data tegratab_cl_dvfs_data = {
651         .dfll_clk_name = "dfll_cpu",
652         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
653         .u.pmu_i2c = {
654                 .fs_rate = 400000,
655                 .slave_addr = 0xb0,
656                 .reg = 0x23,
657         },
658         .vdd_map = pmu_cpu_vdd_map,
659         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
660
661         .cfg_param = &tegratab_cl_dvfs_param,
662 };
663
664 static int __init tegratab_cl_dvfs_init(void)
665 {
666         fill_reg_map();
667         if (tegra_revision < TEGRA_REVISION_A02)
668                 tegratab_cl_dvfs_data.flags =
669                         TEGRA_CL_DVFS_FLAGS_I2C_WAIT_QUIET;
670         tegra_cl_dvfs_device.dev.platform_data = &tegratab_cl_dvfs_data;
671         platform_device_register(&tegra_cl_dvfs_device);
672
673         return 0;
674 }
675 #endif
676
677 static int __init tegratab_fixed_regulator_init(void)
678 {
679         struct board_info board_info;
680         int ret;
681
682         if (!machine_is_tegratab())
683                 return 0;
684
685         tegra_get_board_info(&board_info);
686
687         if (board_info.board_id == BOARD_P1640)
688                 ret = platform_add_devices(fixed_reg_devs_p1640,
689                                            ARRAY_SIZE(fixed_reg_devs_p1640));
690         else
691                 ret = platform_add_devices(fixed_reg_devs_e1569,
692                                            ARRAY_SIZE(fixed_reg_devs_e1569));
693
694         return ret;
695 }
696 subsys_initcall_sync(tegratab_fixed_regulator_init);
697
698
699 int __init tegratab_regulator_init(void)
700 {
701
702 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
703         tegratab_cl_dvfs_init();
704 #endif
705         tegratab_palmas_regulator_init();
706 #ifndef CONFIG_OF
707         tegratab_max17048_boardinfo[0].irq = gpio_to_irq(TEGRA_GPIO_PQ5);
708         i2c_register_board_info(0, tegratab_max17048_boardinfo, 1);
709 #endif
710         /* Disable charger when adapter is power source. */
711         if (get_power_supply_type() != POWER_SUPPLY_TYPE_BATTERY)
712                 tegratab_bq2419x_pdata.bcharger_pdata = NULL;
713
714         tegratab_bq2419x_boardinfo[0].irq = gpio_to_irq(TEGRA_GPIO_PJ0);
715         i2c_register_board_info(0, tegratab_bq2419x_boardinfo, 1);
716
717         platform_device_register(&tegratab_pda_power_device);
718
719         return 0;
720 }
721
722 int __init tegratab_power_off_init(void)
723 {
724         /* Use PMU reset only when battery is exist. */
725         if (get_power_supply_type() == POWER_SUPPLY_TYPE_BATTERY)
726                 pm_power_off = palmas_reset;
727
728         return 0;
729 }
730
731 int __init tegratab_suspend_init(void)
732 {
733         tegra_init_suspend(&tegratab_suspend_data);
734         return 0;
735 }
736
737 int __init tegratab_edp_init(void)
738 {
739         unsigned int regulator_mA;
740
741         regulator_mA = get_maximum_cpu_current_supported();
742         if (!regulator_mA)
743                 regulator_mA = 9000;
744
745         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
746         tegra_init_cpu_edp_limits(regulator_mA);
747
748         regulator_mA = get_maximum_core_current_supported();
749         if (!regulator_mA)
750                 regulator_mA = 4000;
751
752         pr_info("%s: core regulator %d mA\n", __func__, regulator_mA);
753         tegra_init_core_edp_limits(regulator_mA);
754
755         return 0;
756 }
757
758 static struct thermal_zone_params tegratab_soctherm_therm_cpu_tzp = {
759         .governor_name = "pid_thermal_gov",
760 };
761
762 static struct tegra_tsensor_pmu_data tpdata_palmas = {
763         .reset_tegra = 1,
764         .pmu_16bit_ops = 0,
765         .controller_type = 0,
766         .pmu_i2c_addr = 0x58,
767         .i2c_controller_id = 4,
768         .poweroff_reg_addr = 0xa0,
769         .poweroff_reg_data = 0x0,
770 };
771
772 static struct soctherm_platform_data tegratab_soctherm_data = {
773         .therm = {
774                 [THERM_CPU] = {
775                         .zone_enable = true,
776                         .passive_delay = 1000,
777                         .hotspot_offset = 6000,
778                         .num_trips = 3,
779                         .trips = {
780                                 {
781                                         .cdev_type = "tegra-balanced",
782                                         .trip_temp = 90000,
783                                         .trip_type = THERMAL_TRIP_PASSIVE,
784                                         .upper = THERMAL_NO_LIMIT,
785                                         .lower = THERMAL_NO_LIMIT,
786                                 },
787                                 {
788                                         .cdev_type = "tegra-heavy",
789                                         .trip_temp = 100000,
790                                         .trip_type = THERMAL_TRIP_HOT,
791                                         .upper = THERMAL_NO_LIMIT,
792                                         .lower = THERMAL_NO_LIMIT,
793                                 },
794                                 {
795                                         .cdev_type = "tegra-shutdown",
796                                         .trip_temp = 102000,
797                                         .trip_type = THERMAL_TRIP_CRITICAL,
798                                         .upper = THERMAL_NO_LIMIT,
799                                         .lower = THERMAL_NO_LIMIT,
800                                 },
801                         },
802                         .tzp = &tegratab_soctherm_therm_cpu_tzp,
803                 },
804                 [THERM_GPU] = {
805                         .zone_enable = true,
806                         .hotspot_offset = 6000,
807                 },
808                 [THERM_PLL] = {
809                         .zone_enable = true,
810                 },
811         },
812         .throttle = {
813                 [THROTTLE_HEAVY] = {
814                         .devs = {
815                                 [THROTTLE_DEV_CPU] = {
816                                         .enable = 1,
817                                 },
818                         },
819                 },
820         },
821         .tshut_pmu_trip_data = &tpdata_palmas,
822 };
823
824 int __init tegratab_soctherm_init(void)
825 {
826         tegra_platform_edp_init(tegratab_soctherm_data.therm[THERM_CPU].trips,
827                         &tegratab_soctherm_data.therm[THERM_CPU].num_trips,
828                         6000); /* edp temperature margin */
829         tegra_add_tj_trips(tegratab_soctherm_data.therm[THERM_CPU].trips,
830                         &tegratab_soctherm_data.therm[THERM_CPU].num_trips);
831         tegra_add_vc_trips(tegratab_soctherm_data.therm[THERM_CPU].trips,
832                         &tegratab_soctherm_data.therm[THERM_CPU].num_trips);
833
834         return tegra11_soctherm_init(&tegratab_soctherm_data);
835 }