arm: tegra: t11x: cpu rail power good timer
[linux-2.6.git] / arch / arm / mach-tegra / board-pluto-power.c
1 /*
2  * arch/arm/mach-tegra/board-pluto-power.c
3  *
4  * Copyright (C) 2012 NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
24 #include <linux/io.h>
25
26 #include <mach/iomap.h>
27 #include <mach/edp.h>
28 #include <mach/irqs.h>
29 #include <linux/regulator/fixed.h>
30 #include <linux/mfd/palmas.h>
31 #include <linux/regulator/machine.h>
32 #include <linux/irq.h>
33
34 #include <asm/mach-types.h>
35
36 #include "cpu-tegra.h"
37 #include "pm.h"
38 #include "board.h"
39 #include "board-pluto.h"
40 #include "tegra_cl_dvfs.h"
41 #include "devices.h"
42 #include "tegra11_soctherm.h"
43
44 #define PMC_CTRL                0x0
45 #define PMC_CTRL_INTR_LOW       (1 << 17)
46
47 /************************ Pluto based regulator ****************/
48 static struct regulator_consumer_supply palmas_smps123_supply[] = {
49         REGULATOR_SUPPLY("vdd_cpu", NULL),
50 };
51
52 static struct regulator_consumer_supply palmas_smps45_supply[] = {
53         REGULATOR_SUPPLY("vdd_core", NULL),
54 };
55
56 static struct regulator_consumer_supply palmas_smps6_supply[] = {
57         REGULATOR_SUPPLY("vdd_core_bb", NULL),
58 };
59
60 static struct regulator_consumer_supply palmas_smps7_supply[] = {
61         REGULATOR_SUPPLY("vddio_ddr", NULL),
62         REGULATOR_SUPPLY("vddio_lpddr3", NULL),
63         REGULATOR_SUPPLY("vcore2_lpddr3", NULL),
64         REGULATOR_SUPPLY("vcore_audio_1v2", NULL),
65 };
66
67 static struct regulator_consumer_supply palmas_smps8_supply[] = {
68         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
69         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
70         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
71         REGULATOR_SUPPLY("avdd_osc", NULL),
72         REGULATOR_SUPPLY("vddio_sys", NULL),
73         REGULATOR_SUPPLY("vddio_bb", NULL),
74         REGULATOR_SUPPLY("pwrdet_bb", NULL),
75         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
76         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
77         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
78         REGULATOR_SUPPLY("vdd_emmc", "sdhci-tegra.3"),
79         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
80         REGULATOR_SUPPLY("vddio_audio", NULL),
81         REGULATOR_SUPPLY("pwrdet_audio", NULL),
82         REGULATOR_SUPPLY("vddio_uart", NULL),
83         REGULATOR_SUPPLY("pwrdet_uart", NULL),
84         REGULATOR_SUPPLY("vddio_gmi", NULL),
85         REGULATOR_SUPPLY("pwrdet_nand", NULL),
86         REGULATOR_SUPPLY("vddio_cam", "tegra_camera"),
87         REGULATOR_SUPPLY("pwrdet_cam", NULL),
88         REGULATOR_SUPPLY("vdd_gps", NULL),
89         REGULATOR_SUPPLY("vdd_nfc", NULL),
90         REGULATOR_SUPPLY("vdd_sensor", NULL),
91         REGULATOR_SUPPLY("vdd_dtv", NULL),
92         REGULATOR_SUPPLY("vdd_bb", NULL),
93         REGULATOR_SUPPLY("vcore1_lpddr", NULL),
94         REGULATOR_SUPPLY("vcore_lpddr", NULL),
95         REGULATOR_SUPPLY("vddio_lpddr", NULL),
96         REGULATOR_SUPPLY("vdd_rf", NULL),
97         REGULATOR_SUPPLY("vdd_modem2", NULL),
98         REGULATOR_SUPPLY("vdd_dbg", NULL),
99         REGULATOR_SUPPLY("vdd_sim_1v8", NULL),
100         REGULATOR_SUPPLY("vdd_sim1a_1v8", NULL),
101         REGULATOR_SUPPLY("vdd_sim1b_1v8", NULL),
102         REGULATOR_SUPPLY("dvdd_audio", NULL),
103         REGULATOR_SUPPLY("avdd_audio", NULL),
104         REGULATOR_SUPPLY("vdd_com_1v8", NULL),
105         REGULATOR_SUPPLY("vdd_bt_1v8", NULL),
106         REGULATOR_SUPPLY("vdd_ts_1v8", NULL),
107         REGULATOR_SUPPLY("avdd_pll_bb", NULL),
108 };
109
110 static struct regulator_consumer_supply palmas_smps9_supply[] = {
111         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
112         REGULATOR_SUPPLY("vdd_sim_mmc", NULL),
113         REGULATOR_SUPPLY("vdd_sim1a_mmc", NULL),
114         REGULATOR_SUPPLY("vdd_sim1b_mmc", NULL),
115 };
116
117 static struct regulator_consumer_supply palmas_smps10_supply[] = {
118         REGULATOR_SUPPLY("unused_smps10", NULL),
119         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
120         REGULATOR_SUPPLY("vdd_vbrtr", NULL),
121         REGULATOR_SUPPLY("vdd_lcd", NULL),
122 };
123
124 static struct regulator_consumer_supply palmas_ldo1_supply[] = {
125         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
126         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
127         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
128         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegra_camera"),
129         REGULATOR_SUPPLY("avdd_pllm", NULL),
130         REGULATOR_SUPPLY("avdd_pllu", NULL),
131         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
132         REGULATOR_SUPPLY("avdd_pllx", NULL),
133         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
134         REGULATOR_SUPPLY("avdd_plle", NULL),
135 };
136
137 static struct regulator_consumer_supply palmas_ldo2_supply[] = {
138         REGULATOR_SUPPLY("avdd_lcd", NULL),
139 };
140
141 static struct regulator_consumer_supply palmas_ldo3_supply[] = {
142         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
143         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
144         REGULATOR_SUPPLY("avdd_dsi_csi", "tegra_camera"),
145         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
146         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
147         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
148         REGULATOR_SUPPLY("vddio_hsic_bb", NULL),
149         REGULATOR_SUPPLY("vddio_hsic_modem2", NULL),
150 };
151
152 static struct regulator_consumer_supply palmas_ldo4_supply[] = {
153         REGULATOR_SUPPLY("vdd_spare", NULL),
154 };
155
156 static struct regulator_consumer_supply palmas_ldo5_supply[] = {
157         REGULATOR_SUPPLY("avdd_cam1", NULL),
158 };
159
160 static struct regulator_consumer_supply palmas_ldo6_supply[] = {
161         REGULATOR_SUPPLY("vdd_temp", NULL),
162         REGULATOR_SUPPLY("vdd_mb", NULL),
163         REGULATOR_SUPPLY("avdd_ts_3v0", NULL),
164         REGULATOR_SUPPLY("avdd_backlight_3v0", "1-004d"),
165         REGULATOR_SUPPLY("vdd_nfc_3v0", NULL),
166         REGULATOR_SUPPLY("vdd_irled", NULL),
167         REGULATOR_SUPPLY("vdd_sensor_3v0", NULL),
168         REGULATOR_SUPPLY("vdd_3v0_pm", NULL),
169         REGULATOR_SUPPLY("vaux_3v3", NULL),
170         REGULATOR_SUPPLY("vdd", "0-0044"),
171         REGULATOR_SUPPLY("vdd", "0-004c"),
172 };
173
174 static struct regulator_consumer_supply palmas_ldo7_supply[] = {
175         REGULATOR_SUPPLY("vdd_af_cam1", NULL),
176 };
177 static struct regulator_consumer_supply palmas_ldo8_supply[] = {
178         REGULATOR_SUPPLY("vdd_rtc", NULL),
179 };
180 static struct regulator_consumer_supply palmas_ldo9_supply[] = {
181         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
182         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
183 };
184 static struct regulator_consumer_supply palmas_ldoln_supply[] = {
185         REGULATOR_SUPPLY("avdd_cam2", NULL),
186 };
187
188 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
189         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
190         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
191         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
192         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
193         REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
194         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
195         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
196         REGULATOR_SUPPLY("pwrdet_hv", NULL),
197         REGULATOR_SUPPLY("vdd_dtv_3v3", NULL),
198
199 };
200
201 static struct regulator_consumer_supply palmas_regen1_supply[] = {
202         REGULATOR_SUPPLY("mic_ventral", NULL),
203 };
204
205 static struct regulator_consumer_supply palmas_regen2_supply[] = {
206         REGULATOR_SUPPLY("vdd_mic", NULL),
207 };
208
209 #define PALMAS_PDATA_INIT(_name, _minmv, _maxmv, _supply_reg, _always_on, \
210         _boot_on, _apply_uv)                                            \
211         static struct regulator_init_data reg_idata_##_name = {         \
212                 .constraints = {                                        \
213                         .name = palmas_rails(_name),                    \
214                         .min_uV = (_minmv)*1000,                        \
215                         .max_uV = (_maxmv)*1000,                        \
216                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
217                                         REGULATOR_MODE_STANDBY),        \
218                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
219                                         REGULATOR_CHANGE_STATUS |       \
220                                         REGULATOR_CHANGE_VOLTAGE),      \
221                         .always_on = _always_on,                        \
222                         .boot_on = _boot_on,                            \
223                         .apply_uV = _apply_uv,                          \
224                 },                                                      \
225                 .num_consumer_supplies =                                \
226                         ARRAY_SIZE(palmas_##_name##_supply),            \
227                 .consumer_supplies = palmas_##_name##_supply,           \
228                 .supply_regulator = _supply_reg,                        \
229         }
230
231 PALMAS_PDATA_INIT(smps123, 900,  1300, NULL, 0, 0, 0);
232 PALMAS_PDATA_INIT(smps45, 900,  1400, NULL, 0, 0, 0);
233 PALMAS_PDATA_INIT(smps6, 850,  850, NULL, 0, 0, 1);
234 PALMAS_PDATA_INIT(smps7, 1200,  1200, NULL, 0, 0, 1);
235 PALMAS_PDATA_INIT(smps8, 1800,  1800, NULL, 0, 1, 1);
236 PALMAS_PDATA_INIT(smps9, 2800,  2800, NULL, 0, 0, 1);
237 PALMAS_PDATA_INIT(smps10, 5000,  5000, NULL, 0, 0, 0);
238 PALMAS_PDATA_INIT(ldo1, 1050,  1050, palmas_rails(smps7), 0, 0, 1);
239 PALMAS_PDATA_INIT(ldo2, 2800,  3000, NULL, 0, 0, 0);
240 PALMAS_PDATA_INIT(ldo3, 1200,  1200, palmas_rails(smps8), 0, 1, 1);
241 PALMAS_PDATA_INIT(ldo4, 900,  3300, NULL, 0, 0, 0);
242 PALMAS_PDATA_INIT(ldo5, 2700,  2700, NULL, 0, 0, 1);
243 PALMAS_PDATA_INIT(ldo6, 3000,  3000, NULL, 0, 0, 1);
244 PALMAS_PDATA_INIT(ldo7, 2800,  2800, NULL, 0, 0, 1);
245 PALMAS_PDATA_INIT(ldo8, 900,  900, NULL, 1, 1, 1);
246 PALMAS_PDATA_INIT(ldo9, 1800,  3300, palmas_rails(smps9), 0, 0, 1);
247 PALMAS_PDATA_INIT(ldoln, 2700, 2700, NULL, 0, 0, 1);
248 PALMAS_PDATA_INIT(ldousb, 3300,  3300, NULL, 0, 0, 1);
249 PALMAS_PDATA_INIT(regen1, 4300,  4300, NULL, 0, 0, 0);
250 PALMAS_PDATA_INIT(regen2, 4300,  4300, palmas_rails(smps8), 0, 0, 0);
251
252 #define PALMAS_REG_PDATA(_sname) &reg_idata_##_sname
253
254 static struct regulator_init_data *pluto_reg_data[PALMAS_NUM_REGS] = {
255         NULL,
256         PALMAS_REG_PDATA(smps123),
257         NULL,
258         PALMAS_REG_PDATA(smps45),
259         NULL,
260         PALMAS_REG_PDATA(smps6),
261         PALMAS_REG_PDATA(smps7),
262         PALMAS_REG_PDATA(smps8),
263         PALMAS_REG_PDATA(smps9),
264         PALMAS_REG_PDATA(smps10),
265         PALMAS_REG_PDATA(ldo1),
266         PALMAS_REG_PDATA(ldo2),
267         PALMAS_REG_PDATA(ldo3),
268         PALMAS_REG_PDATA(ldo4),
269         PALMAS_REG_PDATA(ldo5),
270         PALMAS_REG_PDATA(ldo6),
271         PALMAS_REG_PDATA(ldo7),
272         PALMAS_REG_PDATA(ldo8),
273         PALMAS_REG_PDATA(ldo9),
274         PALMAS_REG_PDATA(ldoln),
275         PALMAS_REG_PDATA(ldousb),
276         PALMAS_REG_PDATA(regen1),
277         PALMAS_REG_PDATA(regen2),
278         NULL,
279         NULL,
280         NULL,
281 };
282
283 #define PALMAS_REG_INIT(_name, _warm_reset, _roof_floor, _mode_sleep,   \
284                 _tstep, _vsel)                                          \
285         static struct palmas_reg_init reg_init_data_##_name = {         \
286                 .warm_reset = _warm_reset,                              \
287                 .roof_floor =   _roof_floor,                            \
288                 .mode_sleep = _mode_sleep,              \
289                 .tstep = _tstep,                        \
290                 .vsel = _vsel,          \
291         }
292
293 PALMAS_REG_INIT(smps12, 0, 0, 0, 0, 0);
294 PALMAS_REG_INIT(smps123, 0, PALMAS_EXT_CONTROL_ENABLE1, 0, 0, 0);
295 PALMAS_REG_INIT(smps3, 0, 0, 0, 0, 0);
296 PALMAS_REG_INIT(smps45, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
297 PALMAS_REG_INIT(smps457, 0, 0, 0, 0, 0);
298 PALMAS_REG_INIT(smps6, 0, PALMAS_EXT_CONTROL_ENABLE2, 0, 0, 0);
299 PALMAS_REG_INIT(smps7, 0, 0, 0, 0, 0);
300 PALMAS_REG_INIT(smps8, 0, 0, 0, 0, 0);
301 PALMAS_REG_INIT(smps9, 0, 0, 0, 0, 0);
302 PALMAS_REG_INIT(smps10, 0, 0, 0, 0, 0);
303 PALMAS_REG_INIT(ldo1, 0, 0, 0, 0, 0);
304 PALMAS_REG_INIT(ldo2, 0, 0, 0, 0, 0);
305 PALMAS_REG_INIT(ldo3, 0, 0, 0, 0, 0);
306 PALMAS_REG_INIT(ldo4, 0, 0, 0, 0, 0);
307 PALMAS_REG_INIT(ldo5, 0, 0, 0, 0, 0);
308 PALMAS_REG_INIT(ldo6, 0, 0, 0, 0, 0);
309 PALMAS_REG_INIT(ldo7, 0, 0, 0, 0, 0);
310 PALMAS_REG_INIT(ldo8, 0, 0, 0, 0, 0);
311 PALMAS_REG_INIT(ldo9, 0, 0, 0, 0, 0);
312 PALMAS_REG_INIT(ldoln, 0, 0, 0, 0, 0);
313 PALMAS_REG_INIT(ldousb, 0, 0, 0, 0, 0);
314
315 #define PALMAS_REG_INIT_DATA(_sname) &reg_init_data_##_sname
316 static struct palmas_reg_init *pluto_reg_init[PALMAS_NUM_REGS] = {
317         PALMAS_REG_INIT_DATA(smps12),
318         PALMAS_REG_INIT_DATA(smps123),
319         PALMAS_REG_INIT_DATA(smps3),
320         PALMAS_REG_INIT_DATA(smps45),
321         PALMAS_REG_INIT_DATA(smps457),
322         PALMAS_REG_INIT_DATA(smps6),
323         PALMAS_REG_INIT_DATA(smps7),
324         PALMAS_REG_INIT_DATA(smps8),
325         PALMAS_REG_INIT_DATA(smps9),
326         PALMAS_REG_INIT_DATA(smps10),
327         PALMAS_REG_INIT_DATA(ldo1),
328         PALMAS_REG_INIT_DATA(ldo2),
329         PALMAS_REG_INIT_DATA(ldo3),
330         PALMAS_REG_INIT_DATA(ldo4),
331         PALMAS_REG_INIT_DATA(ldo5),
332         PALMAS_REG_INIT_DATA(ldo6),
333         PALMAS_REG_INIT_DATA(ldo7),
334         PALMAS_REG_INIT_DATA(ldo8),
335         PALMAS_REG_INIT_DATA(ldo9),
336         PALMAS_REG_INIT_DATA(ldoln),
337         PALMAS_REG_INIT_DATA(ldousb),
338 };
339
340 static int ac_online(void)
341 {
342         return 1;
343 }
344
345 static struct resource pluto_pda_resources[] = {
346         [0] = {
347                 .name   = "ac",
348         },
349 };
350
351 static struct pda_power_pdata pluto_pda_data = {
352         .is_ac_online   = ac_online,
353 };
354
355 static struct platform_device pluto_pda_power_device = {
356         .name           = "pda-power",
357         .id             = -1,
358         .resource       = pluto_pda_resources,
359         .num_resources  = ARRAY_SIZE(pluto_pda_resources),
360         .dev    = {
361                 .platform_data  = &pluto_pda_data,
362         },
363 };
364
365 /* Always ON /Battery regulator */
366 static struct regulator_consumer_supply fixed_reg_en_battery_supply[] = {
367                 REGULATOR_SUPPLY("vdd_sys_cam", NULL),
368                 REGULATOR_SUPPLY("vdd_sys_bl", NULL),
369                 REGULATOR_SUPPLY("vdd_sys_com", NULL),
370                 REGULATOR_SUPPLY("vdd_sys_gps", NULL),
371                 REGULATOR_SUPPLY("vdd_sys_bt", NULL),
372 };
373
374 static struct regulator_consumer_supply fixed_reg_en_vdd_1v8_cam_supply[] = {
375         REGULATOR_SUPPLY("vddio_cam_mb", NULL),
376         REGULATOR_SUPPLY("vdd_1v8_cam12", NULL),
377 };
378
379 static struct regulator_consumer_supply fixed_reg_en_vdd_1v2_cam_supply[] = {
380         REGULATOR_SUPPLY("vdd_1v2_cam", NULL),
381 };
382
383 static struct regulator_consumer_supply fixed_reg_en_avdd_usb3_1v05_supply[] = {
384         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
385         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
386 };
387
388 static struct regulator_consumer_supply fixed_reg_en_vdd_mmc_sdmmc3_supply[] = {
389         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
390 };
391
392 static struct regulator_consumer_supply fixed_reg_en_vdd_lcd_1v8_supply[] = {
393         REGULATOR_SUPPLY("vdd_lcd_1v8_s", NULL),
394 };
395
396 static struct regulator_consumer_supply fixed_reg_en_vdd_lcd_mmc_supply[] = {
397         REGULATOR_SUPPLY("vdd_lcd_mmc_s_f", NULL),
398 };
399
400 static struct regulator_consumer_supply fixed_reg_en_vdd_1v8_mic_supply[] = {
401         REGULATOR_SUPPLY("vdd_1v8_mic", NULL),
402 };
403
404 static struct regulator_consumer_supply fixed_reg_en_vdd_hdmi_5v0_supply[] = {
405         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
406 };
407
408 static struct regulator_consumer_supply fixed_reg_en_vpp_fuse_supply[] = {
409         REGULATOR_SUPPLY("vpp_fuse", NULL),
410         REGULATOR_SUPPLY("v_efuse", NULL),
411 };
412
413 /* Macro for defining fixed regulator sub device data */
414 #define FIXED_SUPPLY(_name) "fixed_reg_en"#_name
415 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,   \
416         _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts,  \
417         _sdelay)                                                        \
418         static struct regulator_init_data ri_data_##_var =              \
419         {                                                               \
420                 .supply_regulator = _in_supply,                         \
421                 .num_consumer_supplies =                                \
422                         ARRAY_SIZE(fixed_reg_en_##_name##_supply),      \
423                 .consumer_supplies = fixed_reg_en_##_name##_supply,     \
424                 .constraints = {                                        \
425                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
426                                         REGULATOR_MODE_STANDBY),        \
427                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
428                                         REGULATOR_CHANGE_STATUS |       \
429                                         REGULATOR_CHANGE_VOLTAGE),      \
430                         .always_on = _always_on,                        \
431                         .boot_on = _boot_on,                            \
432                 },                                                      \
433         };                                                              \
434         static struct fixed_voltage_config fixed_reg_en_##_var##_pdata = \
435         {                                                               \
436                 .supply_name = FIXED_SUPPLY(_name),                     \
437                 .microvolts = _millivolts * 1000,                       \
438                 .gpio = _gpio_nr,                                       \
439                 .gpio_is_open_drain = _open_drain,                      \
440                 .enable_high = _active_high,                            \
441                 .enabled_at_boot = _boot_state,                         \
442                 .init_data = &ri_data_##_var,                           \
443                 .startup_delay = _sdelay                                \
444         };                                                              \
445         static struct platform_device fixed_reg_en_##_var##_dev = {     \
446                 .name = "reg-fixed-voltage",                            \
447                 .id = _id,                                              \
448                 .dev = {                                                \
449                         .platform_data = &fixed_reg_en_##_var##_pdata,  \
450                 },                                                      \
451         }
452
453 FIXED_REG(0,    battery,        battery,
454         NULL,   0,      0,
455         -1,     false, true,    0,      3300,   0);
456
457 FIXED_REG(1,    vdd_1v8_cam,    vdd_1v8_cam,
458         palmas_rails(smps8),    0,      0,
459         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO1,  false, true,    0,      1800,
460         0);
461
462 FIXED_REG(2,    vdd_1v2_cam,    vdd_1v2_cam,
463         palmas_rails(smps7),    0,      0,
464         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO2,  false, true,    0,      1200,
465         0);
466
467 FIXED_REG(3,    avdd_usb3_1v05, avdd_usb3_1v05,
468         palmas_rails(smps8),    0,      0,
469         TEGRA_GPIO_PK5, false,  true,   0,      1050,   0);
470
471 FIXED_REG(4,    vdd_mmc_sdmmc3, vdd_mmc_sdmmc3,
472         palmas_rails(smps9),    0,      0,
473         TEGRA_GPIO_PK1, false,  true,   0,      3300,   0);
474
475 FIXED_REG(5,    vdd_lcd_1v8,    vdd_lcd_1v8,
476         palmas_rails(smps8),    0,      0,
477         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO4,  false,  true,   0,      1800,
478         0);
479
480 FIXED_REG(6,    vdd_lcd_mmc,    vdd_lcd_mmc,
481         palmas_rails(smps9),    0,      0,
482         TEGRA_GPIO_PI4, false,  true,   0,      1800,   0);
483
484 FIXED_REG(7,    vdd_1v8_mic,    vdd_1v8_mic,
485         palmas_rails(smps8),    0,      0,
486         -1,     false,  true,   0,      1800,   0);
487
488 FIXED_REG(8,    vdd_hdmi_5v0,   vdd_hdmi_5v0,
489         NULL,   0,      0,
490         TEGRA_GPIO_PK6, true,   true,   0,      5000,   5000);
491
492 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
493 FIXED_REG(9,    vpp_fuse,       vpp_fuse,
494         palmas_rails(smps8),    0,      0,
495         TEGRA_GPIO_PX4, false,  true,   0,      1800,   0);
496 #else
497 FIXED_REG(9,    vpp_fuse,       vpp_fuse,
498         palmas_rails(smps8),    0,      0,
499         TEGRA_GPIO_PX0, false,  true,   0,      1800,   0);
500 #endif
501
502 /*
503  * Creating the fixed regulator device tables
504  */
505 #define ADD_FIXED_REG(_name)    (&fixed_reg_en_##_name##_dev)
506
507 #define E1580_COMMON_FIXED_REG                  \
508         ADD_FIXED_REG(battery),                 \
509         ADD_FIXED_REG(vdd_1v8_cam),             \
510         ADD_FIXED_REG(vdd_1v2_cam),             \
511         ADD_FIXED_REG(avdd_usb3_1v05),          \
512         ADD_FIXED_REG(vdd_mmc_sdmmc3),          \
513         ADD_FIXED_REG(vdd_lcd_1v8),             \
514         ADD_FIXED_REG(vdd_lcd_mmc),             \
515         ADD_FIXED_REG(vdd_1v8_mic),             \
516         ADD_FIXED_REG(vdd_hdmi_5v0),
517
518 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
519 #define E1580_T114_FIXED_REG                    \
520         ADD_FIXED_REG(vpp_fuse),
521 #endif
522
523 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
524 #define E1580_T30_FIXED_REG                     \
525         ADD_FIXED_REG(vpp_fuse),
526 #endif
527
528 /* Gpio switch regulator platform data for Pluto E1580 */
529 static struct platform_device *pfixed_reg_devs[] = {
530         E1580_COMMON_FIXED_REG
531 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
532         E1580_T114_FIXED_REG
533 #endif
534 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
535         E1580_T30_FIXED_REG
536 #endif
537 };
538
539 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
540 /* board parameters for cpu dfll */
541 static struct tegra_cl_dvfs_cfg_param pluto_cl_dvfs_param = {
542         .sample_rate = 12500,
543
544         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
545         .cf = 10,
546         .ci = 0,
547         .cg = 2,
548
549         .droop_cut_value = 0xF,
550         .droop_restore_ramp = 0x0,
551         .scale_out_ramp = 0x0,
552 };
553 #endif
554
555 /* palmas: fixed 10mV steps from 600mV to 1400mV, with offset 0x10 */
556 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
557 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
558 static inline void fill_reg_map(void)
559 {
560         int i;
561         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
562                 pmu_cpu_vdd_map[i].reg_value = i + 0x10;
563                 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
564         }
565 }
566
567 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
568 static struct tegra_cl_dvfs_platform_data pluto_cl_dvfs_data = {
569         .dfll_clk_name = "dfll_cpu",
570         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
571         .u.pmu_i2c = {
572                 .fs_rate = 400000,
573                 .slave_addr = 0xb0,
574                 .reg = 0x23,
575         },
576         .vdd_map = pmu_cpu_vdd_map,
577         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
578
579         .cfg_param = &pluto_cl_dvfs_param,
580 };
581
582 static int __init pluto_cl_dvfs_init(void)
583 {
584         fill_reg_map();
585         tegra_cl_dvfs_device.dev.platform_data = &pluto_cl_dvfs_data;
586         platform_device_register(&tegra_cl_dvfs_device);
587
588         return 0;
589 }
590 #endif
591
592 static struct palmas_pmic_platform_data pmic_platform = {
593         .enable_ldo8_tracking = true,
594         .disabe_ldo8_tracking_suspend = true,
595 };
596
597 struct palmas_clk32k_init_data palmas_clk32k_idata[] = {
598         {
599                 .clk32k_id = PALMAS_CLOCK32KG,
600                 .enable = true,
601         }, {
602                 .clk32k_id = PALMAS_CLOCK32KG_AUDIO,
603                 .enable = true,
604         },
605 };
606
607 static struct palmas_platform_data palmas_pdata = {
608         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
609         .irq_base = PALMAS_TEGRA_IRQ_BASE,
610         .pmic_pdata = &pmic_platform,
611         .mux_from_pdata = true,
612         .pad1 = 0,
613         .pad2 = (PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK &
614                         (1 << PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT)),
615         .clk32k_init_data =  palmas_clk32k_idata,
616         .clk32k_init_data_size = ARRAY_SIZE(palmas_clk32k_idata),
617         .irq_type = IRQ_TYPE_LEVEL_HIGH,
618 };
619
620 static struct i2c_board_info palma_device[] = {
621         {
622                 I2C_BOARD_INFO("tps65913", 0x58),
623                 .irq            = INT_EXTERNAL_PMU,
624                 .platform_data  = &palmas_pdata,
625         },
626 };
627
628 int __init pluto_regulator_init(void)
629 {
630         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
631         u32 pmc_ctrl;
632         int i;
633
634 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
635         pluto_cl_dvfs_init();
636 #endif
637
638         /* TPS65913: Normal state of INT request line is LOW.
639          * configure the power management controller to trigger PMU
640          * interrupts when HIGH.
641          */
642         pmc_ctrl = readl(pmc + PMC_CTRL);
643         writel(pmc_ctrl & ~PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
644
645         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
646                 pmic_platform.reg_data[i] = pluto_reg_data[i];
647                 pmic_platform.reg_init[i] = pluto_reg_init[i];
648         }
649
650         platform_device_register(&pluto_pda_power_device);
651         i2c_register_board_info(4, palma_device,
652                         ARRAY_SIZE(palma_device));
653         return 0;
654 }
655
656 static int __init pluto_fixed_regulator_init(void)
657 {
658         if (!machine_is_tegra_pluto())
659                 return 0;
660
661         return platform_add_devices(pfixed_reg_devs,
662                         ARRAY_SIZE(pfixed_reg_devs));
663 }
664 subsys_initcall_sync(pluto_fixed_regulator_init);
665
666 static struct tegra_suspend_platform_data pluto_suspend_data = {
667         .cpu_timer      = 200,
668         .cpu_off_timer  = 200,
669         .suspend_mode   = TEGRA_SUSPEND_LP0,
670         .core_timer     = 0x157e,
671         .core_off_timer = 2000,
672         .corereq_high   = false,
673         .sysclkreq_high = true,
674         .min_residency_noncpu = 600,
675         .min_residency_crail = 1000,
676 };
677
678 int __init pluto_suspend_init(void)
679 {
680         tegra_init_suspend(&pluto_suspend_data);
681         return 0;
682 }
683
684 int __init pluto_edp_init(void)
685 {
686 #ifdef CONFIG_TEGRA_EDP_LIMITS
687         unsigned int regulator_mA;
688
689         regulator_mA = get_maximum_cpu_current_supported();
690         if (!regulator_mA)
691                 regulator_mA = 9000;
692
693         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
694
695         tegra_init_cpu_edp_limits(regulator_mA);
696 #endif
697         return 0;
698 }
699
700 static struct soctherm_platform_data pluto_soctherm_data = {
701         .soctherm_clk_rate = 136000000,
702         .tsensor_clk_rate = 500000,
703         .sensor_data = {
704                 [TSENSE_CPU0] = {
705                         .enable = true,
706                         .therm_a = 570,
707                         .therm_b = -744,
708                         .tall = 16300,
709                         .tiddq = 1,
710                         .ten_count = 1,
711                         .tsample = 163,
712                         .pdiv = 10,
713                 },
714                 [TSENSE_CPU1] = {
715                         .enable = true,
716                         .therm_a = 570,
717                         .therm_b = -744,
718                         .tall = 16300,
719                         .tiddq = 1,
720                         .ten_count = 1,
721                         .tsample = 163,
722                         .pdiv = 10,
723                 },
724                 [TSENSE_CPU2] = {
725                         .enable = true,
726                         .therm_a = 570,
727                         .therm_b = -744,
728                         .tall = 16300,
729                         .tiddq = 1,
730                         .ten_count = 1,
731                         .tsample = 163,
732                         .pdiv = 10,
733                 },
734                 [TSENSE_CPU3] = {
735                         .enable = true,
736                         .therm_a = 570,
737                         .therm_b = -744,
738                         .tall = 16300,
739                         .tiddq = 1,
740                         .ten_count = 1,
741                         .tsample = 163,
742                         .pdiv = 10,
743                 },
744                 [TSENSE_MEM0] = {
745                         .enable = true,
746                         .therm_a = 570,
747                         .therm_b = -744,
748                         .tall = 16300,
749                         .tiddq = 1,
750                         .ten_count = 1,
751                         .tsample = 163,
752                         .pdiv = 10,
753                 },
754                 [TSENSE_MEM1] = {
755                         .enable = true,
756                         .therm_a = 570,
757                         .therm_b = -744,
758                         .tall = 16300,
759                         .tiddq = 1,
760                         .ten_count = 1,
761                         .tsample = 163,
762                         .pdiv = 10,
763                 },
764                 [TSENSE_GPU] = {
765                         .enable = true,
766                         .therm_a = 570,
767                         .therm_b = -744,
768                         .tall = 16300,
769                         .tiddq = 1,
770                         .ten_count = 1,
771                         .tsample = 163,
772                         .pdiv = 10,
773                 },
774                 [TSENSE_PLLX] = {
775                         .enable = true,
776                         .therm_a = 570,
777                         .therm_b = -744,
778                         .tall = 16300,
779                         .tiddq = 1,
780                         .ten_count = 1,
781                         .tsample = 163,
782                         .pdiv = 10,
783                 },
784         },
785
786         .therm = {
787                 [THERM_CPU] = {
788                         .thermtrip = 90, /* in C */
789                         .hw_backstop = 37, /* in C */
790
791                         .trip_temp = 68000, /* in mC */
792                         .tc1 = 0,
793                         .tc2 = 1,
794                         .passive_delay = 2000,
795                 },
796         },
797
798         .throttle = {
799                 [THROTTLE_HEAVY] = {
800                         .priority = 1,
801                         .devs = {
802                                 [THROTTLE_DEV_CPU] = {
803                                         .enable = true,
804                                         .dividend = 1,
805                                         .divisor = 255,
806                                         .step = 0,
807                                         .duration = 65535,
808                                 },
809                         },
810                 },
811         },
812 };
813
814 static struct balanced_throttle tj_throttle = {
815         .throt_tab_size = 10,
816         .throt_tab = {
817                 {      0, 1000 },
818                 { 640000, 1000 },
819                 { 640000, 1000 },
820                 { 640000, 1000 },
821                 { 640000, 1000 },
822                 { 640000, 1000 },
823                 { 760000, 1000 },
824                 { 760000, 1050 },
825                 {1000000, 1050 },
826                 {1000000, 1100 },
827         },
828 };
829
830 static int __init pluto_soctherm_init(void)
831 {
832         pluto_soctherm_data.therm[THERM_CPU].cdev =
833                         balanced_throttle_register(&tj_throttle);
834
835         return tegra11_soctherm_init(&pluto_soctherm_data);
836 }
837 module_init(pluto_soctherm_init);