ARM: tegra: soctherm: Enable clocks
[linux-2.6.git] / arch / arm / mach-tegra / board-pluto-power.c
1 /*
2  * arch/arm/mach-tegra/board-pluto-power.c
3  *
4  * Copyright (C) 2012 NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
24 #include <linux/io.h>
25
26 #include <mach/iomap.h>
27 #include <mach/edp.h>
28 #include <mach/irqs.h>
29 #include <linux/regulator/fixed.h>
30 #include <linux/mfd/palmas.h>
31 #include <linux/regulator/machine.h>
32
33 #include <asm/mach-types.h>
34
35 #include "cpu-tegra.h"
36 #include "pm.h"
37 #include "board.h"
38 #include "board-pluto.h"
39 #include "tegra_cl_dvfs.h"
40 #include "devices.h"
41 #include "tegra11_soctherm.h"
42
43 #define PMC_CTRL                0x0
44 #define PMC_CTRL_INTR_LOW       (1 << 17)
45
46 /************************ Pluto based regulator ****************/
47 static struct regulator_consumer_supply palmas_smps123_supply[] = {
48         REGULATOR_SUPPLY("vdd_cpu", NULL),
49 };
50
51 static struct regulator_consumer_supply palmas_smps45_supply[] = {
52         REGULATOR_SUPPLY("vdd_core", NULL),
53 };
54
55 static struct regulator_consumer_supply palmas_smps6_supply[] = {
56         REGULATOR_SUPPLY("vdd_core_bb", NULL),
57 };
58
59 static struct regulator_consumer_supply palmas_smps7_supply[] = {
60         REGULATOR_SUPPLY("vddio_ddr", NULL),
61         REGULATOR_SUPPLY("vddio_lpddr3", NULL),
62         REGULATOR_SUPPLY("vcore2_lpddr3", NULL),
63         REGULATOR_SUPPLY("vcore_audio_1v2", NULL),
64 };
65
66 static struct regulator_consumer_supply palmas_smps8_supply[] = {
67         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
68         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
69         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
70         REGULATOR_SUPPLY("avdd_osc", NULL),
71         REGULATOR_SUPPLY("vddio_sys", NULL),
72         REGULATOR_SUPPLY("vddio_bb", NULL),
73         REGULATOR_SUPPLY("pwrdet_bb", NULL),
74         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
75         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
76         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
77         REGULATOR_SUPPLY("vdd_emmc", "sdhci-tegra.3"),
78         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
79         REGULATOR_SUPPLY("vddio_audio", NULL),
80         REGULATOR_SUPPLY("pwrdet_audio", NULL),
81         REGULATOR_SUPPLY("vddio_uart", NULL),
82         REGULATOR_SUPPLY("pwrdet_uart", NULL),
83         REGULATOR_SUPPLY("vddio_gmi", NULL),
84         REGULATOR_SUPPLY("pwrdet_nand", NULL),
85         REGULATOR_SUPPLY("vddio_cam", "tegra_camera"),
86         REGULATOR_SUPPLY("pwrdet_cam", NULL),
87         REGULATOR_SUPPLY("vdd_gps", NULL),
88         REGULATOR_SUPPLY("vdd_nfc", NULL),
89         REGULATOR_SUPPLY("vdd_sensor", NULL),
90         REGULATOR_SUPPLY("vdd_dtv", NULL),
91         REGULATOR_SUPPLY("vdd_bb", NULL),
92         REGULATOR_SUPPLY("vcore1_lpddr", NULL),
93         REGULATOR_SUPPLY("vcore_lpddr", NULL),
94         REGULATOR_SUPPLY("vddio_lpddr", NULL),
95         REGULATOR_SUPPLY("vdd_rf", NULL),
96         REGULATOR_SUPPLY("vdd_modem2", NULL),
97         REGULATOR_SUPPLY("vdd_dbg", NULL),
98         REGULATOR_SUPPLY("vdd_sim_1v8", NULL),
99         REGULATOR_SUPPLY("vdd_sim1a_1v8", NULL),
100         REGULATOR_SUPPLY("vdd_sim1b_1v8", NULL),
101         REGULATOR_SUPPLY("dvdd_audio", NULL),
102         REGULATOR_SUPPLY("avdd_audio", NULL),
103         REGULATOR_SUPPLY("vdd_com_1v8", NULL),
104         REGULATOR_SUPPLY("vdd_bt_1v8", NULL),
105         REGULATOR_SUPPLY("vdd_ts_1v8", NULL),
106         REGULATOR_SUPPLY("avdd_pll_bb", NULL),
107 };
108
109 static struct regulator_consumer_supply palmas_smps9_supply[] = {
110         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
111         REGULATOR_SUPPLY("vdd_sim_mmc", NULL),
112         REGULATOR_SUPPLY("vdd_sim1a_mmc", NULL),
113         REGULATOR_SUPPLY("vdd_sim1b_mmc", NULL),
114 };
115
116 static struct regulator_consumer_supply palmas_smps10_supply[] = {
117         REGULATOR_SUPPLY("unused_smps10", NULL),
118         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
119         REGULATOR_SUPPLY("vdd_vbrtr", NULL),
120         REGULATOR_SUPPLY("vdd_lcd", NULL),
121 };
122
123 static struct regulator_consumer_supply palmas_ldo1_supply[] = {
124         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
125         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
126         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
127         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegra_camera"),
128         REGULATOR_SUPPLY("avdd_pllm", NULL),
129         REGULATOR_SUPPLY("avdd_pllu", NULL),
130         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
131         REGULATOR_SUPPLY("avdd_pllx", NULL),
132         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
133         REGULATOR_SUPPLY("avdd_plle", NULL),
134 };
135
136 static struct regulator_consumer_supply palmas_ldo2_supply[] = {
137         REGULATOR_SUPPLY("avdd_lcd", NULL),
138 };
139
140 static struct regulator_consumer_supply palmas_ldo3_supply[] = {
141         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
142         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
143         REGULATOR_SUPPLY("avdd_dsi_csi", "tegra_camera"),
144         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
145         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
146         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
147         REGULATOR_SUPPLY("vddio_hsic_bb", NULL),
148         REGULATOR_SUPPLY("vddio_hsic_modem2", NULL),
149 };
150
151 static struct regulator_consumer_supply palmas_ldo4_supply[] = {
152         REGULATOR_SUPPLY("vdd_spare", NULL),
153 };
154
155 static struct regulator_consumer_supply palmas_ldo5_supply[] = {
156         REGULATOR_SUPPLY("avdd_cam1", NULL),
157 };
158
159 static struct regulator_consumer_supply palmas_ldo6_supply[] = {
160         REGULATOR_SUPPLY("vdd_temp", NULL),
161         REGULATOR_SUPPLY("vdd_mb", NULL),
162         REGULATOR_SUPPLY("avdd_ts_3v0", NULL),
163         REGULATOR_SUPPLY("vdd_nfc_3v0", NULL),
164         REGULATOR_SUPPLY("vdd_irled", NULL),
165         REGULATOR_SUPPLY("vdd_sensor_3v0", NULL),
166         REGULATOR_SUPPLY("vdd_3v0_pm", NULL),
167         REGULATOR_SUPPLY("vaux_3v3", NULL),
168         REGULATOR_SUPPLY("vdd", "0-0044"),
169         REGULATOR_SUPPLY("vdd", "0-004c"),
170 };
171
172 static struct regulator_consumer_supply palmas_ldo7_supply[] = {
173         REGULATOR_SUPPLY("vdd_af_cam1", NULL),
174 };
175 static struct regulator_consumer_supply palmas_ldo8_supply[] = {
176         REGULATOR_SUPPLY("vdd_rtc", NULL),
177 };
178 static struct regulator_consumer_supply palmas_ldo9_supply[] = {
179         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
180         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
181 };
182 static struct regulator_consumer_supply palmas_ldoln_supply[] = {
183         REGULATOR_SUPPLY("avdd_cam2", NULL),
184 };
185
186 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
187         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
188         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
189         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
190         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
191         REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
192         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
193         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
194         REGULATOR_SUPPLY("pwrdet_hv", NULL),
195         REGULATOR_SUPPLY("vdd_dtv_3v3", NULL),
196
197 };
198
199 static struct regulator_consumer_supply palmas_regen1_supply[] = {
200         REGULATOR_SUPPLY("mic_ventral", NULL),
201 };
202
203 static struct regulator_consumer_supply palmas_regen2_supply[] = {
204         REGULATOR_SUPPLY("vdd_mic", NULL),
205 };
206
207 #define PALMAS_PDATA_INIT(_name, _minmv, _maxmv, _supply_reg, _always_on, \
208         _boot_on, _apply_uv)                                            \
209         static struct regulator_init_data reg_idata_##_name = {         \
210                 .constraints = {                                        \
211                         .name = palmas_rails(_name),                    \
212                         .min_uV = (_minmv)*1000,                        \
213                         .max_uV = (_maxmv)*1000,                        \
214                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
215                                         REGULATOR_MODE_STANDBY),        \
216                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
217                                         REGULATOR_CHANGE_STATUS |       \
218                                         REGULATOR_CHANGE_VOLTAGE),      \
219                         .always_on = _always_on,                        \
220                         .boot_on = _boot_on,                            \
221                         .apply_uV = _apply_uv,                          \
222                 },                                                      \
223                 .num_consumer_supplies =                                \
224                         ARRAY_SIZE(palmas_##_name##_supply),            \
225                 .consumer_supplies = palmas_##_name##_supply,           \
226                 .supply_regulator = _supply_reg,                        \
227         }
228
229 PALMAS_PDATA_INIT(smps123, 900,  1300, NULL, 0, 0, 0);
230 PALMAS_PDATA_INIT(smps45, 900,  1400, NULL, 0, 0, 0);
231 PALMAS_PDATA_INIT(smps6, 850,  850, NULL, 0, 0, 1);
232 PALMAS_PDATA_INIT(smps7, 1200,  1200, NULL, 0, 0, 1);
233 PALMAS_PDATA_INIT(smps8, 1800,  1800, NULL, 0, 1, 1);
234 PALMAS_PDATA_INIT(smps9, 2800,  2800, NULL, 0, 0, 1);
235 PALMAS_PDATA_INIT(smps10, 5000,  5000, NULL, 0, 0, 0);
236 PALMAS_PDATA_INIT(ldo1, 1050,  1050, palmas_rails(smps7), 0, 0, 1);
237 PALMAS_PDATA_INIT(ldo2, 2800,  3000, NULL, 0, 0, 0);
238 PALMAS_PDATA_INIT(ldo3, 1200,  1200, palmas_rails(smps8), 0, 1, 1);
239 PALMAS_PDATA_INIT(ldo4, 900,  3300, NULL, 0, 0, 0);
240 PALMAS_PDATA_INIT(ldo5, 2700,  2700, NULL, 0, 0, 1);
241 PALMAS_PDATA_INIT(ldo6, 3000,  3000, NULL, 0, 0, 1);
242 PALMAS_PDATA_INIT(ldo7, 2800,  2800, NULL, 0, 0, 1);
243 PALMAS_PDATA_INIT(ldo8, 900,  900, NULL, 1, 1, 1);
244 PALMAS_PDATA_INIT(ldo9, 1800,  3300, palmas_rails(smps9), 0, 0, 1);
245 PALMAS_PDATA_INIT(ldoln, 2700, 2700, NULL, 0, 0, 1);
246 PALMAS_PDATA_INIT(ldousb, 3300,  3300, NULL, 0, 0, 1);
247 PALMAS_PDATA_INIT(regen1, 4300,  4300, NULL, 0, 0, 0);
248 PALMAS_PDATA_INIT(regen2, 4300,  4300, palmas_rails(smps8), 0, 0, 0);
249
250 #define PALMAS_REG_PDATA(_sname) &reg_idata_##_sname
251
252 static struct regulator_init_data *pluto_reg_data[PALMAS_NUM_REGS] = {
253         NULL,
254         PALMAS_REG_PDATA(smps123),
255         NULL,
256         PALMAS_REG_PDATA(smps45),
257         NULL,
258         PALMAS_REG_PDATA(smps6),
259         PALMAS_REG_PDATA(smps7),
260         PALMAS_REG_PDATA(smps8),
261         PALMAS_REG_PDATA(smps9),
262         PALMAS_REG_PDATA(smps10),
263         PALMAS_REG_PDATA(ldo1),
264         PALMAS_REG_PDATA(ldo2),
265         PALMAS_REG_PDATA(ldo3),
266         PALMAS_REG_PDATA(ldo4),
267         PALMAS_REG_PDATA(ldo5),
268         PALMAS_REG_PDATA(ldo6),
269         PALMAS_REG_PDATA(ldo7),
270         PALMAS_REG_PDATA(ldo8),
271         PALMAS_REG_PDATA(ldo9),
272         PALMAS_REG_PDATA(ldoln),
273         PALMAS_REG_PDATA(ldousb),
274         PALMAS_REG_PDATA(regen1),
275         PALMAS_REG_PDATA(regen2),
276         NULL,
277         NULL,
278         NULL,
279 };
280
281 #define PALMAS_REG_INIT(_name, _warm_reset, _roof_floor, _mode_sleep,   \
282                 _tstep, _vsel)                                          \
283         static struct palmas_reg_init reg_init_data_##_name = {         \
284                 .warm_reset = _warm_reset,                              \
285                 .roof_floor =   _roof_floor,                            \
286                 .mode_sleep = _mode_sleep,              \
287                 .tstep = _tstep,                        \
288                 .vsel = _vsel,          \
289         }
290
291 PALMAS_REG_INIT(smps12, 0, 0, 0, 0, 0);
292 PALMAS_REG_INIT(smps123, 0, PALMAS_EXT_CONTROL_ENABLE1, 0, 0, 0);
293 PALMAS_REG_INIT(smps3, 0, 0, 0, 0, 0);
294 PALMAS_REG_INIT(smps45, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
295 PALMAS_REG_INIT(smps457, 0, 0, 0, 0, 0);
296 PALMAS_REG_INIT(smps6, 0, PALMAS_EXT_CONTROL_ENABLE2, 0, 0, 0);
297 PALMAS_REG_INIT(smps7, 0, 0, 0, 0, 0);
298 PALMAS_REG_INIT(smps8, 0, 0, 0, 0, 0);
299 PALMAS_REG_INIT(smps9, 0, 0, 0, 0, 0);
300 PALMAS_REG_INIT(smps10, 0, 0, 0, 0, 0);
301 PALMAS_REG_INIT(ldo1, 0, 0, 0, 0, 0);
302 PALMAS_REG_INIT(ldo2, 0, 0, 0, 0, 0);
303 PALMAS_REG_INIT(ldo3, 0, 0, 0, 0, 0);
304 PALMAS_REG_INIT(ldo4, 0, 0, 0, 0, 0);
305 PALMAS_REG_INIT(ldo5, 0, 0, 0, 0, 0);
306 PALMAS_REG_INIT(ldo6, 0, 0, 0, 0, 0);
307 PALMAS_REG_INIT(ldo7, 0, 0, 0, 0, 0);
308 PALMAS_REG_INIT(ldo8, 0, 0, 0, 0, 0);
309 PALMAS_REG_INIT(ldo9, 0, 0, 0, 0, 0);
310 PALMAS_REG_INIT(ldoln, 0, 0, 0, 0, 0);
311 PALMAS_REG_INIT(ldousb, 0, 0, 0, 0, 0);
312
313 #define PALMAS_REG_INIT_DATA(_sname) &reg_init_data_##_sname
314 static struct palmas_reg_init *pluto_reg_init[PALMAS_NUM_REGS] = {
315         PALMAS_REG_INIT_DATA(smps12),
316         PALMAS_REG_INIT_DATA(smps123),
317         PALMAS_REG_INIT_DATA(smps3),
318         PALMAS_REG_INIT_DATA(smps45),
319         PALMAS_REG_INIT_DATA(smps457),
320         PALMAS_REG_INIT_DATA(smps6),
321         PALMAS_REG_INIT_DATA(smps7),
322         PALMAS_REG_INIT_DATA(smps8),
323         PALMAS_REG_INIT_DATA(smps9),
324         PALMAS_REG_INIT_DATA(smps10),
325         PALMAS_REG_INIT_DATA(ldo1),
326         PALMAS_REG_INIT_DATA(ldo2),
327         PALMAS_REG_INIT_DATA(ldo3),
328         PALMAS_REG_INIT_DATA(ldo4),
329         PALMAS_REG_INIT_DATA(ldo5),
330         PALMAS_REG_INIT_DATA(ldo6),
331         PALMAS_REG_INIT_DATA(ldo7),
332         PALMAS_REG_INIT_DATA(ldo8),
333         PALMAS_REG_INIT_DATA(ldo9),
334         PALMAS_REG_INIT_DATA(ldoln),
335         PALMAS_REG_INIT_DATA(ldousb),
336 };
337
338 static int ac_online(void)
339 {
340         return 1;
341 }
342
343 static struct resource pluto_pda_resources[] = {
344         [0] = {
345                 .name   = "ac",
346         },
347 };
348
349 static struct pda_power_pdata pluto_pda_data = {
350         .is_ac_online   = ac_online,
351 };
352
353 static struct platform_device pluto_pda_power_device = {
354         .name           = "pda-power",
355         .id             = -1,
356         .resource       = pluto_pda_resources,
357         .num_resources  = ARRAY_SIZE(pluto_pda_resources),
358         .dev    = {
359                 .platform_data  = &pluto_pda_data,
360         },
361 };
362
363 /* Always ON /Battery regulator */
364 static struct regulator_consumer_supply fixed_reg_en_battery_supply[] = {
365                 REGULATOR_SUPPLY("vdd_sys_cam", NULL),
366                 REGULATOR_SUPPLY("vdd_sys_bl", NULL),
367                 REGULATOR_SUPPLY("vdd_sys_com", NULL),
368                 REGULATOR_SUPPLY("vdd_sys_gps", NULL),
369                 REGULATOR_SUPPLY("vdd_sys_bt", NULL),
370 };
371
372 static struct regulator_consumer_supply fixed_reg_en_vdd_1v8_cam_supply[] = {
373         REGULATOR_SUPPLY("vddio_cam_mb", NULL),
374         REGULATOR_SUPPLY("vdd_1v8_cam12", NULL),
375 };
376
377 static struct regulator_consumer_supply fixed_reg_en_vdd_1v2_cam_supply[] = {
378         REGULATOR_SUPPLY("vdd_1v2_cam", NULL),
379 };
380
381 static struct regulator_consumer_supply fixed_reg_en_avdd_usb3_1v05_supply[] = {
382         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
383         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
384 };
385
386 static struct regulator_consumer_supply fixed_reg_en_vdd_mmc_sdmmc3_supply[] = {
387         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
388 };
389
390 static struct regulator_consumer_supply fixed_reg_en_vdd_lcd_1v8_supply[] = {
391         REGULATOR_SUPPLY("vdd_lcd_1v8_s", NULL),
392 };
393
394 static struct regulator_consumer_supply fixed_reg_en_vdd_lcd_mmc_supply[] = {
395         REGULATOR_SUPPLY("vdd_lcd_mmc_s_f", NULL),
396 };
397
398 static struct regulator_consumer_supply fixed_reg_en_vdd_1v8_mic_supply[] = {
399         REGULATOR_SUPPLY("vdd_1v8_mic", NULL),
400 };
401
402 static struct regulator_consumer_supply fixed_reg_en_vdd_hdmi_5v0_supply[] = {
403         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
404 };
405
406 static struct regulator_consumer_supply fixed_reg_en_vpp_fuse_supply[] = {
407         REGULATOR_SUPPLY("vpp_fuse", NULL),
408         REGULATOR_SUPPLY("v_efuse", NULL),
409 };
410
411 /* Macro for defining fixed regulator sub device data */
412 #define FIXED_SUPPLY(_name) "fixed_reg_en"#_name
413 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,   \
414         _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts,  \
415         _sdelay)                                                        \
416         static struct regulator_init_data ri_data_##_var =              \
417         {                                                               \
418                 .supply_regulator = _in_supply,                         \
419                 .num_consumer_supplies =                                \
420                         ARRAY_SIZE(fixed_reg_en_##_name##_supply),      \
421                 .consumer_supplies = fixed_reg_en_##_name##_supply,     \
422                 .constraints = {                                        \
423                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
424                                         REGULATOR_MODE_STANDBY),        \
425                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
426                                         REGULATOR_CHANGE_STATUS |       \
427                                         REGULATOR_CHANGE_VOLTAGE),      \
428                         .always_on = _always_on,                        \
429                         .boot_on = _boot_on,                            \
430                 },                                                      \
431         };                                                              \
432         static struct fixed_voltage_config fixed_reg_en_##_var##_pdata = \
433         {                                                               \
434                 .supply_name = FIXED_SUPPLY(_name),                     \
435                 .microvolts = _millivolts * 1000,                       \
436                 .gpio = _gpio_nr,                                       \
437                 .gpio_is_open_drain = _open_drain,                      \
438                 .enable_high = _active_high,                            \
439                 .enabled_at_boot = _boot_state,                         \
440                 .init_data = &ri_data_##_var,                           \
441                 .startup_delay = _sdelay                                \
442         };                                                              \
443         static struct platform_device fixed_reg_en_##_var##_dev = {     \
444                 .name = "reg-fixed-voltage",                            \
445                 .id = _id,                                              \
446                 .dev = {                                                \
447                         .platform_data = &fixed_reg_en_##_var##_pdata,  \
448                 },                                                      \
449         }
450
451 FIXED_REG(0,    battery,        battery,
452         NULL,   0,      0,
453         -1,     false, true,    0,      3300,   0);
454
455 FIXED_REG(1,    vdd_1v8_cam,    vdd_1v8_cam,
456         palmas_rails(smps8),    0,      0,
457         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO1,  false, true,    0,      1800,
458         0);
459
460 FIXED_REG(2,    vdd_1v2_cam,    vdd_1v2_cam,
461         palmas_rails(smps7),    0,      0,
462         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO2,  false, true,    0,      1200,
463         0);
464
465 FIXED_REG(3,    avdd_usb3_1v05, avdd_usb3_1v05,
466         palmas_rails(smps8),    0,      0,
467         TEGRA_GPIO_PK5, false,  true,   0,      1050,   0);
468
469 FIXED_REG(4,    vdd_mmc_sdmmc3, vdd_mmc_sdmmc3,
470         palmas_rails(smps9),    0,      0,
471         TEGRA_GPIO_PK1, false,  true,   0,      3300,   0);
472
473 FIXED_REG(5,    vdd_lcd_1v8,    vdd_lcd_1v8,
474         palmas_rails(smps8),    0,      0,
475         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO4,  false,  true,   0,      1800,
476         0);
477
478 FIXED_REG(6,    vdd_lcd_mmc,    vdd_lcd_mmc,
479         palmas_rails(smps9),    0,      0,
480         TEGRA_GPIO_PI4, false,  true,   0,      1800,   0);
481
482 FIXED_REG(7,    vdd_1v8_mic,    vdd_1v8_mic,
483         palmas_rails(smps8),    0,      0,
484         -1,     false,  true,   0,      1800,   0);
485
486 FIXED_REG(8,    vdd_hdmi_5v0,   vdd_hdmi_5v0,
487         NULL,   0,      0,
488         TEGRA_GPIO_PK6, true,   true,   0,      5000,   5000);
489
490 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
491 FIXED_REG(9,    vpp_fuse,       vpp_fuse,
492         palmas_rails(smps8),    0,      0,
493         TEGRA_GPIO_PX4, false,  true,   0,      1800,   0);
494 #else
495 FIXED_REG(9,    vpp_fuse,       vpp_fuse,
496         palmas_rails(smps8),    0,      0,
497         TEGRA_GPIO_PX0, false,  true,   0,      1800,   0);
498 #endif
499
500 /*
501  * Creating the fixed regulator device tables
502  */
503 #define ADD_FIXED_REG(_name)    (&fixed_reg_en_##_name##_dev)
504
505 #define E1580_COMMON_FIXED_REG                  \
506         ADD_FIXED_REG(battery),                 \
507         ADD_FIXED_REG(vdd_1v8_cam),             \
508         ADD_FIXED_REG(vdd_1v2_cam),             \
509         ADD_FIXED_REG(avdd_usb3_1v05),          \
510         ADD_FIXED_REG(vdd_mmc_sdmmc3),          \
511         ADD_FIXED_REG(vdd_lcd_1v8),             \
512         ADD_FIXED_REG(vdd_lcd_mmc),             \
513         ADD_FIXED_REG(vdd_1v8_mic),             \
514         ADD_FIXED_REG(vdd_hdmi_5v0),
515
516 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
517 #define E1580_T114_FIXED_REG                    \
518         ADD_FIXED_REG(vpp_fuse),
519 #endif
520
521 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
522 #define E1580_T30_FIXED_REG                     \
523         ADD_FIXED_REG(vpp_fuse),
524 #endif
525
526 /* Gpio switch regulator platform data for Pluto E1580 */
527 static struct platform_device *pfixed_reg_devs[] = {
528         E1580_COMMON_FIXED_REG
529 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
530         E1580_T114_FIXED_REG
531 #endif
532 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
533         E1580_T30_FIXED_REG
534 #endif
535 };
536
537 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
538 /* board parameters for cpu dfll */
539 static struct tegra_cl_dvfs_cfg_param pluto_cl_dvfs_param = {
540         .sample_rate = 12500,
541
542         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
543         .cf = 10,
544         .ci = 0,
545         .cg = 2,
546
547         .droop_cut_value = 0xF,
548         .droop_restore_ramp = 0x0,
549         .scale_out_ramp = 0x0,
550 };
551 #endif
552
553 /* palmas: fixed 10mV steps from 600mV to 1400mV, with offset 0x10 */
554 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
555 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
556 static inline void fill_reg_map(void)
557 {
558         int i;
559         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
560                 pmu_cpu_vdd_map[i].reg_value = i + 0x10;
561                 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
562         }
563 }
564
565 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
566 static struct tegra_cl_dvfs_platform_data pluto_cl_dvfs_data = {
567         .dfll_clk_name = "dfll_cpu",
568         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
569         .u.pmu_i2c = {
570                 .fs_rate = 400000,
571                 .slave_addr = 0xb0,
572                 .reg = 0x23,
573         },
574         .vdd_map = pmu_cpu_vdd_map,
575         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
576
577         .cfg_param = &pluto_cl_dvfs_param,
578 };
579
580 static int __init pluto_cl_dvfs_init(void)
581 {
582         fill_reg_map();
583         tegra_cl_dvfs_device.dev.platform_data = &pluto_cl_dvfs_data;
584         platform_device_register(&tegra_cl_dvfs_device);
585
586         return 0;
587 }
588 #endif
589
590 static struct palmas_pmic_platform_data pmic_platform = {
591         .enable_ldo8_tracking = true,
592         .disabe_ldo8_tracking_suspend = true,
593 };
594
595 struct palmas_clk32k_init_data palmas_clk32k_idata[] = {
596         {
597                 .clk32k_id = PALMAS_CLOCK32KG,
598                 .enable = true,
599         }, {
600                 .clk32k_id = PALMAS_CLOCK32KG_AUDIO,
601                 .enable = true,
602         },
603 };
604
605 static struct palmas_platform_data palmas_pdata = {
606         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
607         .irq_base = PALMAS_TEGRA_IRQ_BASE,
608         .pmic_pdata = &pmic_platform,
609         .mux_from_pdata = true,
610         .pad1 = 0,
611         .pad2 = (PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK &
612                         (1 << PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT)),
613         .clk32k_init_data =  palmas_clk32k_idata,
614         .clk32k_init_data_size = ARRAY_SIZE(palmas_clk32k_idata),
615 };
616
617 static struct i2c_board_info palma_device[] = {
618         {
619                 I2C_BOARD_INFO("tps65913", 0x58),
620                 .irq            = INT_EXTERNAL_PMU,
621                 .platform_data  = &palmas_pdata,
622         },
623 };
624
625 int __init pluto_regulator_init(void)
626 {
627         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
628         u32 pmc_ctrl;
629         int i;
630
631 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
632         pluto_cl_dvfs_init();
633 #endif
634
635         /* TPS65913: Normal state of INT request line is LOW.
636          * configure the power management controller to trigger PMU
637          * interrupts when HIGH.
638          */
639         pmc_ctrl = readl(pmc + PMC_CTRL);
640         writel(pmc_ctrl & ~PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
641
642         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
643                 pmic_platform.reg_data[i] = pluto_reg_data[i];
644                 pmic_platform.reg_init[i] = pluto_reg_init[i];
645         }
646
647         platform_device_register(&pluto_pda_power_device);
648         i2c_register_board_info(4, palma_device,
649                         ARRAY_SIZE(palma_device));
650         return 0;
651 }
652
653 static int __init pluto_fixed_regulator_init(void)
654 {
655         if (!machine_is_tegra_pluto())
656                 return 0;
657
658         return platform_add_devices(pfixed_reg_devs,
659                         ARRAY_SIZE(pfixed_reg_devs));
660 }
661 subsys_initcall_sync(pluto_fixed_regulator_init);
662
663 static struct tegra_suspend_platform_data pluto_suspend_data = {
664         .cpu_timer      = 2000,
665         .cpu_off_timer  = 2000,
666         .suspend_mode   = TEGRA_SUSPEND_LP0,
667         .core_timer     = 0x157e,
668         .core_off_timer = 2000,
669         .corereq_high   = false,
670         .sysclkreq_high = true,
671         .min_residency_noncpu = 600,
672         .min_residency_crail = 1000,
673 };
674
675 int __init pluto_suspend_init(void)
676 {
677         tegra_init_suspend(&pluto_suspend_data);
678         return 0;
679 }
680
681 int __init pluto_edp_init(void)
682 {
683 #ifdef CONFIG_TEGRA_EDP_LIMITS
684         unsigned int regulator_mA;
685
686         regulator_mA = get_maximum_cpu_current_supported();
687         if (!regulator_mA)
688                 regulator_mA = 9000;
689
690         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
691
692         tegra_init_cpu_edp_limits(regulator_mA);
693 #endif
694         return 0;
695 }
696
697 static struct soctherm_platform_data pluto_soctherm_data = {
698         .soctherm_clk_rate = 136000000,
699         .tsensor_clk_rate = 500000,
700         .sensor_data = {
701                 [TSENSE_CPU0] = {
702                         .enable = true,
703                         .therm_a = 570,
704                         .therm_b = -744,
705                         .tall = 16300,
706                         .tiddq = 1,
707                         .ten_count = 1,
708                         .tsample = 163,
709                         .pdiv = 10,
710                 },
711                 [TSENSE_CPU1] = {
712                         .enable = true,
713                         .therm_a = 570,
714                         .therm_b = -744,
715                         .tall = 16300,
716                         .tiddq = 1,
717                         .ten_count = 1,
718                         .tsample = 163,
719                         .pdiv = 10,
720                 },
721                 [TSENSE_CPU2] = {
722                         .enable = true,
723                         .therm_a = 570,
724                         .therm_b = -744,
725                         .tall = 16300,
726                         .tiddq = 1,
727                         .ten_count = 1,
728                         .tsample = 163,
729                         .pdiv = 10,
730                 },
731                 [TSENSE_CPU3] = {
732                         .enable = true,
733                         .therm_a = 570,
734                         .therm_b = -744,
735                         .tall = 16300,
736                         .tiddq = 1,
737                         .ten_count = 1,
738                         .tsample = 163,
739                         .pdiv = 10,
740                 },
741                 [TSENSE_MEM0] = {
742                         .enable = true,
743                         .therm_a = 570,
744                         .therm_b = -744,
745                         .tall = 16300,
746                         .tiddq = 1,
747                         .ten_count = 1,
748                         .tsample = 163,
749                         .pdiv = 10,
750                 },
751                 [TSENSE_MEM1] = {
752                         .enable = true,
753                         .therm_a = 570,
754                         .therm_b = -744,
755                         .tall = 16300,
756                         .tiddq = 1,
757                         .ten_count = 1,
758                         .tsample = 163,
759                         .pdiv = 10,
760                 },
761                 [TSENSE_GPU] = {
762                         .enable = true,
763                         .therm_a = 570,
764                         .therm_b = -744,
765                         .tall = 16300,
766                         .tiddq = 1,
767                         .ten_count = 1,
768                         .tsample = 163,
769                         .pdiv = 10,
770                 },
771                 [TSENSE_PLLX] = {
772                         .enable = true,
773                         .therm_a = 570,
774                         .therm_b = -744,
775                         .tall = 16300,
776                         .tiddq = 1,
777                         .ten_count = 1,
778                         .tsample = 163,
779                         .pdiv = 10,
780                 },
781         },
782
783         .therm = {
784                 [THERM_CPU] = {
785                         .thermtrip = 90, /* in C */
786                         .hw_backstop = 37, /* in C */
787
788                         .trip_temp = 68000, /* in mC */
789                         .tc1 = 0,
790                         .tc2 = 1,
791                         .passive_delay = 2000,
792                 },
793         },
794
795         .throttle = {
796                 [THROTTLE_HEAVY] = {
797                         .priority = 1,
798                         .devs = {
799                                 [THROTTLE_DEV_CPU] = {
800                                         .enable = true,
801                                         .dividend = 1,
802                                         .divisor = 255,
803                                         .step = 0,
804                                         .duration = 65535,
805                                 },
806                         },
807                 },
808         },
809 };
810
811 static struct balanced_throttle tj_throttle = {
812         .throt_tab_size = 10,
813         .throt_tab = {
814                 {      0, 1000 },
815                 { 640000, 1000 },
816                 { 640000, 1000 },
817                 { 640000, 1000 },
818                 { 640000, 1000 },
819                 { 640000, 1000 },
820                 { 760000, 1000 },
821                 { 760000, 1050 },
822                 {1000000, 1050 },
823                 {1000000, 1100 },
824         },
825 };
826
827 static int __init pluto_soctherm_init(void)
828 {
829         pluto_soctherm_data.therm[THERM_CPU].cdev =
830                         balanced_throttle_register(&tj_throttle);
831
832         return tegra11_soctherm_init(&pluto_soctherm_data);
833 }
834 module_init(pluto_soctherm_init);