ARM: tegra: soctherm: Enable THERMTRIP
[linux-2.6.git] / arch / arm / mach-tegra / board-pluto-power.c
1 /*
2  * arch/arm/mach-tegra/board-pluto-power.c
3  *
4  * Copyright (C) 2012 NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
24 #include <linux/io.h>
25
26 #include <mach/iomap.h>
27 #include <mach/edp.h>
28 #include <mach/irqs.h>
29 #include <linux/regulator/fixed.h>
30 #include <linux/mfd/palmas.h>
31 #include <linux/regulator/machine.h>
32
33 #include <asm/mach-types.h>
34
35 #include "pm.h"
36 #include "board.h"
37 #include "board-pluto.h"
38 #include "tegra_cl_dvfs.h"
39 #include "devices.h"
40 #include "tegra11_soctherm.h"
41
42 #define PMC_CTRL                0x0
43 #define PMC_CTRL_INTR_LOW       (1 << 17)
44
45 /************************ Pluto based regulator ****************/
46 static struct regulator_consumer_supply palmas_smps123_supply[] = {
47         REGULATOR_SUPPLY("vdd_cpu", NULL),
48 };
49
50 static struct regulator_consumer_supply palmas_smps45_supply[] = {
51         REGULATOR_SUPPLY("vdd_core", NULL),
52 };
53
54 static struct regulator_consumer_supply palmas_smps6_supply[] = {
55         REGULATOR_SUPPLY("vdd_core_bb", NULL),
56 };
57
58 static struct regulator_consumer_supply palmas_smps7_supply[] = {
59         REGULATOR_SUPPLY("vddio_ddr", NULL),
60         REGULATOR_SUPPLY("vddio_lpddr3", NULL),
61         REGULATOR_SUPPLY("vcore2_lpddr3", NULL),
62         REGULATOR_SUPPLY("vcore_audio_1v2", NULL),
63 };
64
65 static struct regulator_consumer_supply palmas_smps8_supply[] = {
66         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
67         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
68         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
69         REGULATOR_SUPPLY("avdd_osc", NULL),
70         REGULATOR_SUPPLY("vddio_sys", NULL),
71         REGULATOR_SUPPLY("vddio_bb", NULL),
72         REGULATOR_SUPPLY("pwrdet_bb", NULL),
73         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
74         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
75         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
76         REGULATOR_SUPPLY("vdd_emmc", "sdhci-tegra.3"),
77         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
78         REGULATOR_SUPPLY("vddio_audio", NULL),
79         REGULATOR_SUPPLY("pwrdet_audio", NULL),
80         REGULATOR_SUPPLY("vddio_uart", NULL),
81         REGULATOR_SUPPLY("pwrdet_uart", NULL),
82         REGULATOR_SUPPLY("vddio_gmi", NULL),
83         REGULATOR_SUPPLY("pwrdet_nand", NULL),
84         REGULATOR_SUPPLY("vddio_cam", "tegra_camera"),
85         REGULATOR_SUPPLY("pwrdet_cam", NULL),
86         REGULATOR_SUPPLY("vdd_gps", NULL),
87         REGULATOR_SUPPLY("vdd_nfc", NULL),
88         REGULATOR_SUPPLY("vdd_sensor", NULL),
89         REGULATOR_SUPPLY("vdd_dtv", NULL),
90         REGULATOR_SUPPLY("vdd_bb", NULL),
91         REGULATOR_SUPPLY("vcore1_lpddr", NULL),
92         REGULATOR_SUPPLY("vcore_lpddr", NULL),
93         REGULATOR_SUPPLY("vddio_lpddr", NULL),
94         REGULATOR_SUPPLY("vdd_rf", NULL),
95         REGULATOR_SUPPLY("vdd_modem2", NULL),
96         REGULATOR_SUPPLY("vdd_dbg", NULL),
97         REGULATOR_SUPPLY("vdd_sim_1v8", NULL),
98         REGULATOR_SUPPLY("vdd_sim1a_1v8", NULL),
99         REGULATOR_SUPPLY("vdd_sim1b_1v8", NULL),
100         REGULATOR_SUPPLY("dvdd_audio", NULL),
101         REGULATOR_SUPPLY("avdd_audio", NULL),
102         REGULATOR_SUPPLY("vdd_com_1v8", NULL),
103         REGULATOR_SUPPLY("vdd_bt_1v8", NULL),
104         REGULATOR_SUPPLY("vdd_ts_1v8", NULL),
105         REGULATOR_SUPPLY("avdd_pll_bb", NULL),
106 };
107
108 static struct regulator_consumer_supply palmas_smps9_supply[] = {
109         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
110         REGULATOR_SUPPLY("vdd_sim_mmc", NULL),
111         REGULATOR_SUPPLY("vdd_sim1a_mmc", NULL),
112         REGULATOR_SUPPLY("vdd_sim1b_mmc", NULL),
113 };
114
115 static struct regulator_consumer_supply palmas_smps10_supply[] = {
116         REGULATOR_SUPPLY("unused_smps10", NULL),
117         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
118         REGULATOR_SUPPLY("vdd_vbrtr", NULL),
119         REGULATOR_SUPPLY("vdd_lcd", NULL),
120 };
121
122 static struct regulator_consumer_supply palmas_ldo1_supply[] = {
123         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
124         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
125         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
126         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegra_camera"),
127         REGULATOR_SUPPLY("avdd_pllm", NULL),
128         REGULATOR_SUPPLY("avdd_pllu", NULL),
129         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
130         REGULATOR_SUPPLY("avdd_pllx", NULL),
131         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
132         REGULATOR_SUPPLY("avdd_plle", NULL),
133 };
134
135 static struct regulator_consumer_supply palmas_ldo2_supply[] = {
136         REGULATOR_SUPPLY("avdd_lcd", NULL),
137 };
138
139 static struct regulator_consumer_supply palmas_ldo3_supply[] = {
140         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
141         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
142         REGULATOR_SUPPLY("avdd_dsi_csi", "tegra_camera"),
143         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
144         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
145         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
146         REGULATOR_SUPPLY("vddio_hsic_bb", NULL),
147         REGULATOR_SUPPLY("vddio_hsic_modem2", NULL),
148 };
149
150 static struct regulator_consumer_supply palmas_ldo4_supply[] = {
151         REGULATOR_SUPPLY("vdd_spare", NULL),
152 };
153
154 static struct regulator_consumer_supply palmas_ldo5_supply[] = {
155         REGULATOR_SUPPLY("avdd_cam1", NULL),
156 };
157
158 static struct regulator_consumer_supply palmas_ldo6_supply[] = {
159         REGULATOR_SUPPLY("vdd_temp", NULL),
160         REGULATOR_SUPPLY("vdd_mb", NULL),
161         REGULATOR_SUPPLY("avdd_ts_3v0", NULL),
162         REGULATOR_SUPPLY("vdd_nfc_3v0", NULL),
163         REGULATOR_SUPPLY("vdd_irled", NULL),
164         REGULATOR_SUPPLY("vdd_sensor_3v0", NULL),
165         REGULATOR_SUPPLY("vdd_3v0_pm", NULL),
166         REGULATOR_SUPPLY("vaux_3v3", NULL),
167         REGULATOR_SUPPLY("vdd", "0-0044"),
168         REGULATOR_SUPPLY("vdd", "0-004c"),
169 };
170
171 static struct regulator_consumer_supply palmas_ldo7_supply[] = {
172         REGULATOR_SUPPLY("vdd_af_cam1", NULL),
173 };
174 static struct regulator_consumer_supply palmas_ldo8_supply[] = {
175         REGULATOR_SUPPLY("vdd_rtc", NULL),
176 };
177 static struct regulator_consumer_supply palmas_ldo9_supply[] = {
178         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
179         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
180 };
181 static struct regulator_consumer_supply palmas_ldoln_supply[] = {
182         REGULATOR_SUPPLY("avdd_cam2", NULL),
183 };
184
185 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
186         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
187         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
188         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
189         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
190         REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
191         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
192         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
193         REGULATOR_SUPPLY("pwrdet_hv", NULL),
194         REGULATOR_SUPPLY("vdd_dtv_3v3", NULL),
195
196 };
197
198 static struct regulator_consumer_supply palmas_regen1_supply[] = {
199         REGULATOR_SUPPLY("mic_ventral", NULL),
200 };
201
202 static struct regulator_consumer_supply palmas_regen2_supply[] = {
203         REGULATOR_SUPPLY("vdd_mic", NULL),
204 };
205
206 #define PALMAS_PDATA_INIT(_name, _minmv, _maxmv, _supply_reg, _always_on, \
207         _boot_on, _apply_uv)                                            \
208         static struct regulator_init_data reg_idata_##_name = {         \
209                 .constraints = {                                        \
210                         .name = palmas_rails(_name),                    \
211                         .min_uV = (_minmv)*1000,                        \
212                         .max_uV = (_maxmv)*1000,                        \
213                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
214                                         REGULATOR_MODE_STANDBY),        \
215                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
216                                         REGULATOR_CHANGE_STATUS |       \
217                                         REGULATOR_CHANGE_VOLTAGE),      \
218                         .always_on = _always_on,                        \
219                         .boot_on = _boot_on,                            \
220                         .apply_uV = _apply_uv,                          \
221                 },                                                      \
222                 .num_consumer_supplies =                                \
223                         ARRAY_SIZE(palmas_##_name##_supply),            \
224                 .consumer_supplies = palmas_##_name##_supply,           \
225                 .supply_regulator = _supply_reg,                        \
226         }
227
228 PALMAS_PDATA_INIT(smps123, 900,  1300, NULL, 0, 0, 0);
229 PALMAS_PDATA_INIT(smps45, 900,  1400, NULL, 0, 0, 0);
230 PALMAS_PDATA_INIT(smps6, 850,  850, NULL, 0, 0, 1);
231 PALMAS_PDATA_INIT(smps7, 1200,  1200, NULL, 0, 0, 1);
232 PALMAS_PDATA_INIT(smps8, 1800,  1800, NULL, 0, 1, 1);
233 PALMAS_PDATA_INIT(smps9, 2800,  2800, NULL, 0, 0, 1);
234 PALMAS_PDATA_INIT(smps10, 5000,  5000, NULL, 0, 0, 0);
235 PALMAS_PDATA_INIT(ldo1, 1050,  1050, palmas_rails(smps7), 0, 0, 1);
236 PALMAS_PDATA_INIT(ldo2, 2800,  3000, NULL, 0, 0, 0);
237 PALMAS_PDATA_INIT(ldo3, 1200,  1200, palmas_rails(smps8), 0, 1, 1);
238 PALMAS_PDATA_INIT(ldo4, 900,  3300, NULL, 0, 0, 0);
239 PALMAS_PDATA_INIT(ldo5, 2700,  2700, NULL, 0, 0, 1);
240 PALMAS_PDATA_INIT(ldo6, 3000,  3000, NULL, 0, 0, 1);
241 PALMAS_PDATA_INIT(ldo7, 2800,  2800, NULL, 0, 0, 1);
242 PALMAS_PDATA_INIT(ldo8, 900,  900, NULL, 1, 1, 1);
243 PALMAS_PDATA_INIT(ldo9, 1800,  3300, palmas_rails(smps9), 0, 0, 1);
244 PALMAS_PDATA_INIT(ldoln, 2700, 2700, NULL, 0, 0, 1);
245 PALMAS_PDATA_INIT(ldousb, 3300,  3300, NULL, 0, 0, 1);
246 PALMAS_PDATA_INIT(regen1, 4300,  4300, NULL, 0, 0, 0);
247 PALMAS_PDATA_INIT(regen2, 4300,  4300, palmas_rails(smps8), 0, 0, 0);
248
249 #define PALMAS_REG_PDATA(_sname) &reg_idata_##_sname
250
251 static struct regulator_init_data *pluto_reg_data[PALMAS_NUM_REGS] = {
252         NULL,
253         PALMAS_REG_PDATA(smps123),
254         NULL,
255         PALMAS_REG_PDATA(smps45),
256         NULL,
257         PALMAS_REG_PDATA(smps6),
258         PALMAS_REG_PDATA(smps7),
259         PALMAS_REG_PDATA(smps8),
260         PALMAS_REG_PDATA(smps9),
261         PALMAS_REG_PDATA(smps10),
262         PALMAS_REG_PDATA(ldo1),
263         PALMAS_REG_PDATA(ldo2),
264         PALMAS_REG_PDATA(ldo3),
265         PALMAS_REG_PDATA(ldo4),
266         PALMAS_REG_PDATA(ldo5),
267         PALMAS_REG_PDATA(ldo6),
268         PALMAS_REG_PDATA(ldo7),
269         PALMAS_REG_PDATA(ldo8),
270         PALMAS_REG_PDATA(ldo9),
271         PALMAS_REG_PDATA(ldoln),
272         PALMAS_REG_PDATA(ldousb),
273         PALMAS_REG_PDATA(regen1),
274         PALMAS_REG_PDATA(regen2),
275         NULL,
276         NULL,
277         NULL,
278 };
279
280 #define PALMAS_REG_INIT(_name, _warm_reset, _roof_floor, _mode_sleep,   \
281                 _tstep, _vsel)                                          \
282         static struct palmas_reg_init reg_init_data_##_name = {         \
283                 .warm_reset = _warm_reset,                              \
284                 .roof_floor =   _roof_floor,                            \
285                 .mode_sleep = _mode_sleep,              \
286                 .tstep = _tstep,                        \
287                 .vsel = _vsel,          \
288         }
289
290 PALMAS_REG_INIT(smps12, 0, 0, 0, 0, 0);
291 PALMAS_REG_INIT(smps123, 0, PALMAS_EXT_CONTROL_ENABLE1, 0, 0, 0);
292 PALMAS_REG_INIT(smps3, 0, 0, 0, 0, 0);
293 PALMAS_REG_INIT(smps45, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
294 PALMAS_REG_INIT(smps457, 0, 0, 0, 0, 0);
295 PALMAS_REG_INIT(smps6, 0, PALMAS_EXT_CONTROL_ENABLE2, 0, 0, 0);
296 PALMAS_REG_INIT(smps7, 0, 0, 0, 0, 0);
297 PALMAS_REG_INIT(smps8, 0, 0, 0, 0, 0);
298 PALMAS_REG_INIT(smps9, 0, 0, 0, 0, 0);
299 PALMAS_REG_INIT(smps10, 0, 0, 0, 0, 0);
300 PALMAS_REG_INIT(ldo1, 0, 0, 0, 0, 0);
301 PALMAS_REG_INIT(ldo2, 0, 0, 0, 0, 0);
302 PALMAS_REG_INIT(ldo3, 0, 0, 0, 0, 0);
303 PALMAS_REG_INIT(ldo4, 0, 0, 0, 0, 0);
304 PALMAS_REG_INIT(ldo5, 0, 0, 0, 0, 0);
305 PALMAS_REG_INIT(ldo6, 0, 0, 0, 0, 0);
306 PALMAS_REG_INIT(ldo7, 0, 0, 0, 0, 0);
307 PALMAS_REG_INIT(ldo8, 0, 0, 0, 0, 0);
308 PALMAS_REG_INIT(ldo9, 0, 0, 0, 0, 0);
309 PALMAS_REG_INIT(ldoln, 0, 0, 0, 0, 0);
310 PALMAS_REG_INIT(ldousb, 0, 0, 0, 0, 0);
311
312 #define PALMAS_REG_INIT_DATA(_sname) &reg_init_data_##_sname
313 static struct palmas_reg_init *pluto_reg_init[PALMAS_NUM_REGS] = {
314         PALMAS_REG_INIT_DATA(smps12),
315         PALMAS_REG_INIT_DATA(smps123),
316         PALMAS_REG_INIT_DATA(smps3),
317         PALMAS_REG_INIT_DATA(smps45),
318         PALMAS_REG_INIT_DATA(smps457),
319         PALMAS_REG_INIT_DATA(smps6),
320         PALMAS_REG_INIT_DATA(smps7),
321         PALMAS_REG_INIT_DATA(smps8),
322         PALMAS_REG_INIT_DATA(smps9),
323         PALMAS_REG_INIT_DATA(smps10),
324         PALMAS_REG_INIT_DATA(ldo1),
325         PALMAS_REG_INIT_DATA(ldo2),
326         PALMAS_REG_INIT_DATA(ldo3),
327         PALMAS_REG_INIT_DATA(ldo4),
328         PALMAS_REG_INIT_DATA(ldo5),
329         PALMAS_REG_INIT_DATA(ldo6),
330         PALMAS_REG_INIT_DATA(ldo7),
331         PALMAS_REG_INIT_DATA(ldo8),
332         PALMAS_REG_INIT_DATA(ldo9),
333         PALMAS_REG_INIT_DATA(ldoln),
334         PALMAS_REG_INIT_DATA(ldousb),
335 };
336
337 static int ac_online(void)
338 {
339         return 1;
340 }
341
342 static struct resource pluto_pda_resources[] = {
343         [0] = {
344                 .name   = "ac",
345         },
346 };
347
348 static struct pda_power_pdata pluto_pda_data = {
349         .is_ac_online   = ac_online,
350 };
351
352 static struct platform_device pluto_pda_power_device = {
353         .name           = "pda-power",
354         .id             = -1,
355         .resource       = pluto_pda_resources,
356         .num_resources  = ARRAY_SIZE(pluto_pda_resources),
357         .dev    = {
358                 .platform_data  = &pluto_pda_data,
359         },
360 };
361
362 /* Always ON /Battery regulator */
363 static struct regulator_consumer_supply fixed_reg_en_battery_supply[] = {
364                 REGULATOR_SUPPLY("vdd_sys_cam", NULL),
365                 REGULATOR_SUPPLY("vdd_sys_bl", NULL),
366                 REGULATOR_SUPPLY("vdd_sys_com", NULL),
367                 REGULATOR_SUPPLY("vdd_sys_gps", NULL),
368                 REGULATOR_SUPPLY("vdd_sys_bt", NULL),
369 };
370
371 static struct regulator_consumer_supply fixed_reg_en_vdd_1v8_cam_supply[] = {
372         REGULATOR_SUPPLY("vddio_cam_mb", NULL),
373         REGULATOR_SUPPLY("vdd_1v8_cam12", NULL),
374 };
375
376 static struct regulator_consumer_supply fixed_reg_en_vdd_1v2_cam_supply[] = {
377         REGULATOR_SUPPLY("vdd_1v2_cam", NULL),
378 };
379
380 static struct regulator_consumer_supply fixed_reg_en_avdd_usb3_1v05_supply[] = {
381         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
382         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
383 };
384
385 static struct regulator_consumer_supply fixed_reg_en_vdd_mmc_sdmmc3_supply[] = {
386         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
387 };
388
389 static struct regulator_consumer_supply fixed_reg_en_vdd_lcd_1v8_supply[] = {
390         REGULATOR_SUPPLY("vdd_lcd_1v8_s", NULL),
391 };
392
393 static struct regulator_consumer_supply fixed_reg_en_vdd_lcd_mmc_supply[] = {
394         REGULATOR_SUPPLY("vdd_lcd_mmc_s_f", NULL),
395 };
396
397 static struct regulator_consumer_supply fixed_reg_en_vdd_1v8_mic_supply[] = {
398         REGULATOR_SUPPLY("vdd_1v8_mic", NULL),
399 };
400
401 static struct regulator_consumer_supply fixed_reg_en_vdd_hdmi_5v0_supply[] = {
402         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
403 };
404
405 static struct regulator_consumer_supply fixed_reg_en_vpp_fuse_supply[] = {
406         REGULATOR_SUPPLY("vpp_fuse", NULL),
407         REGULATOR_SUPPLY("v_efuse", NULL),
408 };
409
410 /* Macro for defining fixed regulator sub device data */
411 #define FIXED_SUPPLY(_name) "fixed_reg_en"#_name
412 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,   \
413         _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts,  \
414         _sdelay)                                                        \
415         static struct regulator_init_data ri_data_##_var =              \
416         {                                                               \
417                 .supply_regulator = _in_supply,                         \
418                 .num_consumer_supplies =                                \
419                         ARRAY_SIZE(fixed_reg_en_##_name##_supply),      \
420                 .consumer_supplies = fixed_reg_en_##_name##_supply,     \
421                 .constraints = {                                        \
422                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
423                                         REGULATOR_MODE_STANDBY),        \
424                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
425                                         REGULATOR_CHANGE_STATUS |       \
426                                         REGULATOR_CHANGE_VOLTAGE),      \
427                         .always_on = _always_on,                        \
428                         .boot_on = _boot_on,                            \
429                 },                                                      \
430         };                                                              \
431         static struct fixed_voltage_config fixed_reg_en_##_var##_pdata = \
432         {                                                               \
433                 .supply_name = FIXED_SUPPLY(_name),                     \
434                 .microvolts = _millivolts * 1000,                       \
435                 .gpio = _gpio_nr,                                       \
436                 .gpio_is_open_drain = _open_drain,                      \
437                 .enable_high = _active_high,                            \
438                 .enabled_at_boot = _boot_state,                         \
439                 .init_data = &ri_data_##_var,                           \
440                 .startup_delay = _sdelay                                \
441         };                                                              \
442         static struct platform_device fixed_reg_en_##_var##_dev = {     \
443                 .name = "reg-fixed-voltage",                            \
444                 .id = _id,                                              \
445                 .dev = {                                                \
446                         .platform_data = &fixed_reg_en_##_var##_pdata,  \
447                 },                                                      \
448         }
449
450 FIXED_REG(0,    battery,        battery,
451         NULL,   0,      0,
452         -1,     false, true,    0,      3300,   0);
453
454 FIXED_REG(1,    vdd_1v8_cam,    vdd_1v8_cam,
455         palmas_rails(smps8),    0,      0,
456         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO1,  false, true,    0,      1800,
457         0);
458
459 FIXED_REG(2,    vdd_1v2_cam,    vdd_1v2_cam,
460         palmas_rails(smps7),    0,      0,
461         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO2,  false, true,    0,      1200,
462         0);
463
464 FIXED_REG(3,    avdd_usb3_1v05, avdd_usb3_1v05,
465         palmas_rails(smps8),    0,      0,
466         TEGRA_GPIO_PK5, false,  true,   0,      1050,   0);
467
468 FIXED_REG(4,    vdd_mmc_sdmmc3, vdd_mmc_sdmmc3,
469         palmas_rails(smps9),    0,      0,
470         TEGRA_GPIO_PK1, false,  true,   0,      3300,   0);
471
472 FIXED_REG(5,    vdd_lcd_1v8,    vdd_lcd_1v8,
473         palmas_rails(smps8),    0,      0,
474         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO4,  false,  true,   0,      1800,
475         0);
476
477 FIXED_REG(6,    vdd_lcd_mmc,    vdd_lcd_mmc,
478         palmas_rails(smps9),    0,      0,
479         TEGRA_GPIO_PI4, false,  true,   0,      1800,   0);
480
481 FIXED_REG(7,    vdd_1v8_mic,    vdd_1v8_mic,
482         palmas_rails(smps8),    0,      0,
483         -1,     false,  true,   0,      1800,   0);
484
485 FIXED_REG(8,    vdd_hdmi_5v0,   vdd_hdmi_5v0,
486         NULL,   0,      0,
487         TEGRA_GPIO_PK6, true,   true,   0,      5000,   5000);
488
489 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
490 FIXED_REG(9,    vpp_fuse,       vpp_fuse,
491         palmas_rails(smps8),    0,      0,
492         TEGRA_GPIO_PX4, false,  true,   0,      1800,   0);
493 #else
494 FIXED_REG(9,    vpp_fuse,       vpp_fuse,
495         palmas_rails(smps8),    0,      0,
496         TEGRA_GPIO_PX0, false,  true,   0,      1800,   0);
497 #endif
498
499 /*
500  * Creating the fixed regulator device tables
501  */
502 #define ADD_FIXED_REG(_name)    (&fixed_reg_en_##_name##_dev)
503
504 #define E1580_COMMON_FIXED_REG                  \
505         ADD_FIXED_REG(battery),                 \
506         ADD_FIXED_REG(vdd_1v8_cam),             \
507         ADD_FIXED_REG(vdd_1v2_cam),             \
508         ADD_FIXED_REG(avdd_usb3_1v05),          \
509         ADD_FIXED_REG(vdd_mmc_sdmmc3),          \
510         ADD_FIXED_REG(vdd_lcd_1v8),             \
511         ADD_FIXED_REG(vdd_lcd_mmc),             \
512         ADD_FIXED_REG(vdd_1v8_mic),             \
513         ADD_FIXED_REG(vdd_hdmi_5v0),
514
515 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
516 #define E1580_T114_FIXED_REG                    \
517         ADD_FIXED_REG(vpp_fuse),
518 #endif
519
520 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
521 #define E1580_T30_FIXED_REG                     \
522         ADD_FIXED_REG(vpp_fuse),
523 #endif
524
525 /* Gpio switch regulator platform data for Pluto E1580 */
526 static struct platform_device *pfixed_reg_devs[] = {
527         E1580_COMMON_FIXED_REG
528 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
529         E1580_T114_FIXED_REG
530 #endif
531 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
532         E1580_T30_FIXED_REG
533 #endif
534 };
535
536 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
537 /* board parameters for cpu dfll */
538 static struct tegra_cl_dvfs_cfg_param pluto_cl_dvfs_param = {
539         .sample_rate = 12500,
540
541         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
542         .cf = 10,
543         .ci = 0,
544         .cg = 2,
545
546         .droop_cut_value = 0xF,
547         .droop_restore_ramp = 0x0,
548         .scale_out_ramp = 0x0,
549 };
550 #endif
551
552 /* palmas: fixed 10mV steps from 600mV to 1400mV, with offset 0x10 */
553 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
554 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
555 static inline void fill_reg_map(void)
556 {
557         int i;
558         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
559                 pmu_cpu_vdd_map[i].reg_value = i + 0x10;
560                 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
561         }
562 }
563
564 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
565 static struct tegra_cl_dvfs_platform_data pluto_cl_dvfs_data = {
566         .dfll_clk_name = "dfll_cpu",
567         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
568         .u.pmu_i2c = {
569                 .fs_rate = 400000,
570                 .slave_addr = 0xb0,
571                 .reg = 0x23,
572         },
573         .vdd_map = pmu_cpu_vdd_map,
574         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
575
576         .cfg_param = &pluto_cl_dvfs_param,
577 };
578
579 static int __init pluto_cl_dvfs_init(void)
580 {
581         fill_reg_map();
582         tegra_cl_dvfs_device.dev.platform_data = &pluto_cl_dvfs_data;
583         platform_device_register(&tegra_cl_dvfs_device);
584
585         return 0;
586 }
587 #endif
588
589 static struct palmas_pmic_platform_data pmic_platform = {
590         .enable_ldo8_tracking = true,
591         .disabe_ldo8_tracking_suspend = true,
592 };
593
594 struct palmas_clk32k_init_data palmas_clk32k_idata[] = {
595         {
596                 .clk32k_id = PALMAS_CLOCK32KG,
597                 .enable = true,
598         }, {
599                 .clk32k_id = PALMAS_CLOCK32KG_AUDIO,
600                 .enable = true,
601         },
602 };
603
604 static struct palmas_platform_data palmas_pdata = {
605         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
606         .irq_base = PALMAS_TEGRA_IRQ_BASE,
607         .pmic_pdata = &pmic_platform,
608         .mux_from_pdata = true,
609         .pad1 = 0,
610         .pad2 = (PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK &
611                         (1 << PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT)),
612         .clk32k_init_data =  palmas_clk32k_idata,
613         .clk32k_init_data_size = ARRAY_SIZE(palmas_clk32k_idata),
614 };
615
616 static struct i2c_board_info palma_device[] = {
617         {
618                 I2C_BOARD_INFO("tps65913", 0x58),
619                 .irq            = INT_EXTERNAL_PMU,
620                 .platform_data  = &palmas_pdata,
621         },
622 };
623
624 int __init pluto_regulator_init(void)
625 {
626         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
627         u32 pmc_ctrl;
628         int i;
629
630 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
631         pluto_cl_dvfs_init();
632 #endif
633
634         /* TPS65913: Normal state of INT request line is LOW.
635          * configure the power management controller to trigger PMU
636          * interrupts when HIGH.
637          */
638         pmc_ctrl = readl(pmc + PMC_CTRL);
639         writel(pmc_ctrl & ~PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
640
641         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
642                 pmic_platform.reg_data[i] = pluto_reg_data[i];
643                 pmic_platform.reg_init[i] = pluto_reg_init[i];
644         }
645
646         platform_device_register(&pluto_pda_power_device);
647         i2c_register_board_info(4, palma_device,
648                         ARRAY_SIZE(palma_device));
649         return 0;
650 }
651
652 static int __init pluto_fixed_regulator_init(void)
653 {
654         if (!machine_is_tegra_pluto())
655                 return 0;
656
657         return platform_add_devices(pfixed_reg_devs,
658                         ARRAY_SIZE(pfixed_reg_devs));
659 }
660 subsys_initcall_sync(pluto_fixed_regulator_init);
661
662 static struct tegra_suspend_platform_data pluto_suspend_data = {
663         .cpu_timer      = 2000,
664         .cpu_off_timer  = 2000,
665         .suspend_mode   = TEGRA_SUSPEND_LP0,
666         .core_timer     = 0x157e,
667         .core_off_timer = 2000,
668         .corereq_high   = false,
669         .sysclkreq_high = true,
670         .min_residency_noncpu = 600,
671         .min_residency_crail = 1000,
672 };
673
674 int __init pluto_suspend_init(void)
675 {
676         tegra_init_suspend(&pluto_suspend_data);
677         return 0;
678 }
679
680 int __init pluto_edp_init(void)
681 {
682 #ifdef CONFIG_TEGRA_EDP_LIMITS
683         unsigned int regulator_mA;
684
685         regulator_mA = get_maximum_cpu_current_supported();
686         if (!regulator_mA)
687                 regulator_mA = 9000;
688
689         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
690
691         tegra_init_cpu_edp_limits(regulator_mA);
692 #endif
693         return 0;
694 }
695
696 static struct soctherm_platform_data pluto_soctherm_data = {
697         .thermtrip = {
698                 [THERM_CPU] = 90,
699                 [THERM_GPU] = 0, /* Not enabled */
700                 [THERM_MEM] = 0, /* Not enabled */
701                 [THERM_PLL] = 0, /* Not enabled */
702         },
703
704         .hw_backstop = 60,
705         .dividend = 1,
706         .divisor = 2,
707         .duration = 1,
708         .step = 1,
709         .sensor_data = {
710                 [TSENSE_CPU0] = {
711                         .enable = true,
712                         .therm_a = 570,
713                         .therm_b = -744,
714                         .tall = 16300,
715                         .tiddq = 1,
716                         .ten_count = 1,
717                         .tsample = 163,
718                         .pdiv = 10,
719                 },
720                 [TSENSE_CPU1] = {
721                         .enable = true,
722                         .therm_a = 570,
723                         .therm_b = -744,
724                         .tall = 16300,
725                         .tiddq = 1,
726                         .ten_count = 1,
727                         .tsample = 163,
728                         .pdiv = 10,
729                 },
730                 [TSENSE_CPU2] = {
731                         .enable = true,
732                         .therm_a = 570,
733                         .therm_b = -744,
734                         .tall = 16300,
735                         .tiddq = 1,
736                         .ten_count = 1,
737                         .tsample = 163,
738                         .pdiv = 10,
739                 },
740                 [TSENSE_CPU3] = {
741                         .enable = true,
742                         .therm_a = 570,
743                         .therm_b = -744,
744                         .tall = 16300,
745                         .tiddq = 1,
746                         .ten_count = 1,
747                         .tsample = 163,
748                         .pdiv = 10,
749                 },
750                 [TSENSE_MEM0] = {
751                         .enable = true,
752                         .therm_a = 570,
753                         .therm_b = -744,
754                         .tall = 16300,
755                         .tiddq = 1,
756                         .ten_count = 1,
757                         .tsample = 163,
758                         .pdiv = 10,
759                 },
760                 [TSENSE_MEM1] = {
761                         .enable = true,
762                         .therm_a = 570,
763                         .therm_b = -744,
764                         .tall = 16300,
765                         .tiddq = 1,
766                         .ten_count = 1,
767                         .tsample = 163,
768                         .pdiv = 10,
769                 },
770                 [TSENSE_GPU] = {
771                         .enable = true,
772                         .therm_a = 570,
773                         .therm_b = -744,
774                         .tall = 16300,
775                         .tiddq = 1,
776                         .ten_count = 1,
777                         .tsample = 163,
778                         .pdiv = 10,
779                 },
780                 [TSENSE_PLLX] = {
781                         .enable = true,
782                         .therm_a = 570,
783                         .therm_b = -744,
784                         .tall = 16300,
785                         .tiddq = 1,
786                         .ten_count = 1,
787                         .tsample = 163,
788                         .pdiv = 10,
789                 },
790         },
791 };
792
793 static int __init pluto_soctherm_init(void)
794 {
795         return tegra11_soctherm_init(&pluto_soctherm_data);
796 }
797 module_init(pluto_soctherm_init);