ARM: tegra: Dalmore/Pluto: set vdd_rtc to 900mV in suspend
[linux-2.6.git] / arch / arm / mach-tegra / board-pluto-power.c
1 /*
2  * arch/arm/mach-tegra/board-pluto-power.c
3  *
4  * Copyright (C) 2012 NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
24 #include <linux/io.h>
25
26 #include <mach/iomap.h>
27 #include <mach/irqs.h>
28 #include <linux/regulator/fixed.h>
29 #include <linux/mfd/palmas.h>
30 #include <linux/regulator/machine.h>
31
32 #include <asm/mach-types.h>
33
34 #include "pm.h"
35 #include "board.h"
36 #include "board-pluto.h"
37 #include "tegra_cl_dvfs.h"
38 #include "devices.h"
39
40 #define PMC_CTRL                0x0
41 #define PMC_CTRL_INTR_LOW       (1 << 17)
42
43 /************************ Pluto based regulator ****************/
44 static struct regulator_consumer_supply palmas_smps123_supply[] = {
45         REGULATOR_SUPPLY("vdd_cpu", NULL),
46 };
47
48 static struct regulator_consumer_supply palmas_smps45_supply[] = {
49         REGULATOR_SUPPLY("vdd_core", NULL),
50 };
51
52 static struct regulator_consumer_supply palmas_smps6_supply[] = {
53         REGULATOR_SUPPLY("vdd_core_bb", NULL),
54 };
55
56 static struct regulator_consumer_supply palmas_smps7_supply[] = {
57         REGULATOR_SUPPLY("vddio_ddr", NULL),
58         REGULATOR_SUPPLY("vddio_lpddr3", NULL),
59         REGULATOR_SUPPLY("vcore2_lpddr3", NULL),
60         REGULATOR_SUPPLY("vcore_audio_1v2", NULL),
61 };
62
63 static struct regulator_consumer_supply palmas_smps8_supply[] = {
64         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
65         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
66         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
67         REGULATOR_SUPPLY("avdd_osc", NULL),
68         REGULATOR_SUPPLY("vddio_sys", NULL),
69         REGULATOR_SUPPLY("vddio_bb", NULL),
70         REGULATOR_SUPPLY("pwrdet_bb", NULL),
71         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
72         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
73         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
74         REGULATOR_SUPPLY("vdd_emmc", "sdhci-tegra.3"),
75         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
76         REGULATOR_SUPPLY("vddio_audio", NULL),
77         REGULATOR_SUPPLY("pwrdet_audio", NULL),
78         REGULATOR_SUPPLY("vddio_uart", NULL),
79         REGULATOR_SUPPLY("pwrdet_uart", NULL),
80         REGULATOR_SUPPLY("vddio_gmi", NULL),
81         REGULATOR_SUPPLY("pwrdet_nand", NULL),
82         REGULATOR_SUPPLY("vddio_cam", "tegra_camera"),
83         REGULATOR_SUPPLY("pwrdet_cam", NULL),
84         REGULATOR_SUPPLY("vdd_gps", NULL),
85         REGULATOR_SUPPLY("vdd_nfc", NULL),
86         REGULATOR_SUPPLY("vdd_sensor", NULL),
87         REGULATOR_SUPPLY("vdd_dtv", NULL),
88         REGULATOR_SUPPLY("vdd_bb", NULL),
89         REGULATOR_SUPPLY("vcore1_lpddr", NULL),
90         REGULATOR_SUPPLY("vcore_lpddr", NULL),
91         REGULATOR_SUPPLY("vddio_lpddr", NULL),
92         REGULATOR_SUPPLY("vdd_rf", NULL),
93         REGULATOR_SUPPLY("vdd_modem2", NULL),
94         REGULATOR_SUPPLY("vdd_dbg", NULL),
95         REGULATOR_SUPPLY("vdd_sim_1v8", NULL),
96         REGULATOR_SUPPLY("vdd_sim1a_1v8", NULL),
97         REGULATOR_SUPPLY("vdd_sim1b_1v8", NULL),
98         REGULATOR_SUPPLY("dvdd_audio", NULL),
99         REGULATOR_SUPPLY("avdd_audio", NULL),
100         REGULATOR_SUPPLY("vdd_com_1v8", NULL),
101         REGULATOR_SUPPLY("vdd_bt_1v8", NULL),
102         REGULATOR_SUPPLY("vdd_ts_1v8", NULL),
103         REGULATOR_SUPPLY("avdd_pll_bb", NULL),
104 };
105
106 static struct regulator_consumer_supply palmas_smps9_supply[] = {
107         REGULATOR_SUPPLY("vcore_emmc", NULL),
108         REGULATOR_SUPPLY("vdd_sim_mmc", NULL),
109         REGULATOR_SUPPLY("vdd_sim1a_mmc", NULL),
110         REGULATOR_SUPPLY("vdd_sim1b_mmc", NULL),
111 };
112
113 static struct regulator_consumer_supply palmas_smps10_supply[] = {
114         REGULATOR_SUPPLY("unused_smps10", NULL),
115         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
116         REGULATOR_SUPPLY("vdd_vbrtr", NULL),
117         REGULATOR_SUPPLY("vdd_lcd", NULL),
118 };
119
120 static struct regulator_consumer_supply palmas_ldo1_supply[] = {
121         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
122         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
123         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
124         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegra_camera"),
125         REGULATOR_SUPPLY("avdd_pllm", NULL),
126         REGULATOR_SUPPLY("avdd_pllu", NULL),
127         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
128         REGULATOR_SUPPLY("avdd_pllx", NULL),
129         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
130         REGULATOR_SUPPLY("avdd_plle", NULL),
131 };
132
133 static struct regulator_consumer_supply palmas_ldo2_supply[] = {
134         REGULATOR_SUPPLY("avdd_lcd", NULL),
135 };
136
137 static struct regulator_consumer_supply palmas_ldo3_supply[] = {
138         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
139         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
140         REGULATOR_SUPPLY("avdd_dsi_csi", "tegra_camera"),
141         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
142         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
143         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
144         REGULATOR_SUPPLY("vddio_hsic_bb", NULL),
145         REGULATOR_SUPPLY("vddio_hsic_modem2", NULL),
146 };
147
148 static struct regulator_consumer_supply palmas_ldo4_supply[] = {
149         REGULATOR_SUPPLY("vdd_spare", NULL),
150 };
151
152 static struct regulator_consumer_supply palmas_ldo5_supply[] = {
153         REGULATOR_SUPPLY("avdd_cam1", NULL),
154 };
155
156 static struct regulator_consumer_supply palmas_ldo6_supply[] = {
157         REGULATOR_SUPPLY("vdd_temp", NULL),
158         REGULATOR_SUPPLY("vdd_mb", NULL),
159         REGULATOR_SUPPLY("avdd_ts_3v0", NULL),
160         REGULATOR_SUPPLY("vdd_nfc_3v0", NULL),
161         REGULATOR_SUPPLY("vdd_irled", NULL),
162         REGULATOR_SUPPLY("vdd_sensor_3v0", NULL),
163         REGULATOR_SUPPLY("vdd_3v0_pm", NULL),
164         REGULATOR_SUPPLY("vaux_3v3", NULL),
165         REGULATOR_SUPPLY("vdd", "0-0044"),
166 };
167
168 static struct regulator_consumer_supply palmas_ldo7_supply[] = {
169         REGULATOR_SUPPLY("vdd_af_cam1", NULL),
170 };
171 static struct regulator_consumer_supply palmas_ldo8_supply[] = {
172         REGULATOR_SUPPLY("vdd_rtc", NULL),
173 };
174 static struct regulator_consumer_supply palmas_ldo9_supply[] = {
175         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
176         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
177 };
178 static struct regulator_consumer_supply palmas_ldoln_supply[] = {
179         REGULATOR_SUPPLY("avdd_cam2", NULL),
180 };
181
182 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
183         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
184         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
185         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
186         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
187         REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
188         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
189         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
190         REGULATOR_SUPPLY("pwrdet_hv", NULL),
191         REGULATOR_SUPPLY("vdd_dtv_3v3", NULL),
192
193 };
194
195 static struct regulator_consumer_supply palmas_regen1_supply[] = {
196         REGULATOR_SUPPLY("mic_ventral", NULL),
197 };
198
199 static struct regulator_consumer_supply palmas_regen2_supply[] = {
200         REGULATOR_SUPPLY("vdd_mic", NULL),
201 };
202
203 #define PALMAS_PDATA_INIT(_name, _minmv, _maxmv, _supply_reg, _always_on, \
204         _boot_on, _apply_uv)                                            \
205         static struct regulator_init_data reg_idata_##_name = {         \
206                 .constraints = {                                        \
207                         .name = palmas_rails(_name),                    \
208                         .min_uV = (_minmv)*1000,                        \
209                         .max_uV = (_maxmv)*1000,                        \
210                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
211                                         REGULATOR_MODE_STANDBY),        \
212                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
213                                         REGULATOR_CHANGE_STATUS |       \
214                                         REGULATOR_CHANGE_VOLTAGE),      \
215                         .always_on = _always_on,                        \
216                         .boot_on = _boot_on,                            \
217                         .apply_uV = _apply_uv,                          \
218                 },                                                      \
219                 .num_consumer_supplies =                                \
220                         ARRAY_SIZE(palmas_##_name##_supply),            \
221                 .consumer_supplies = palmas_##_name##_supply,           \
222                 .supply_regulator = _supply_reg,                        \
223         }
224
225 PALMAS_PDATA_INIT(smps123, 900,  1300, NULL, 0, 0, 0);
226 PALMAS_PDATA_INIT(smps45, 900,  1400, NULL, 0, 0, 0);
227 PALMAS_PDATA_INIT(smps6, 850,  850, NULL, 0, 0, 1);
228 PALMAS_PDATA_INIT(smps7, 1200,  1200, NULL, 0, 0, 1);
229 PALMAS_PDATA_INIT(smps8, 1800,  1800, NULL, 0, 1, 1);
230 PALMAS_PDATA_INIT(smps9, 2800,  2800, NULL, 0, 0, 1);
231 PALMAS_PDATA_INIT(smps10, 5000,  5000, NULL, 0, 0, 0);
232 PALMAS_PDATA_INIT(ldo1, 1050,  1050, palmas_rails(smps7), 0, 0, 1);
233 PALMAS_PDATA_INIT(ldo2, 2800,  3000, NULL, 0, 0, 0);
234 PALMAS_PDATA_INIT(ldo3, 1200,  1200, palmas_rails(smps8), 0, 1, 1);
235 PALMAS_PDATA_INIT(ldo4, 900,  3300, NULL, 0, 0, 0);
236 PALMAS_PDATA_INIT(ldo5, 2700,  2700, NULL, 0, 0, 1);
237 PALMAS_PDATA_INIT(ldo6, 3000,  3000, NULL, 0, 0, 1);
238 PALMAS_PDATA_INIT(ldo7, 2800,  2800, NULL, 0, 0, 1);
239 PALMAS_PDATA_INIT(ldo8, 900,  900, NULL, 1, 1, 1);
240 PALMAS_PDATA_INIT(ldo9, 1800,  3300, palmas_rails(smps9), 0, 0, 1);
241 PALMAS_PDATA_INIT(ldoln, 2700, 2700, NULL, 0, 0, 1);
242 PALMAS_PDATA_INIT(ldousb, 3300,  3300, NULL, 0, 0, 1);
243 PALMAS_PDATA_INIT(regen1, 4300,  4300, NULL, 0, 0, 0);
244 PALMAS_PDATA_INIT(regen2, 4300,  4300, palmas_rails(smps8), 0, 0, 0);
245
246 #define PALMAS_REG_PDATA(_sname) &reg_idata_##_sname
247
248 static struct regulator_init_data *pluto_reg_data[PALMAS_NUM_REGS] = {
249         NULL,
250         PALMAS_REG_PDATA(smps123),
251         NULL,
252         PALMAS_REG_PDATA(smps45),
253         NULL,
254         PALMAS_REG_PDATA(smps6),
255         PALMAS_REG_PDATA(smps7),
256         PALMAS_REG_PDATA(smps8),
257         PALMAS_REG_PDATA(smps9),
258         PALMAS_REG_PDATA(smps10),
259         PALMAS_REG_PDATA(ldo1),
260         PALMAS_REG_PDATA(ldo2),
261         PALMAS_REG_PDATA(ldo3),
262         PALMAS_REG_PDATA(ldo4),
263         PALMAS_REG_PDATA(ldo5),
264         PALMAS_REG_PDATA(ldo6),
265         PALMAS_REG_PDATA(ldo7),
266         PALMAS_REG_PDATA(ldo8),
267         PALMAS_REG_PDATA(ldo9),
268         PALMAS_REG_PDATA(ldoln),
269         PALMAS_REG_PDATA(ldousb),
270         PALMAS_REG_PDATA(regen1),
271         PALMAS_REG_PDATA(regen2),
272         NULL,
273         NULL,
274         NULL,
275 };
276
277 #define PALMAS_REG_INIT(_name, _warm_reset, _roof_floor, _mode_sleep,   \
278                 _tstep, _vsel)                                          \
279         static struct palmas_reg_init reg_init_data_##_name = {         \
280                 .warm_reset = _warm_reset,                              \
281                 .roof_floor =   _roof_floor,                            \
282                 .mode_sleep = _mode_sleep,              \
283                 .tstep = _tstep,                        \
284                 .vsel = _vsel,          \
285         }
286
287 PALMAS_REG_INIT(smps12, 0, 0, 0, 0, 0);
288 PALMAS_REG_INIT(smps123, 0, PALMAS_EXT_CONTROL_ENABLE1, 0, 0, 0);
289 PALMAS_REG_INIT(smps3, 0, 0, 0, 0, 0);
290 PALMAS_REG_INIT(smps45, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
291 PALMAS_REG_INIT(smps457, 0, 0, 0, 0, 0);
292 PALMAS_REG_INIT(smps6, 0, PALMAS_EXT_CONTROL_ENABLE2, 0, 0, 0);
293 PALMAS_REG_INIT(smps7, 0, 0, 0, 0, 0);
294 PALMAS_REG_INIT(smps8, 0, 0, 0, 0, 0);
295 PALMAS_REG_INIT(smps9, 0, 0, 0, 0, 0);
296 PALMAS_REG_INIT(smps10, 0, 0, 0, 0, 0);
297 PALMAS_REG_INIT(ldo1, 0, 0, 0, 0, 0);
298 PALMAS_REG_INIT(ldo2, 0, 0, 0, 0, 0);
299 PALMAS_REG_INIT(ldo3, 0, 0, 0, 0, 0);
300 PALMAS_REG_INIT(ldo4, 0, 0, 0, 0, 0);
301 PALMAS_REG_INIT(ldo5, 0, 0, 0, 0, 0);
302 PALMAS_REG_INIT(ldo6, 0, 0, 0, 0, 0);
303 PALMAS_REG_INIT(ldo7, 0, 0, 0, 0, 0);
304 PALMAS_REG_INIT(ldo8, 0, 0, 0, 0, 0);
305 PALMAS_REG_INIT(ldo9, 0, 0, 0, 0, 0);
306 PALMAS_REG_INIT(ldoln, 0, 0, 0, 0, 0);
307 PALMAS_REG_INIT(ldousb, 0, 0, 0, 0, 0);
308
309 #define PALMAS_REG_INIT_DATA(_sname) &reg_init_data_##_sname
310 static struct palmas_reg_init *pluto_reg_init[PALMAS_NUM_REGS] = {
311         PALMAS_REG_INIT_DATA(smps12),
312         PALMAS_REG_INIT_DATA(smps123),
313         PALMAS_REG_INIT_DATA(smps3),
314         PALMAS_REG_INIT_DATA(smps45),
315         PALMAS_REG_INIT_DATA(smps457),
316         PALMAS_REG_INIT_DATA(smps6),
317         PALMAS_REG_INIT_DATA(smps7),
318         PALMAS_REG_INIT_DATA(smps8),
319         PALMAS_REG_INIT_DATA(smps9),
320         PALMAS_REG_INIT_DATA(smps10),
321         PALMAS_REG_INIT_DATA(ldo1),
322         PALMAS_REG_INIT_DATA(ldo2),
323         PALMAS_REG_INIT_DATA(ldo3),
324         PALMAS_REG_INIT_DATA(ldo4),
325         PALMAS_REG_INIT_DATA(ldo5),
326         PALMAS_REG_INIT_DATA(ldo6),
327         PALMAS_REG_INIT_DATA(ldo7),
328         PALMAS_REG_INIT_DATA(ldo8),
329         PALMAS_REG_INIT_DATA(ldo9),
330         PALMAS_REG_INIT_DATA(ldoln),
331         PALMAS_REG_INIT_DATA(ldousb),
332 };
333
334 static int ac_online(void)
335 {
336         return 1;
337 }
338
339 static struct resource pluto_pda_resources[] = {
340         [0] = {
341                 .name   = "ac",
342         },
343 };
344
345 static struct pda_power_pdata pluto_pda_data = {
346         .is_ac_online   = ac_online,
347 };
348
349 static struct platform_device pluto_pda_power_device = {
350         .name           = "pda-power",
351         .id             = -1,
352         .resource       = pluto_pda_resources,
353         .num_resources  = ARRAY_SIZE(pluto_pda_resources),
354         .dev    = {
355                 .platform_data  = &pluto_pda_data,
356         },
357 };
358
359 /* Always ON /Battery regulator */
360 static struct regulator_consumer_supply fixed_reg_en_battery_supply[] = {
361                 REGULATOR_SUPPLY("vdd_sys_cam", NULL),
362                 REGULATOR_SUPPLY("vdd_sys_bl", NULL),
363                 REGULATOR_SUPPLY("vdd_sys_com", NULL),
364                 REGULATOR_SUPPLY("vdd_sys_gps", NULL),
365                 REGULATOR_SUPPLY("vdd_sys_bt", NULL),
366 };
367
368 static struct regulator_consumer_supply fixed_reg_en_vdd_1v8_cam_supply[] = {
369         REGULATOR_SUPPLY("vddio_cam_mb", NULL),
370         REGULATOR_SUPPLY("vdd_1v8_cam12", NULL),
371 };
372
373 static struct regulator_consumer_supply fixed_reg_en_vdd_1v2_cam_supply[] = {
374         REGULATOR_SUPPLY("vdd_1v2_cam", NULL),
375 };
376
377 static struct regulator_consumer_supply fixed_reg_en_avdd_usb3_1v05_supply[] = {
378         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
379         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
380 };
381
382 static struct regulator_consumer_supply fixed_reg_en_vdd_mmc_sdmmc3_supply[] = {
383         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
384 };
385
386 static struct regulator_consumer_supply fixed_reg_en_vdd_lcd_1v8_supply[] = {
387         REGULATOR_SUPPLY("vdd_lcd_1v8_s", NULL),
388 };
389
390 static struct regulator_consumer_supply fixed_reg_en_vdd_lcd_mmc_supply[] = {
391         REGULATOR_SUPPLY("vdd_lcd_mmc_s_f", NULL),
392 };
393
394 static struct regulator_consumer_supply fixed_reg_en_vdd_1v8_mic_supply[] = {
395         REGULATOR_SUPPLY("unused_fixed_reg_en_vdd_1v8_mic", NULL),
396 };
397
398 static struct regulator_consumer_supply fixed_reg_en_vdd_hdmi_5v0_supply[] = {
399         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
400 };
401
402 static struct regulator_consumer_supply fixed_reg_en_vpp_fuse_supply[] = {
403         REGULATOR_SUPPLY("vpp_fuse", NULL),
404         REGULATOR_SUPPLY("v_efuse", NULL),
405 };
406
407 /* Macro for defining fixed regulator sub device data */
408 #define FIXED_SUPPLY(_name) "fixed_reg_en"#_name
409 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,   \
410         _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts,  \
411         _sdelay)                                                        \
412         static struct regulator_init_data ri_data_##_var =              \
413         {                                                               \
414                 .supply_regulator = _in_supply,                         \
415                 .num_consumer_supplies =                                \
416                         ARRAY_SIZE(fixed_reg_en_##_name##_supply),      \
417                 .consumer_supplies = fixed_reg_en_##_name##_supply,     \
418                 .constraints = {                                        \
419                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
420                                         REGULATOR_MODE_STANDBY),        \
421                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
422                                         REGULATOR_CHANGE_STATUS |       \
423                                         REGULATOR_CHANGE_VOLTAGE),      \
424                         .always_on = _always_on,                        \
425                         .boot_on = _boot_on,                            \
426                 },                                                      \
427         };                                                              \
428         static struct fixed_voltage_config fixed_reg_en_##_var##_pdata = \
429         {                                                               \
430                 .supply_name = FIXED_SUPPLY(_name),                     \
431                 .microvolts = _millivolts * 1000,                       \
432                 .gpio = _gpio_nr,                                       \
433                 .gpio_is_open_drain = _open_drain,                      \
434                 .enable_high = _active_high,                            \
435                 .enabled_at_boot = _boot_state,                         \
436                 .init_data = &ri_data_##_var,                           \
437                 .startup_delay = _sdelay                                \
438         };                                                              \
439         static struct platform_device fixed_reg_en_##_var##_dev = {     \
440                 .name = "reg-fixed-voltage",                            \
441                 .id = _id,                                              \
442                 .dev = {                                                \
443                         .platform_data = &fixed_reg_en_##_var##_pdata,  \
444                 },                                                      \
445         }
446
447 FIXED_REG(0,    battery,        battery,
448         NULL,   0,      0,
449         -1,     false, true,    0,      3300,   0);
450
451 FIXED_REG(1,    vdd_1v8_cam,    vdd_1v8_cam,
452         palmas_rails(smps8),    0,      0,
453         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO1,  false, true,    0,      1800,
454         0);
455
456 FIXED_REG(2,    vdd_1v2_cam,    vdd_1v2_cam,
457         palmas_rails(smps7),    0,      0,
458         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO2,  false, true,    0,      1200,
459         0);
460
461 FIXED_REG(3,    avdd_usb3_1v05, avdd_usb3_1v05,
462         palmas_rails(smps8),    0,      0,
463         TEGRA_GPIO_PK5, false,  true,   0,      1050,   0);
464
465 FIXED_REG(4,    vdd_mmc_sdmmc3, vdd_mmc_sdmmc3,
466         palmas_rails(smps9),    0,      0,
467         TEGRA_GPIO_PK1, false,  true,   0,      3300,   0);
468
469 FIXED_REG(5,    vdd_lcd_1v8,    vdd_lcd_1v8,
470         palmas_rails(smps8),    0,      0,
471         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO4,  false,  true,   0,      1800,
472         0);
473
474 FIXED_REG(6,    vdd_lcd_mmc,    vdd_lcd_mmc,
475         palmas_rails(smps9),    0,      0,
476         TEGRA_GPIO_PI4, false,  true,   0,      1800,   0);
477
478 FIXED_REG(7,    vdd_1v8_mic,    vdd_1v8_mic,
479         palmas_rails(smps8),    0,      0,
480         -1,     false,  true,   0,      1800,   0);
481
482 FIXED_REG(8,    vdd_hdmi_5v0,   vdd_hdmi_5v0,
483         NULL,   0,      0,
484         TEGRA_GPIO_PK6, true,   true,   0,      5000,   5000);
485
486 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
487 FIXED_REG(9,    vpp_fuse,       vpp_fuse,
488         palmas_rails(smps8),    0,      0,
489         TEGRA_GPIO_PX4, false,  true,   0,      1800,   0);
490 #else
491 FIXED_REG(9,    vpp_fuse,       vpp_fuse,
492         palmas_rails(smps8),    0,      0,
493         TEGRA_GPIO_PX0, false,  true,   0,      1800,   0);
494 #endif
495
496 /*
497  * Creating the fixed regulator device tables
498  */
499 #define ADD_FIXED_REG(_name)    (&fixed_reg_en_##_name##_dev)
500
501 #define E1580_COMMON_FIXED_REG                  \
502         ADD_FIXED_REG(battery),                 \
503         ADD_FIXED_REG(vdd_1v8_cam),             \
504         ADD_FIXED_REG(vdd_1v2_cam),             \
505         ADD_FIXED_REG(avdd_usb3_1v05),          \
506         ADD_FIXED_REG(vdd_mmc_sdmmc3),          \
507         ADD_FIXED_REG(vdd_lcd_1v8),             \
508         ADD_FIXED_REG(vdd_lcd_mmc),             \
509         ADD_FIXED_REG(vdd_1v8_mic),             \
510         ADD_FIXED_REG(vdd_hdmi_5v0),
511
512 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
513 #define E1580_T114_FIXED_REG                    \
514         ADD_FIXED_REG(vpp_fuse),
515 #endif
516
517 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
518 #define E1580_T30_FIXED_REG                     \
519         ADD_FIXED_REG(vpp_fuse),
520 #endif
521
522 /* Gpio switch regulator platform data for Pluto E1580 */
523 static struct platform_device *pfixed_reg_devs[] = {
524         E1580_COMMON_FIXED_REG
525 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
526         E1580_T114_FIXED_REG
527 #endif
528 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
529         E1580_T30_FIXED_REG
530 #endif
531 };
532
533 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
534 /* board parameters for cpu dfll */
535 static struct tegra_cl_dvfs_cfg_param pluto_cl_dvfs_param = {
536         .sample_rate = 12500,
537
538         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
539         .cf = 10,
540         .ci = 0,
541         .cg = 2,
542
543         .droop_cut_value = 0xF,
544         .droop_restore_ramp = 0x0,
545         .scale_out_ramp = 0x0,
546 };
547 #endif
548
549 /* palmas: fixed 10mV steps from 600mV to 1400mV, with offset 0x10 */
550 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
551 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
552 static inline void fill_reg_map(void)
553 {
554         int i;
555         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
556                 pmu_cpu_vdd_map[i].reg_value = i + 0x10;
557                 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
558         }
559 }
560
561 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
562 static struct tegra_cl_dvfs_platform_data pluto_cl_dvfs_data = {
563         .dfll_clk_name = "dfll_cpu",
564         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
565         .u.pmu_i2c = {
566                 .fs_rate = 400000,
567                 .slave_addr = 0xb0,
568                 .reg = 0x23,
569         },
570         .vdd_map = pmu_cpu_vdd_map,
571         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
572
573         .cfg_param = &pluto_cl_dvfs_param,
574 };
575
576 static int __init pluto_cl_dvfs_init(void)
577 {
578         fill_reg_map();
579         tegra_cl_dvfs_device.dev.platform_data = &pluto_cl_dvfs_data;
580         platform_device_register(&tegra_cl_dvfs_device);
581
582         return 0;
583 }
584 #endif
585
586 static struct palmas_pmic_platform_data pmic_platform = {
587         .enable_ldo8_tracking = true,
588         .disabe_ldo8_tracking_suspend = true,
589 };
590
591 struct palmas_clk32k_init_data palmas_clk32k_idata[] = {
592         {
593                 .clk32k_id = PALMAS_CLOCK32KG,
594                 .enable = true,
595         }, {
596                 .clk32k_id = PALMAS_CLOCK32KG_AUDIO,
597                 .enable = true,
598         },
599 };
600
601 static struct palmas_platform_data palmas_pdata = {
602         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
603         .irq_base = PALMAS_TEGRA_IRQ_BASE,
604         .pmic_pdata = &pmic_platform,
605         .mux_from_pdata = true,
606         .pad1 = 0,
607         .pad2 = (PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK &
608                         (1 << PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT)),
609         .clk32k_init_data =  palmas_clk32k_idata,
610         .clk32k_init_data_size = ARRAY_SIZE(palmas_clk32k_idata),
611 };
612
613 static struct i2c_board_info palma_device[] = {
614         {
615                 I2C_BOARD_INFO("tps65913", 0x58),
616                 .irq            = INT_EXTERNAL_PMU,
617                 .platform_data  = &palmas_pdata,
618         },
619 };
620
621 int __init pluto_regulator_init(void)
622 {
623         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
624         u32 pmc_ctrl;
625         int i;
626
627 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
628         pluto_cl_dvfs_init();
629 #endif
630
631         /* TPS65913: Normal state of INT request line is LOW.
632          * configure the power management controller to trigger PMU
633          * interrupts when HIGH.
634          */
635         pmc_ctrl = readl(pmc + PMC_CTRL);
636         writel(pmc_ctrl & ~PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
637
638         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
639                 pmic_platform.reg_data[i] = pluto_reg_data[i];
640                 pmic_platform.reg_init[i] = pluto_reg_init[i];
641         }
642
643         platform_device_register(&pluto_pda_power_device);
644         i2c_register_board_info(4, palma_device,
645                         ARRAY_SIZE(palma_device));
646         return 0;
647 }
648
649 static int __init pluto_fixed_regulator_init(void)
650 {
651         if (!machine_is_tegra_pluto())
652                 return 0;
653
654         return platform_add_devices(pfixed_reg_devs,
655                         ARRAY_SIZE(pfixed_reg_devs));
656 }
657 subsys_initcall_sync(pluto_fixed_regulator_init);
658
659 static struct tegra_suspend_platform_data pluto_suspend_data = {
660         .cpu_timer      = 2000,
661         .cpu_off_timer  = 2000,
662         .suspend_mode   = TEGRA_SUSPEND_LP0,
663         .core_timer     = 0x7e7e,
664         .core_off_timer = 2000,
665         .corereq_high   = false,
666         .sysclkreq_high = true,
667 };
668
669 int __init pluto_suspend_init(void)
670 {
671         tegra_init_suspend(&pluto_suspend_data);
672         return 0;
673 }
674