ARM: tegra: pluto: updating regulators sources for xusb
[linux-2.6.git] / arch / arm / mach-tegra / board-pluto-power.c
1 /*
2  * arch/arm/mach-tegra/board-pluto-power.c
3  *
4  * Copyright (C) 2012-2013 NVIDIA Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
24 #include <linux/io.h>
25
26 #include <mach/iomap.h>
27 #include <mach/edp.h>
28 #include <mach/irqs.h>
29 #include <linux/regulator/fixed.h>
30 #include <linux/mfd/palmas.h>
31 #include <linux/regulator/machine.h>
32 #include <linux/irq.h>
33
34 #include <asm/mach-types.h>
35
36 #include "cpu-tegra.h"
37 #include "pm.h"
38 #include "board.h"
39 #include "board-pluto.h"
40 #include "tegra_cl_dvfs.h"
41 #include "devices.h"
42 #include "tegra11_soctherm.h"
43
44 #define PMC_CTRL                0x0
45 #define PMC_CTRL_INTR_LOW       (1 << 17)
46
47 /************************ Pluto based regulator ****************/
48 static struct regulator_consumer_supply palmas_smps123_supply[] = {
49         REGULATOR_SUPPLY("vdd_cpu", NULL),
50 };
51
52 static struct regulator_consumer_supply palmas_smps45_supply[] = {
53         REGULATOR_SUPPLY("vdd_core", NULL),
54 };
55
56 static struct regulator_consumer_supply palmas_smps6_supply[] = {
57         REGULATOR_SUPPLY("vdd_core_bb", NULL),
58 };
59
60 static struct regulator_consumer_supply palmas_smps7_supply[] = {
61         REGULATOR_SUPPLY("vddio_ddr", NULL),
62         REGULATOR_SUPPLY("vddio_lpddr3", NULL),
63         REGULATOR_SUPPLY("vcore2_lpddr3", NULL),
64         REGULATOR_SUPPLY("vcore_audio_1v2", NULL),
65 };
66
67 static struct regulator_consumer_supply palmas_smps8_supply[] = {
68         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
69         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
70         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
71         REGULATOR_SUPPLY("avdd_osc", NULL),
72         REGULATOR_SUPPLY("vddio_sys", NULL),
73         REGULATOR_SUPPLY("vddio_bb", NULL),
74         REGULATOR_SUPPLY("pwrdet_bb", NULL),
75         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
76         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
77         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
78         REGULATOR_SUPPLY("vdd_emmc", "sdhci-tegra.3"),
79         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
80         REGULATOR_SUPPLY("vddio_audio", NULL),
81         REGULATOR_SUPPLY("pwrdet_audio", NULL),
82         REGULATOR_SUPPLY("vddio_uart", NULL),
83         REGULATOR_SUPPLY("pwrdet_uart", NULL),
84         REGULATOR_SUPPLY("vddio_gmi", NULL),
85         REGULATOR_SUPPLY("pwrdet_nand", NULL),
86         REGULATOR_SUPPLY("vddio_cam", "vi"),
87         REGULATOR_SUPPLY("pwrdet_cam", NULL),
88         REGULATOR_SUPPLY("vdd_gps", NULL),
89         REGULATOR_SUPPLY("vdd_nfc", NULL),
90         REGULATOR_SUPPLY("vlogic", "0-0069"),
91         REGULATOR_SUPPLY("vdd_dtv", NULL),
92         REGULATOR_SUPPLY("vdd_bb", NULL),
93         REGULATOR_SUPPLY("vcore1_lpddr", NULL),
94         REGULATOR_SUPPLY("vcore_lpddr", NULL),
95         REGULATOR_SUPPLY("vddio_lpddr", NULL),
96         REGULATOR_SUPPLY("vdd_rf", NULL),
97         REGULATOR_SUPPLY("vdd_modem2", NULL),
98         REGULATOR_SUPPLY("vdd_dbg", NULL),
99         REGULATOR_SUPPLY("vdd_sim_1v8", NULL),
100         REGULATOR_SUPPLY("vdd_sim1a_1v8", NULL),
101         REGULATOR_SUPPLY("vdd_sim1b_1v8", NULL),
102         REGULATOR_SUPPLY("dvdd_audio", NULL),
103         REGULATOR_SUPPLY("avdd_audio", NULL),
104         REGULATOR_SUPPLY("vdd_com_1v8", NULL),
105         REGULATOR_SUPPLY("vdd_bt_1v8", NULL),
106         REGULATOR_SUPPLY("dvdd", "spi3.2"),
107         REGULATOR_SUPPLY("avdd_pll_bb", NULL),
108 };
109
110 static struct regulator_consumer_supply palmas_smps9_supply[] = {
111         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
112         REGULATOR_SUPPLY("vdd_sim_mmc", NULL),
113         REGULATOR_SUPPLY("vdd_sim1a_mmc", NULL),
114         REGULATOR_SUPPLY("vdd_sim1b_mmc", NULL),
115 };
116
117 static struct regulator_consumer_supply palmas_smps10_supply[] = {
118         REGULATOR_SUPPLY("unused_smps10", NULL),
119         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
120         REGULATOR_SUPPLY("avddio_usb", "tegra-xhci"),
121         REGULATOR_SUPPLY("usb_vbus", "tegra-xhci"),
122         REGULATOR_SUPPLY("vdd_vbrtr", NULL),
123         REGULATOR_SUPPLY("vdd_lcd", NULL),
124 };
125
126 static struct regulator_consumer_supply palmas_ldo1_supply[] = {
127         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
128         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
129         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
130         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "vi"),
131         REGULATOR_SUPPLY("avdd_pllm", NULL),
132         REGULATOR_SUPPLY("avdd_pllu", NULL),
133         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
134         REGULATOR_SUPPLY("avdd_pllx", NULL),
135         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
136         REGULATOR_SUPPLY("avdd_plle", NULL),
137 };
138
139 static struct regulator_consumer_supply palmas_ldo2_supply[] = {
140         REGULATOR_SUPPLY("avdd_lcd", NULL),
141 };
142
143 static struct regulator_consumer_supply palmas_ldo3_supply[] = {
144         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
145         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
146         REGULATOR_SUPPLY("avdd_dsi_csi", "vi"),
147         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
148         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
149         REGULATOR_SUPPLY("vddio_hsic", "tegra-xhci"),
150         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
151         REGULATOR_SUPPLY("vddio_hsic_bb", NULL),
152         REGULATOR_SUPPLY("vddio_hsic_modem2", NULL),
153 };
154
155 static struct regulator_consumer_supply palmas_ldo4_supply[] = {
156         REGULATOR_SUPPLY("vdd_spare", NULL),
157 };
158
159 static struct regulator_consumer_supply palmas_ldo5_supply[] = {
160         REGULATOR_SUPPLY("avdd_cam1", NULL),
161         REGULATOR_SUPPLY("vana", "2-0010"),
162 };
163
164 static struct regulator_consumer_supply palmas_ldo6_supply[] = {
165         REGULATOR_SUPPLY("vdd_temp", NULL),
166         REGULATOR_SUPPLY("vdd_mb", NULL),
167         REGULATOR_SUPPLY("vin", "1-004d"),
168         REGULATOR_SUPPLY("vdd_nfc_3v0", NULL),
169         REGULATOR_SUPPLY("vdd_irled", NULL),
170         REGULATOR_SUPPLY("vdd_sensor_3v0", NULL),
171         REGULATOR_SUPPLY("vdd_3v0_pm", NULL),
172         REGULATOR_SUPPLY("vaux_3v3", NULL),
173         REGULATOR_SUPPLY("vdd", "0-0044"),
174         REGULATOR_SUPPLY("vdd", "0-004c"),
175         REGULATOR_SUPPLY("avdd", "spi3.2"),
176         REGULATOR_SUPPLY("vdd", "0-0069"),
177 };
178
179 static struct regulator_consumer_supply palmas_ldo7_supply[] = {
180         REGULATOR_SUPPLY("vdd_af_cam1", NULL),
181         REGULATOR_SUPPLY("vdd", "2-000e"),
182 };
183 static struct regulator_consumer_supply palmas_ldo8_supply[] = {
184         REGULATOR_SUPPLY("vdd_rtc", NULL),
185 };
186 static struct regulator_consumer_supply palmas_ldo9_supply[] = {
187         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
188         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
189 };
190 static struct regulator_consumer_supply palmas_ldoln_supply[] = {
191         REGULATOR_SUPPLY("avdd_cam2", NULL),
192         REGULATOR_SUPPLY("vana", "2-0036"),
193 };
194
195 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
196         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
197         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
198         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
199         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
200         REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
201         REGULATOR_SUPPLY("hvdd_usb", "tegra-xhci"),
202         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
203         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
204         REGULATOR_SUPPLY("pwrdet_hv", NULL),
205         REGULATOR_SUPPLY("vdd_dtv_3v3", NULL),
206
207 };
208
209 static struct regulator_consumer_supply palmas_regen1_supply[] = {
210         REGULATOR_SUPPLY("mic_ventral", NULL),
211 };
212
213 static struct regulator_consumer_supply palmas_regen2_supply[] = {
214         REGULATOR_SUPPLY("vdd_mic", NULL),
215 };
216
217 #define PALMAS_PDATA_INIT(_name, _minmv, _maxmv, _supply_reg, _always_on, \
218         _boot_on, _apply_uv)                                            \
219         static struct regulator_init_data reg_idata_##_name = {         \
220                 .constraints = {                                        \
221                         .name = palmas_rails(_name),                    \
222                         .min_uV = (_minmv)*1000,                        \
223                         .max_uV = (_maxmv)*1000,                        \
224                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
225                                         REGULATOR_MODE_STANDBY),        \
226                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
227                                         REGULATOR_CHANGE_STATUS |       \
228                                         REGULATOR_CHANGE_VOLTAGE),      \
229                         .always_on = _always_on,                        \
230                         .boot_on = _boot_on,                            \
231                         .apply_uV = _apply_uv,                          \
232                 },                                                      \
233                 .num_consumer_supplies =                                \
234                         ARRAY_SIZE(palmas_##_name##_supply),            \
235                 .consumer_supplies = palmas_##_name##_supply,           \
236                 .supply_regulator = _supply_reg,                        \
237         }
238
239 PALMAS_PDATA_INIT(smps123, 900,  1300, NULL, 0, 0, 0);
240 PALMAS_PDATA_INIT(smps45, 900,  1400, NULL, 0, 0, 0);
241 PALMAS_PDATA_INIT(smps6, 850,  850, NULL, 0, 0, 1);
242 PALMAS_PDATA_INIT(smps7, 1200,  1200, NULL, 0, 0, 1);
243 PALMAS_PDATA_INIT(smps8, 1800,  1800, NULL, 1, 1, 1);
244 PALMAS_PDATA_INIT(smps9, 2800,  2800, NULL, 1, 0, 1);
245 PALMAS_PDATA_INIT(smps10, 5000,  5000, NULL, 0, 0, 0);
246 PALMAS_PDATA_INIT(ldo1, 1050,  1050, palmas_rails(smps7), 0, 0, 1);
247 PALMAS_PDATA_INIT(ldo2, 2800,  3000, NULL, 0, 0, 0);
248 PALMAS_PDATA_INIT(ldo3, 1200,  1200, palmas_rails(smps8), 0, 1, 1);
249 PALMAS_PDATA_INIT(ldo4, 900,  3300, NULL, 0, 0, 0);
250 PALMAS_PDATA_INIT(ldo5, 2700,  2700, NULL, 0, 0, 1);
251 PALMAS_PDATA_INIT(ldo6, 3000,  3000, NULL, 1, 1, 1);
252 PALMAS_PDATA_INIT(ldo7, 2800,  2800, NULL, 0, 0, 1);
253 PALMAS_PDATA_INIT(ldo8, 900,  900, NULL, 1, 1, 1);
254 PALMAS_PDATA_INIT(ldo9, 1800,  3300, palmas_rails(smps9), 0, 0, 1);
255 PALMAS_PDATA_INIT(ldoln, 2700, 2700, NULL, 0, 0, 1);
256 PALMAS_PDATA_INIT(ldousb, 3300,  3300, NULL, 0, 0, 1);
257 PALMAS_PDATA_INIT(regen1, 4300,  4300, NULL, 0, 0, 0);
258 PALMAS_PDATA_INIT(regen2, 4300,  4300, palmas_rails(smps8), 0, 0, 0);
259
260 #define PALMAS_REG_PDATA(_sname) &reg_idata_##_sname
261
262 static struct regulator_init_data *pluto_reg_data[PALMAS_NUM_REGS] = {
263         NULL,
264         PALMAS_REG_PDATA(smps123),
265         NULL,
266         PALMAS_REG_PDATA(smps45),
267         NULL,
268         PALMAS_REG_PDATA(smps6),
269         PALMAS_REG_PDATA(smps7),
270         PALMAS_REG_PDATA(smps8),
271         PALMAS_REG_PDATA(smps9),
272         PALMAS_REG_PDATA(smps10),
273         PALMAS_REG_PDATA(ldo1),
274         PALMAS_REG_PDATA(ldo2),
275         PALMAS_REG_PDATA(ldo3),
276         PALMAS_REG_PDATA(ldo4),
277         PALMAS_REG_PDATA(ldo5),
278         PALMAS_REG_PDATA(ldo6),
279         PALMAS_REG_PDATA(ldo7),
280         PALMAS_REG_PDATA(ldo8),
281         PALMAS_REG_PDATA(ldo9),
282         PALMAS_REG_PDATA(ldoln),
283         PALMAS_REG_PDATA(ldousb),
284         PALMAS_REG_PDATA(regen1),
285         PALMAS_REG_PDATA(regen2),
286         NULL,
287         NULL,
288         NULL,
289 };
290
291 #define PALMAS_REG_INIT(_name, _warm_reset, _roof_floor, _mode_sleep,   \
292                 _tstep, _vsel)                                          \
293         static struct palmas_reg_init reg_init_data_##_name = {         \
294                 .warm_reset = _warm_reset,                              \
295                 .roof_floor =   _roof_floor,                            \
296                 .mode_sleep = _mode_sleep,              \
297                 .tstep = _tstep,                        \
298                 .vsel = _vsel,          \
299         }
300
301 PALMAS_REG_INIT(smps12, 0, 0, 0, 0, 0);
302 PALMAS_REG_INIT(smps123, 0, PALMAS_EXT_CONTROL_ENABLE1, 0, 0, 0);
303 PALMAS_REG_INIT(smps3, 0, 0, 0, 0, 0);
304 PALMAS_REG_INIT(smps45, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
305 PALMAS_REG_INIT(smps457, 0, 0, 0, 0, 0);
306 PALMAS_REG_INIT(smps6, 0, 0, 0, 0, 0);
307 PALMAS_REG_INIT(smps7, 0, 0, 0, 0, 0);
308 PALMAS_REG_INIT(smps8, 0, 0, 0, 0, 0);
309 PALMAS_REG_INIT(smps9, 0, 0, 0, 0, 0);
310 PALMAS_REG_INIT(smps10, 0, 0, 0, 0, 0);
311 PALMAS_REG_INIT(ldo1, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
312 PALMAS_REG_INIT(ldo2, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
313 PALMAS_REG_INIT(ldo3, 0, 0, 0, 0, 0);
314 PALMAS_REG_INIT(ldo4, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
315 PALMAS_REG_INIT(ldo5, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
316 PALMAS_REG_INIT(ldo6, 0, 0, 0, 0, 0);
317 PALMAS_REG_INIT(ldo7, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
318 PALMAS_REG_INIT(ldo8, 0, 0, 0, 0, 0);
319 PALMAS_REG_INIT(ldo9, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
320 PALMAS_REG_INIT(ldoln, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
321 PALMAS_REG_INIT(ldousb, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
322
323 #define PALMAS_REG_INIT_DATA(_sname) &reg_init_data_##_sname
324 static struct palmas_reg_init *pluto_reg_init[PALMAS_NUM_REGS] = {
325         PALMAS_REG_INIT_DATA(smps12),
326         PALMAS_REG_INIT_DATA(smps123),
327         PALMAS_REG_INIT_DATA(smps3),
328         PALMAS_REG_INIT_DATA(smps45),
329         PALMAS_REG_INIT_DATA(smps457),
330         PALMAS_REG_INIT_DATA(smps6),
331         PALMAS_REG_INIT_DATA(smps7),
332         PALMAS_REG_INIT_DATA(smps8),
333         PALMAS_REG_INIT_DATA(smps9),
334         PALMAS_REG_INIT_DATA(smps10),
335         PALMAS_REG_INIT_DATA(ldo1),
336         PALMAS_REG_INIT_DATA(ldo2),
337         PALMAS_REG_INIT_DATA(ldo3),
338         PALMAS_REG_INIT_DATA(ldo4),
339         PALMAS_REG_INIT_DATA(ldo5),
340         PALMAS_REG_INIT_DATA(ldo6),
341         PALMAS_REG_INIT_DATA(ldo7),
342         PALMAS_REG_INIT_DATA(ldo8),
343         PALMAS_REG_INIT_DATA(ldo9),
344         PALMAS_REG_INIT_DATA(ldoln),
345         PALMAS_REG_INIT_DATA(ldousb),
346 };
347
348 static int ac_online(void)
349 {
350         return 1;
351 }
352
353 static struct resource pluto_pda_resources[] = {
354         [0] = {
355                 .name   = "ac",
356         },
357 };
358
359 static struct pda_power_pdata pluto_pda_data = {
360         .is_ac_online   = ac_online,
361 };
362
363 static struct platform_device pluto_pda_power_device = {
364         .name           = "pda-power",
365         .id             = -1,
366         .resource       = pluto_pda_resources,
367         .num_resources  = ARRAY_SIZE(pluto_pda_resources),
368         .dev    = {
369                 .platform_data  = &pluto_pda_data,
370         },
371 };
372
373 /* Always ON /Battery regulator */
374 static struct regulator_consumer_supply fixed_reg_en_battery_supply[] = {
375                 REGULATOR_SUPPLY("vdd_sys_cam", NULL),
376                 REGULATOR_SUPPLY("vdd_sys_bl", NULL),
377                 REGULATOR_SUPPLY("vdd_sys_com", NULL),
378                 REGULATOR_SUPPLY("vdd_sys_gps", NULL),
379                 REGULATOR_SUPPLY("vdd_sys_bt", NULL),
380                 REGULATOR_SUPPLY("vdd_sys_audio", NULL),
381 };
382
383 static struct regulator_consumer_supply fixed_reg_en_vdd_1v8_cam_supply[] = {
384         REGULATOR_SUPPLY("vddio_cam_mb", NULL),
385         REGULATOR_SUPPLY("vdd_1v8_cam12", NULL),
386         REGULATOR_SUPPLY("vif", "2-0010"),
387         REGULATOR_SUPPLY("vif", "2-0036"),
388         REGULATOR_SUPPLY("vdd_i2c", "2-000e"),
389 };
390
391 static struct regulator_consumer_supply fixed_reg_en_vdd_1v2_cam_supply[] = {
392         REGULATOR_SUPPLY("vdd_1v2_cam", NULL),
393         REGULATOR_SUPPLY("vdig", "2-0010"),
394         REGULATOR_SUPPLY("vdig", "2-0036"),
395 };
396
397 static struct regulator_consumer_supply fixed_reg_en_avdd_usb3_1v05_supply[] = {
398         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
399         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
400         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-xhci"),
401 };
402
403 static struct regulator_consumer_supply fixed_reg_en_vdd_mmc_sdmmc3_supply[] = {
404         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
405 };
406
407 static struct regulator_consumer_supply fixed_reg_en_vdd_lcd_1v8_supply[] = {
408         REGULATOR_SUPPLY("vdd_lcd_1v8_s", NULL),
409 };
410
411 static struct regulator_consumer_supply fixed_reg_en_vdd_lcd_mmc_supply[] = {
412         REGULATOR_SUPPLY("vdd_lcd_mmc_s_f", NULL),
413 };
414
415 static struct regulator_consumer_supply fixed_reg_en_vdd_1v8_mic_supply[] = {
416         REGULATOR_SUPPLY("vdd_1v8_mic", NULL),
417 };
418
419 static struct regulator_consumer_supply fixed_reg_en_vdd_hdmi_5v0_supply[] = {
420         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
421 };
422
423 static struct regulator_consumer_supply fixed_reg_en_vpp_fuse_supply[] = {
424         REGULATOR_SUPPLY("vpp_fuse", NULL),
425         REGULATOR_SUPPLY("v_efuse", NULL),
426 };
427
428 /* Macro for defining fixed regulator sub device data */
429 #define FIXED_SUPPLY(_name) "fixed_reg_en"#_name
430 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,   \
431         _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts,  \
432         _sdelay)                                                        \
433         static struct regulator_init_data ri_data_##_var =              \
434         {                                                               \
435                 .supply_regulator = _in_supply,                         \
436                 .num_consumer_supplies =                                \
437                         ARRAY_SIZE(fixed_reg_en_##_name##_supply),      \
438                 .consumer_supplies = fixed_reg_en_##_name##_supply,     \
439                 .constraints = {                                        \
440                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
441                                         REGULATOR_MODE_STANDBY),        \
442                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
443                                         REGULATOR_CHANGE_STATUS |       \
444                                         REGULATOR_CHANGE_VOLTAGE),      \
445                         .always_on = _always_on,                        \
446                         .boot_on = _boot_on,                            \
447                 },                                                      \
448         };                                                              \
449         static struct fixed_voltage_config fixed_reg_en_##_var##_pdata = \
450         {                                                               \
451                 .supply_name = FIXED_SUPPLY(_name),                     \
452                 .microvolts = _millivolts * 1000,                       \
453                 .gpio = _gpio_nr,                                       \
454                 .gpio_is_open_drain = _open_drain,                      \
455                 .enable_high = _active_high,                            \
456                 .enabled_at_boot = _boot_state,                         \
457                 .init_data = &ri_data_##_var,                           \
458                 .startup_delay = _sdelay                                \
459         };                                                              \
460         static struct platform_device fixed_reg_en_##_var##_dev = {     \
461                 .name = "reg-fixed-voltage",                            \
462                 .id = _id,                                              \
463                 .dev = {                                                \
464                         .platform_data = &fixed_reg_en_##_var##_pdata,  \
465                 },                                                      \
466         }
467
468 FIXED_REG(0,    battery,        battery,
469         NULL,   0,      0,
470         -1,     false, true,    0,      3300,   0);
471
472 FIXED_REG(1,    vdd_1v8_cam,    vdd_1v8_cam,
473         palmas_rails(smps8),    0,      0,
474         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO1,  false, true,    0,      1800,
475         0);
476
477 FIXED_REG(2,    vdd_1v2_cam,    vdd_1v2_cam,
478         palmas_rails(smps7),    0,      0,
479         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO2,  false, true,    0,      1200,
480         0);
481
482 FIXED_REG(3,    avdd_usb3_1v05, avdd_usb3_1v05,
483         palmas_rails(smps8),    0,      0,
484         TEGRA_GPIO_PK5, false,  true,   0,      1050,   0);
485
486 FIXED_REG(4,    vdd_mmc_sdmmc3, vdd_mmc_sdmmc3,
487         palmas_rails(smps9),    0,      0,
488         TEGRA_GPIO_PK1, false,  true,   0,      3300,   0);
489
490 FIXED_REG(5,    vdd_lcd_1v8,    vdd_lcd_1v8,
491         palmas_rails(smps8),    0,      0,
492         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO4,  false,  true,   0,      1800,
493         0);
494
495 FIXED_REG(6,    vdd_lcd_mmc,    vdd_lcd_mmc,
496         palmas_rails(smps9),    0,      0,
497         TEGRA_GPIO_PI4, false,  true,   0,      1800,   0);
498
499 FIXED_REG(7,    vdd_1v8_mic,    vdd_1v8_mic,
500         palmas_rails(smps8),    0,      0,
501         -1,     false,  true,   0,      1800,   0);
502
503 FIXED_REG(8,    vdd_hdmi_5v0,   vdd_hdmi_5v0,
504         NULL,   0,      0,
505         TEGRA_GPIO_PK6, true,   true,   0,      5000,   5000);
506
507 FIXED_REG(9,    vpp_fuse,       vpp_fuse,
508         palmas_rails(smps8),    0,      0,
509         TEGRA_GPIO_PX4, false,  true,   0,      1800,   0);
510
511 /*
512  * Creating the fixed regulator device tables
513  */
514 #define ADD_FIXED_REG(_name)    (&fixed_reg_en_##_name##_dev)
515
516 #define E1580_COMMON_FIXED_REG                  \
517         ADD_FIXED_REG(battery),                 \
518         ADD_FIXED_REG(vdd_1v8_cam),             \
519         ADD_FIXED_REG(vdd_1v2_cam),             \
520         ADD_FIXED_REG(avdd_usb3_1v05),          \
521         ADD_FIXED_REG(vdd_mmc_sdmmc3),          \
522         ADD_FIXED_REG(vdd_lcd_1v8),             \
523         ADD_FIXED_REG(vdd_lcd_mmc),             \
524         ADD_FIXED_REG(vdd_1v8_mic),             \
525         ADD_FIXED_REG(vdd_hdmi_5v0),
526
527 #define E1580_T114_FIXED_REG                    \
528         ADD_FIXED_REG(vpp_fuse),
529
530 /* Gpio switch regulator platform data for Pluto E1580 */
531 static struct platform_device *pfixed_reg_devs[] = {
532         E1580_COMMON_FIXED_REG
533         E1580_T114_FIXED_REG
534 };
535
536 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
537 /* board parameters for cpu dfll */
538 static struct tegra_cl_dvfs_cfg_param pluto_cl_dvfs_param = {
539         .sample_rate = 12500,
540
541         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
542         .cf = 10,
543         .ci = 0,
544         .cg = 2,
545
546         .droop_cut_value = 0xF,
547         .droop_restore_ramp = 0x0,
548         .scale_out_ramp = 0x0,
549 };
550 #endif
551
552 /* palmas: fixed 10mV steps from 600mV to 1400mV, with offset 0x10 */
553 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
554 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
555 static inline void fill_reg_map(void)
556 {
557         int i;
558         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
559                 pmu_cpu_vdd_map[i].reg_value = i + 0x10;
560                 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
561         }
562 }
563
564 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
565 static struct tegra_cl_dvfs_platform_data pluto_cl_dvfs_data = {
566         .dfll_clk_name = "dfll_cpu",
567         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
568         .u.pmu_i2c = {
569                 .fs_rate = 400000,
570                 .slave_addr = 0xb0,
571                 .reg = 0x23,
572         },
573         .vdd_map = pmu_cpu_vdd_map,
574         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
575
576         .cfg_param = &pluto_cl_dvfs_param,
577 };
578
579 static int __init pluto_cl_dvfs_init(void)
580 {
581         fill_reg_map();
582         tegra_cl_dvfs_device.dev.platform_data = &pluto_cl_dvfs_data;
583         platform_device_register(&tegra_cl_dvfs_device);
584
585         return 0;
586 }
587 #endif
588
589 static struct palmas_dvfs_init_data palmas_dvfs_idata[] = {
590         {
591                 .en_pwm = false,
592         }, {
593                 .en_pwm = true,
594                 .ext_ctrl = PALMAS_EXT_CONTROL_ENABLE2,
595                 .reg_id = PALMAS_REG_SMPS6,
596                 .step_20mV = true,
597                 .base_voltage_uV = 500000,
598                 .max_voltage_uV = 1100000,
599         },
600 };
601
602 static struct palmas_pmic_platform_data pmic_platform = {
603         .enable_ldo8_tracking = true,
604         .disabe_ldo8_tracking_suspend = true,
605         .disable_smps10_boost_suspend = true,
606         .dvfs_init_data = palmas_dvfs_idata,
607         .dvfs_init_data_size = ARRAY_SIZE(palmas_dvfs_idata),
608 };
609
610 struct palmas_clk32k_init_data palmas_clk32k_idata[] = {
611         {
612                 .clk32k_id = PALMAS_CLOCK32KG,
613                 .enable = true,
614         }, {
615                 .clk32k_id = PALMAS_CLOCK32KG_AUDIO,
616                 .enable = true,
617         },
618 };
619
620 static struct palmas_platform_data palmas_pdata = {
621         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
622         .irq_base = PALMAS_TEGRA_IRQ_BASE,
623         .pmic_pdata = &pmic_platform,
624         .mux_from_pdata = true,
625         .pad1 = 0,
626         .pad2 = (PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK &
627                         (1 << PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT)),
628         .pad3 = PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2,
629         .clk32k_init_data =  palmas_clk32k_idata,
630         .clk32k_init_data_size = ARRAY_SIZE(palmas_clk32k_idata),
631         .irq_type = IRQ_TYPE_LEVEL_HIGH,
632         .use_power_off = true,
633 };
634
635 static struct i2c_board_info palma_device[] = {
636         {
637                 I2C_BOARD_INFO("tps65913", 0x58),
638                 .irq            = INT_EXTERNAL_PMU,
639                 .platform_data  = &palmas_pdata,
640         },
641 };
642
643 int __init pluto_regulator_init(void)
644 {
645         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
646         u32 pmc_ctrl;
647         int i;
648
649 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
650         pluto_cl_dvfs_init();
651 #endif
652
653         /* TPS65913: Normal state of INT request line is LOW.
654          * configure the power management controller to trigger PMU
655          * interrupts when HIGH.
656          */
657         pmc_ctrl = readl(pmc + PMC_CTRL);
658         writel(pmc_ctrl & ~PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
659
660         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
661                 pmic_platform.reg_data[i] = pluto_reg_data[i];
662                 pmic_platform.reg_init[i] = pluto_reg_init[i];
663         }
664
665         platform_device_register(&pluto_pda_power_device);
666         i2c_register_board_info(4, palma_device,
667                         ARRAY_SIZE(palma_device));
668         return 0;
669 }
670
671 static int __init pluto_fixed_regulator_init(void)
672 {
673         if (!machine_is_tegra_pluto())
674                 return 0;
675
676         return platform_add_devices(pfixed_reg_devs,
677                         ARRAY_SIZE(pfixed_reg_devs));
678 }
679 subsys_initcall_sync(pluto_fixed_regulator_init);
680
681 static struct tegra_suspend_platform_data pluto_suspend_data = {
682         .cpu_timer      = 300,
683         .cpu_off_timer  = 300,
684         .suspend_mode   = TEGRA_SUSPEND_LP0,
685         .core_timer     = 0x157e,
686         .core_off_timer = 2000,
687         .corereq_high   = true,
688         .sysclkreq_high = true,
689         .min_residency_noncpu = 2000,
690         .min_residency_crail = 8000,
691 };
692
693 int __init pluto_suspend_init(void)
694 {
695         tegra_init_suspend(&pluto_suspend_data);
696         return 0;
697 }
698
699 int __init pluto_edp_init(void)
700 {
701         unsigned int regulator_mA;
702
703         regulator_mA = get_maximum_cpu_current_supported();
704         if (!regulator_mA)
705                 regulator_mA = 9000;
706
707         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
708         tegra_init_cpu_edp_limits(regulator_mA);
709
710         regulator_mA = get_maximum_core_current_supported();
711         if (!regulator_mA)
712                 regulator_mA = 4000;
713
714         pr_info("%s: core regulator %d mA\n", __func__, regulator_mA);
715         tegra_init_core_edp_limits(regulator_mA);
716
717         return 0;
718 }
719
720 static struct soctherm_platform_data pluto_soctherm_data = {
721         .therm = {
722                 [THERM_CPU] = {
723                         .zone_enable = true,
724                         .passive_delay = 1000,
725                         .num_trips = 3,
726                         .trips = {
727                                 {
728                                         .cdev_type = "tegra-balanced",
729                                         .trip_temp = 85000,
730                                         .trip_type = THERMAL_TRIP_PASSIVE,
731                                         .upper = THERMAL_NO_LIMIT,
732                                         .lower = THERMAL_NO_LIMIT,
733                                 },
734                                 {
735                                         .cdev_type = "tegra-heavy",
736                                         .trip_temp = 95000,
737                                         .trip_type = THERMAL_TRIP_HOT,
738                                         .upper = THERMAL_NO_LIMIT,
739                                         .lower = THERMAL_NO_LIMIT,
740                                 },
741                                 {
742                                         .cdev_type = "tegra-shutdown",
743                                         .trip_temp = 105000,
744                                         .trip_type = THERMAL_TRIP_CRITICAL,
745                                         .upper = THERMAL_NO_LIMIT,
746                                         .lower = THERMAL_NO_LIMIT,
747                                 },
748                         },
749                 },
750                 [THERM_GPU] = {
751                         .zone_enable = true,
752                 },
753                 [THERM_PLL] = {
754                         .zone_enable = true,
755                 },
756         },
757         .throttle = {
758                 [THROTTLE_HEAVY] = {
759                         .devs = {
760                                 [THROTTLE_DEV_CPU] = {
761                                         .enable = 1,
762                                 },
763                         },
764                 },
765         },
766 };
767
768 int __init pluto_soctherm_init(void)
769 {
770         return tegra11_soctherm_init(&pluto_soctherm_data);
771 }