ARM: tegra: pluto: Enable ext control for modem
[linux-2.6.git] / arch / arm / mach-tegra / board-pluto-power.c
1 /*
2  * arch/arm/mach-tegra/board-pluto-power.c
3  *
4  * Copyright (C) 2012 NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
24 #include <linux/io.h>
25
26 #include <mach/iomap.h>
27 #include <mach/irqs.h>
28 #include <linux/regulator/fixed.h>
29 #include <linux/mfd/palmas.h>
30 #include <linux/regulator/machine.h>
31
32 #include <asm/mach-types.h>
33
34 #include "pm.h"
35 #include "board.h"
36 #include "board-pluto.h"
37
38 #define PMC_CTRL                0x0
39 #define PMC_CTRL_INTR_LOW       (1 << 17)
40
41 /************************ Pluto based regulator ****************/
42 static struct regulator_consumer_supply palmas_smps123_supply[] = {
43         REGULATOR_SUPPLY("vdd_cpu", NULL),
44 };
45
46 static struct regulator_consumer_supply palmas_smps45_supply[] = {
47         REGULATOR_SUPPLY("vdd_core", NULL),
48 };
49
50 static struct regulator_consumer_supply palmas_smps6_supply[] = {
51         REGULATOR_SUPPLY("vdd_core_bb", NULL),
52 };
53
54 static struct regulator_consumer_supply palmas_smps7_supply[] = {
55         REGULATOR_SUPPLY("vddio_ddr", NULL),
56         REGULATOR_SUPPLY("vddio_lpddr3", NULL),
57         REGULATOR_SUPPLY("vcore2_lpddr3", NULL),
58         REGULATOR_SUPPLY("vcore_audio_1v2", NULL),
59 };
60
61 static struct regulator_consumer_supply palmas_smps8_supply[] = {
62         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
63         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
64         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
65         REGULATOR_SUPPLY("avdd_osc", NULL),
66         REGULATOR_SUPPLY("vddio_sys", NULL),
67         REGULATOR_SUPPLY("vddio_bb", NULL),
68         REGULATOR_SUPPLY("pwrdet_bb", NULL),
69         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
70         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
71         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
72         REGULATOR_SUPPLY("vdd_emmc", "sdhci-tegra.3"),
73         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
74         REGULATOR_SUPPLY("vddio_audio", NULL),
75         REGULATOR_SUPPLY("pwrdet_audio", NULL),
76         REGULATOR_SUPPLY("vddio_uart", NULL),
77         REGULATOR_SUPPLY("pwrdet_uart", NULL),
78         REGULATOR_SUPPLY("vddio_gmi", NULL),
79         REGULATOR_SUPPLY("pwrdet_nand", NULL),
80         REGULATOR_SUPPLY("vddio_cam", "tegra_camera"),
81         REGULATOR_SUPPLY("pwrdet_cam", NULL),
82         REGULATOR_SUPPLY("vdd_gps", NULL),
83         REGULATOR_SUPPLY("vdd_nfc", NULL),
84         REGULATOR_SUPPLY("vdd_sensor", NULL),
85         REGULATOR_SUPPLY("vdd_dtv", NULL),
86         REGULATOR_SUPPLY("vdd_bb", NULL),
87         REGULATOR_SUPPLY("vcore1_lpddr", NULL),
88         REGULATOR_SUPPLY("vcore_lpddr", NULL),
89         REGULATOR_SUPPLY("vddio_lpddr", NULL),
90         REGULATOR_SUPPLY("vdd_rf", NULL),
91         REGULATOR_SUPPLY("vdd_modem2", NULL),
92         REGULATOR_SUPPLY("vdd_dbg", NULL),
93         REGULATOR_SUPPLY("vdd_sim_1v8", NULL),
94         REGULATOR_SUPPLY("vdd_sim1a_1v8", NULL),
95         REGULATOR_SUPPLY("vdd_sim1b_1v8", NULL),
96         REGULATOR_SUPPLY("dvdd_audio", NULL),
97         REGULATOR_SUPPLY("avdd_audio", NULL),
98         REGULATOR_SUPPLY("vdd_com_1v8", NULL),
99         REGULATOR_SUPPLY("vdd_bt_1v8", NULL),
100         REGULATOR_SUPPLY("vdd_ts_1v8", NULL),
101         REGULATOR_SUPPLY("avdd_pll_bb", NULL),
102 };
103
104 static struct regulator_consumer_supply palmas_smps9_supply[] = {
105         REGULATOR_SUPPLY("vcore_emmc", NULL),
106         REGULATOR_SUPPLY("vdd_sim_mmc", NULL),
107         REGULATOR_SUPPLY("vdd_sim1a_mmc", NULL),
108         REGULATOR_SUPPLY("vdd_sim1b_mmc", NULL),
109 };
110
111 static struct regulator_consumer_supply palmas_smps10_supply[] = {
112         REGULATOR_SUPPLY("unused_smps10", NULL),
113         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
114         REGULATOR_SUPPLY("vdd_vbrtr", NULL),
115         REGULATOR_SUPPLY("vdd_lcd", NULL),
116 };
117
118 static struct regulator_consumer_supply palmas_ldo1_supply[] = {
119         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
120         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
121         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
122         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegra_camera"),
123         REGULATOR_SUPPLY("avdd_pllm", NULL),
124         REGULATOR_SUPPLY("avdd_pllu", NULL),
125         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
126         REGULATOR_SUPPLY("avdd_pllx", NULL),
127         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
128         REGULATOR_SUPPLY("avdd_plle", NULL),
129 };
130
131 static struct regulator_consumer_supply palmas_ldo2_supply[] = {
132         REGULATOR_SUPPLY("avdd_lcd", NULL),
133 };
134
135 static struct regulator_consumer_supply palmas_ldo3_supply[] = {
136         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
137         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
138         REGULATOR_SUPPLY("avdd_dsi_csi", "tegra_camera"),
139         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
140         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
141         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
142         REGULATOR_SUPPLY("vddio_hsic_bb", NULL),
143         REGULATOR_SUPPLY("vddio_hsic_modem2", NULL),
144 };
145
146 static struct regulator_consumer_supply palmas_ldo4_supply[] = {
147         REGULATOR_SUPPLY("vdd_spare", NULL),
148 };
149
150 static struct regulator_consumer_supply palmas_ldo5_supply[] = {
151         REGULATOR_SUPPLY("avdd_cam1", NULL),
152 };
153
154 static struct regulator_consumer_supply palmas_ldo6_supply[] = {
155         REGULATOR_SUPPLY("vdd_temp", NULL),
156         REGULATOR_SUPPLY("vdd_mb", NULL),
157         REGULATOR_SUPPLY("avdd_ts_3v0", NULL),
158         REGULATOR_SUPPLY("vdd_nfc_3v0", NULL),
159         REGULATOR_SUPPLY("vdd_irled", NULL),
160         REGULATOR_SUPPLY("vdd_sensor_3v0", NULL),
161         REGULATOR_SUPPLY("vdd_3v0_pm", NULL),
162         REGULATOR_SUPPLY("vaux_3v3", NULL),
163         REGULATOR_SUPPLY("vdd", "0-0044"),
164 };
165
166 static struct regulator_consumer_supply palmas_ldo7_supply[] = {
167         REGULATOR_SUPPLY("vdd_af_cam1", NULL),
168 };
169 static struct regulator_consumer_supply palmas_ldo8_supply[] = {
170         REGULATOR_SUPPLY("vdd_rtc", NULL),
171 };
172 static struct regulator_consumer_supply palmas_ldo9_supply[] = {
173         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
174         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
175 };
176 static struct regulator_consumer_supply palmas_ldoln_supply[] = {
177         REGULATOR_SUPPLY("avdd_cam2", NULL),
178 };
179
180 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
181         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
182         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
183         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
184         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
185         REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
186         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
187         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
188         REGULATOR_SUPPLY("pwrdet_hv", NULL),
189         REGULATOR_SUPPLY("vdd_dtv_3v3", NULL),
190
191 };
192
193 static struct regulator_consumer_supply palmas_regen1_supply[] = {
194         REGULATOR_SUPPLY("mic_ventral", NULL),
195 };
196
197 static struct regulator_consumer_supply palmas_regen2_supply[] = {
198         REGULATOR_SUPPLY("vdd_mic", NULL),
199 };
200
201 #define PALMAS_PDATA_INIT(_name, _minmv, _maxmv, _supply_reg, _always_on, \
202         _boot_on, _apply_uv)                                            \
203         static struct regulator_init_data reg_idata_##_name = {         \
204                 .constraints = {                                        \
205                         .name = palmas_rails(_name),                    \
206                         .min_uV = (_minmv)*1000,                        \
207                         .max_uV = (_maxmv)*1000,                        \
208                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
209                                         REGULATOR_MODE_STANDBY),        \
210                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
211                                         REGULATOR_CHANGE_STATUS |       \
212                                         REGULATOR_CHANGE_VOLTAGE),      \
213                         .always_on = _always_on,                        \
214                         .boot_on = _boot_on,                            \
215                         .apply_uV = _apply_uv,                          \
216                 },                                                      \
217                 .num_consumer_supplies =                                \
218                         ARRAY_SIZE(palmas_##_name##_supply),            \
219                 .consumer_supplies = palmas_##_name##_supply,           \
220                 .supply_regulator = _supply_reg,                        \
221         }
222
223 PALMAS_PDATA_INIT(smps123, 900,  1300, NULL, 0, 0, 0);
224 PALMAS_PDATA_INIT(smps45, 900,  1400, NULL, 0, 0, 0);
225 PALMAS_PDATA_INIT(smps6, 850,  850, NULL, 0, 0, 1);
226 PALMAS_PDATA_INIT(smps7, 1200,  1200, NULL, 0, 0, 1);
227 PALMAS_PDATA_INIT(smps8, 1800,  1800, NULL, 0, 1, 1);
228 PALMAS_PDATA_INIT(smps9, 2800,  2800, NULL, 0, 0, 1);
229 PALMAS_PDATA_INIT(smps10, 5000,  5000, NULL, 0, 0, 0);
230 PALMAS_PDATA_INIT(ldo1, 1050,  1050, palmas_rails(smps7), 0, 0, 1);
231 PALMAS_PDATA_INIT(ldo2, 2800,  3000, NULL, 0, 0, 0);
232 PALMAS_PDATA_INIT(ldo3, 1200,  1200, palmas_rails(smps8), 0, 0, 1);
233 PALMAS_PDATA_INIT(ldo4, 900,  3300, NULL, 0, 0, 0);
234 PALMAS_PDATA_INIT(ldo5, 2700,  2700, NULL, 0, 0, 1);
235 PALMAS_PDATA_INIT(ldo6, 3000,  3000, NULL, 0, 0, 1);
236 PALMAS_PDATA_INIT(ldo7, 2800,  2800, NULL, 0, 0, 1);
237 PALMAS_PDATA_INIT(ldo8, 1150,  1150, NULL, 1, 1, 1);
238 PALMAS_PDATA_INIT(ldo9, 1800,  3300, palmas_rails(smps9), 0, 0, 1);
239 PALMAS_PDATA_INIT(ldoln, 2700, 2700, NULL, 0, 0, 1);
240 PALMAS_PDATA_INIT(ldousb, 3300,  3300, NULL, 0, 0, 1);
241 PALMAS_PDATA_INIT(regen1, 4300,  4300, NULL, 0, 0, 0);
242 PALMAS_PDATA_INIT(regen2, 4300,  4300, palmas_rails(smps8), 0, 0, 0);
243
244 #define PALMAS_REG_PDATA(_sname) &reg_idata_##_sname
245
246 static struct regulator_init_data *pluto_reg_data[] = {
247         NULL,
248         PALMAS_REG_PDATA(smps123),
249         NULL,
250         PALMAS_REG_PDATA(smps45),
251         NULL,
252         PALMAS_REG_PDATA(smps6),
253         PALMAS_REG_PDATA(smps7),
254         PALMAS_REG_PDATA(smps8),
255         PALMAS_REG_PDATA(smps9),
256         PALMAS_REG_PDATA(smps10),
257         PALMAS_REG_PDATA(ldo1),
258         PALMAS_REG_PDATA(ldo2),
259         PALMAS_REG_PDATA(ldo3),
260         PALMAS_REG_PDATA(ldo4),
261         PALMAS_REG_PDATA(ldo5),
262         PALMAS_REG_PDATA(ldo6),
263         PALMAS_REG_PDATA(ldo7),
264         PALMAS_REG_PDATA(ldo8),
265         PALMAS_REG_PDATA(ldo9),
266         PALMAS_REG_PDATA(ldoln),
267         PALMAS_REG_PDATA(ldousb),
268         PALMAS_REG_PDATA(regen1),
269         PALMAS_REG_PDATA(regen2),
270         NULL,
271         NULL,
272         NULL,
273 };
274
275 #define PALMAS_REG_INIT(_name, _warm_reset, _roof_floor, _mode_sleep,   \
276                 _tstep, _vsel)                                          \
277         static struct palmas_reg_init reg_init_data_##_name = {         \
278                 .warm_reset = _warm_reset,                              \
279                 .roof_floor =   _roof_floor,                            \
280                 .mode_sleep = _mode_sleep,              \
281                 .tstep = _tstep,                        \
282                 .vsel = _vsel,          \
283         }
284
285 PALMAS_REG_INIT(smps12, 0, 0, 0, 0, 0);
286 PALMAS_REG_INIT(smps123, 0, PALMAS_EXT_CONTROL_ENABLE1, 0, 0, 0);
287 PALMAS_REG_INIT(smps3, 0, 0, 0, 0, 0);
288 PALMAS_REG_INIT(smps45, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
289 PALMAS_REG_INIT(smps457, 0, 0, 0, 0, 0);
290 PALMAS_REG_INIT(smps6, 0, PALMAS_EXT_CONTROL_ENABLE2, 0, 0, 0);
291 PALMAS_REG_INIT(smps7, 0, 0, 0, 0, 0);
292 PALMAS_REG_INIT(smps8, 0, 0, 0, 0, 0);
293 PALMAS_REG_INIT(smps9, 0, 0, 0, 0, 0);
294 PALMAS_REG_INIT(smps10, 0, 0, 0, 0, 0);
295 PALMAS_REG_INIT(ldo1, 0, 0, 0, 0, 0);
296 PALMAS_REG_INIT(ldo2, 0, 0, 0, 0, 0);
297 PALMAS_REG_INIT(ldo3, 0, 0, 0, 0, 0);
298 PALMAS_REG_INIT(ldo4, 0, 0, 0, 0, 0);
299 PALMAS_REG_INIT(ldo5, 0, 0, 0, 0, 0);
300 PALMAS_REG_INIT(ldo6, 0, 0, 0, 0, 0);
301 PALMAS_REG_INIT(ldo7, 0, 0, 0, 0, 0);
302 PALMAS_REG_INIT(ldo8, 0, 0, 0, 0, 0);
303 PALMAS_REG_INIT(ldo9, 0, 0, 0, 0, 0);
304 PALMAS_REG_INIT(ldoln, 0, 0, 0, 0, 0);
305 PALMAS_REG_INIT(ldousb, 0, 0, 0, 0, 0);
306
307 #define PALMAS_REG_INIT_DATA(_sname) &reg_init_data_##_sname
308 static struct palmas_reg_init *pluto_reg_init[] = {
309         PALMAS_REG_INIT_DATA(smps12),
310         PALMAS_REG_INIT_DATA(smps123),
311         PALMAS_REG_INIT_DATA(smps3),
312         PALMAS_REG_INIT_DATA(smps45),
313         PALMAS_REG_INIT_DATA(smps457),
314         PALMAS_REG_INIT_DATA(smps6),
315         PALMAS_REG_INIT_DATA(smps7),
316         PALMAS_REG_INIT_DATA(smps8),
317         PALMAS_REG_INIT_DATA(smps9),
318         PALMAS_REG_INIT_DATA(smps10),
319         PALMAS_REG_INIT_DATA(ldo1),
320         PALMAS_REG_INIT_DATA(ldo2),
321         PALMAS_REG_INIT_DATA(ldo3),
322         PALMAS_REG_INIT_DATA(ldo4),
323         PALMAS_REG_INIT_DATA(ldo5),
324         PALMAS_REG_INIT_DATA(ldo6),
325         PALMAS_REG_INIT_DATA(ldo7),
326         PALMAS_REG_INIT_DATA(ldo8),
327         PALMAS_REG_INIT_DATA(ldo9),
328         PALMAS_REG_INIT_DATA(ldoln),
329         PALMAS_REG_INIT_DATA(ldousb),
330 };
331
332 static int ac_online(void)
333 {
334         return 1;
335 }
336
337 static struct resource pluto_pda_resources[] = {
338         [0] = {
339                 .name   = "ac",
340         },
341 };
342
343 static struct pda_power_pdata pluto_pda_data = {
344         .is_ac_online   = ac_online,
345 };
346
347 static struct platform_device pluto_pda_power_device = {
348         .name           = "pda-power",
349         .id             = -1,
350         .resource       = pluto_pda_resources,
351         .num_resources  = ARRAY_SIZE(pluto_pda_resources),
352         .dev    = {
353                 .platform_data  = &pluto_pda_data,
354         },
355 };
356
357 /* Always ON /Battery regulator */
358 static struct regulator_consumer_supply fixed_reg_en_battery_supply[] = {
359                 REGULATOR_SUPPLY("vdd_sys_cam", NULL),
360                 REGULATOR_SUPPLY("vdd_sys_bl", NULL),
361                 REGULATOR_SUPPLY("vdd_sys_com", NULL),
362                 REGULATOR_SUPPLY("vdd_sys_gps", NULL),
363                 REGULATOR_SUPPLY("vdd_sys_bt", NULL),
364 };
365
366 static struct regulator_consumer_supply fixed_reg_en_vdd_1v8_cam_supply[] = {
367         REGULATOR_SUPPLY("vddio_cam_mb", NULL),
368         REGULATOR_SUPPLY("vdd_1v8_cam12", NULL),
369 };
370
371 static struct regulator_consumer_supply fixed_reg_en_vdd_1v2_cam_supply[] = {
372         REGULATOR_SUPPLY("vdd_1v2_cam", NULL),
373 };
374
375 static struct regulator_consumer_supply fixed_reg_en_avdd_usb3_1v05_supply[] = {
376         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
377         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
378 };
379
380 static struct regulator_consumer_supply fixed_reg_en_vdd_mmc_sdmmc3_supply[] = {
381         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
382 };
383
384 static struct regulator_consumer_supply fixed_reg_en_vdd_lcd_1v8_supply[] = {
385         REGULATOR_SUPPLY("vdd_lcd_1v8_s", NULL),
386 };
387
388 static struct regulator_consumer_supply fixed_reg_en_vdd_lcd_mmc_supply[] = {
389         REGULATOR_SUPPLY("vdd_lcd_mmc_s_f", NULL),
390 };
391
392 static struct regulator_consumer_supply fixed_reg_en_vdd_1v8_mic_supply[] = {
393         REGULATOR_SUPPLY("unused_fixed_reg_en_vdd_1v8_mic", NULL),
394 };
395
396 static struct regulator_consumer_supply fixed_reg_en_vdd_hdmi_5v0_supply[] = {
397         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
398 };
399
400 static struct regulator_consumer_supply fixed_reg_en_vpp_fuse_supply[] = {
401         REGULATOR_SUPPLY("vpp_fuse", NULL),
402         REGULATOR_SUPPLY("v_efuse", NULL),
403 };
404
405 /* Macro for defining fixed regulator sub device data */
406 #define FIXED_SUPPLY(_name) "fixed_reg_en"#_name
407 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,   \
408         _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts)  \
409         static struct regulator_init_data ri_data_##_var =              \
410         {                                                               \
411                 .supply_regulator = _in_supply,                         \
412                 .num_consumer_supplies =                                \
413                         ARRAY_SIZE(fixed_reg_en_##_name##_supply),      \
414                 .consumer_supplies = fixed_reg_en_##_name##_supply,     \
415                 .constraints = {                                        \
416                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
417                                         REGULATOR_MODE_STANDBY),        \
418                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
419                                         REGULATOR_CHANGE_STATUS |       \
420                                         REGULATOR_CHANGE_VOLTAGE),      \
421                         .always_on = _always_on,                        \
422                         .boot_on = _boot_on,                            \
423                 },                                                      \
424         };                                                              \
425         static struct fixed_voltage_config fixed_reg_en_##_var##_pdata = \
426         {                                                               \
427                 .supply_name = FIXED_SUPPLY(_name),                     \
428                 .microvolts = _millivolts * 1000,                       \
429                 .gpio = _gpio_nr,                                       \
430                 .gpio_is_open_drain = _open_drain,                      \
431                 .enable_high = _active_high,                            \
432                 .enabled_at_boot = _boot_state,                         \
433                 .init_data = &ri_data_##_var,                           \
434         };                                                              \
435         static struct platform_device fixed_reg_en_##_var##_dev = {     \
436                 .name = "reg-fixed-voltage",                            \
437                 .id = _id,                                              \
438                 .dev = {                                                \
439                         .platform_data = &fixed_reg_en_##_var##_pdata,  \
440                 },                                                      \
441         }
442
443 FIXED_REG(0,    battery,        battery,
444         NULL,   0,      0,
445         -1,     false, true,    0,      3300);
446
447 FIXED_REG(1,    vdd_1v8_cam,    vdd_1v8_cam,
448         palmas_rails(smps8),    0,      0,
449         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO1,  false, true,    0,      1800);
450
451 FIXED_REG(2,    vdd_1v2_cam,    vdd_1v2_cam,
452         palmas_rails(smps7),    0,      0,
453         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO2,  false, true,    0,      1200);
454
455 FIXED_REG(3,    avdd_usb3_1v05, avdd_usb3_1v05,
456         palmas_rails(smps8),    0,      0,
457         TEGRA_GPIO_PK5, false,  true,   0,      1050);
458
459 FIXED_REG(4,    vdd_mmc_sdmmc3, vdd_mmc_sdmmc3,
460         palmas_rails(smps9),    0,      0,
461         TEGRA_GPIO_PK1, false,  true,   0,      3300);
462
463 FIXED_REG(5,    vdd_lcd_1v8,    vdd_lcd_1v8,
464         palmas_rails(smps8),    0,      0,
465         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO4,  false,  true,   0,      1800);
466
467 FIXED_REG(6,    vdd_lcd_mmc,    vdd_lcd_mmc,
468         palmas_rails(smps9),    0,      0,
469         TEGRA_GPIO_PI4, false,  true,   0,      1800);
470
471 FIXED_REG(7,    vdd_1v8_mic,    vdd_1v8_mic,
472         palmas_rails(smps8),    0,      0,
473         -1,     false,  true,   0,      1800);
474
475 FIXED_REG(8,    vdd_hdmi_5v0,   vdd_hdmi_5v0,
476         NULL,   0,      0,
477         TEGRA_GPIO_PK6, true,   true,   0,      5000);
478
479 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
480 FIXED_REG(9,    vpp_fuse,       vpp_fuse,
481         palmas_rails(smps8),    0,      0,
482         TEGRA_GPIO_PX4, false,  true,   0,      1800);
483 #else
484 FIXED_REG(9,    vpp_fuse,       vpp_fuse,
485         palmas_rails(smps8),    0,      0,
486         TEGRA_GPIO_PX0, false,  true,   0,      1800);
487 #endif
488
489 /*
490  * Creating the fixed regulator device tables
491  */
492 #define ADD_FIXED_REG(_name)    (&fixed_reg_en_##_name##_dev)
493
494 #define E1580_COMMON_FIXED_REG                  \
495         ADD_FIXED_REG(battery),                 \
496         ADD_FIXED_REG(vdd_1v8_cam),             \
497         ADD_FIXED_REG(vdd_1v2_cam),             \
498         ADD_FIXED_REG(avdd_usb3_1v05),          \
499         ADD_FIXED_REG(vdd_mmc_sdmmc3),          \
500         ADD_FIXED_REG(vdd_lcd_1v8),             \
501         ADD_FIXED_REG(vdd_lcd_mmc),             \
502         ADD_FIXED_REG(vdd_1v8_mic),             \
503         ADD_FIXED_REG(vdd_hdmi_5v0),
504
505 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
506 #define E1580_T114_FIXED_REG                    \
507         ADD_FIXED_REG(vpp_fuse),
508 #endif
509
510 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
511 #define E1580_T30_FIXED_REG                     \
512         ADD_FIXED_REG(vpp_fuse),
513 #endif
514
515 /* Gpio switch regulator platform data for Pluto E1580 */
516 static struct platform_device *pfixed_reg_devs[] = {
517         E1580_COMMON_FIXED_REG
518 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
519         E1580_T114_FIXED_REG
520 #endif
521 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
522         E1580_T30_FIXED_REG
523 #endif
524 };
525
526 static struct palmas_pmic_platform_data pmic_platform = {
527         .reg_data = pluto_reg_data,
528         .reg_init = pluto_reg_init,
529         .enable_ldo8_tracking = true,
530 };
531
532 struct palmas_clk32k_init_data palmas_clk32k_idata[] = {
533         {
534                 .clk32k_id = PALMAS_CLOCK32KG,
535                 .enable = true,
536         }, {
537                 .clk32k_id = PALMAS_CLOCK32KG_AUDIO,
538                 .enable = true,
539         },
540 };
541
542 static struct palmas_platform_data palmas_pdata = {
543         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
544         .irq_base = PALMAS_TEGRA_IRQ_BASE,
545         .pmic_pdata = &pmic_platform,
546         .mux_from_pdata = true,
547         .pad1 = 0,
548         .pad2 = (PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK &
549                         (1 << PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT)),
550         .clk32k_init_data =  palmas_clk32k_idata,
551         .clk32k_init_data_size = ARRAY_SIZE(palmas_clk32k_idata),
552 };
553
554 static struct i2c_board_info palma_device[] = {
555         {
556                 I2C_BOARD_INFO("tps65913", 0x58),
557                 .irq            = INT_EXTERNAL_PMU,
558                 .platform_data  = &palmas_pdata,
559         },
560 };
561
562 int __init pluto_regulator_init(void)
563 {
564         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
565         u32 pmc_ctrl;
566
567         /* TPS65913: Normal state of INT request line is LOW.
568          * configure the power management controller to trigger PMU
569          * interrupts when HIGH.
570          */
571         pmc_ctrl = readl(pmc + PMC_CTRL);
572         writel(pmc_ctrl & ~PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
573
574         platform_device_register(&pluto_pda_power_device);
575         i2c_register_board_info(4, palma_device,
576                         ARRAY_SIZE(palma_device));
577         return 0;
578 }
579
580 static int __init pluto_fixed_regulator_init(void)
581 {
582         if (!machine_is_tegra_pluto())
583                 return 0;
584
585         return platform_add_devices(pfixed_reg_devs,
586                         ARRAY_SIZE(pfixed_reg_devs));
587 }
588 subsys_initcall_sync(pluto_fixed_regulator_init);
589
590 static struct tegra_suspend_platform_data pluto_suspend_data = {
591         .cpu_timer      = 2000,
592         .cpu_off_timer  = 2000,
593         .suspend_mode   = TEGRA_SUSPEND_LP0,
594         .core_timer     = 0x7e7e,
595         .core_off_timer = 2000,
596         .corereq_high   = false,
597         .sysclkreq_high = true,
598 };
599
600 int __init pluto_suspend_init(void)
601 {
602         tegra_init_suspend(&pluto_suspend_data);
603         return 0;
604 }
605