ARM: tegra: pluto/dalmore: power sequence updates
[linux-2.6.git] / arch / arm / mach-tegra / board-pluto-power.c
1 /*
2  * arch/arm/mach-tegra/board-pluto-power.c
3  *
4  * Copyright (C) 2012 NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
24 #include <linux/io.h>
25
26 #include <mach/iomap.h>
27 #include <mach/edp.h>
28 #include <mach/irqs.h>
29 #include <linux/regulator/fixed.h>
30 #include <linux/mfd/palmas.h>
31 #include <linux/regulator/machine.h>
32 #include <linux/irq.h>
33
34 #include <asm/mach-types.h>
35
36 #include "cpu-tegra.h"
37 #include "pm.h"
38 #include "board.h"
39 #include "board-pluto.h"
40 #include "tegra_cl_dvfs.h"
41 #include "devices.h"
42 #include "tegra11_soctherm.h"
43
44 #define PMC_CTRL                0x0
45 #define PMC_CTRL_INTR_LOW       (1 << 17)
46
47 /************************ Pluto based regulator ****************/
48 static struct regulator_consumer_supply palmas_smps123_supply[] = {
49         REGULATOR_SUPPLY("vdd_cpu", NULL),
50 };
51
52 static struct regulator_consumer_supply palmas_smps45_supply[] = {
53         REGULATOR_SUPPLY("vdd_core", NULL),
54 };
55
56 static struct regulator_consumer_supply palmas_smps6_supply[] = {
57         REGULATOR_SUPPLY("vdd_core_bb", NULL),
58 };
59
60 static struct regulator_consumer_supply palmas_smps7_supply[] = {
61         REGULATOR_SUPPLY("vddio_ddr", NULL),
62         REGULATOR_SUPPLY("vddio_lpddr3", NULL),
63         REGULATOR_SUPPLY("vcore2_lpddr3", NULL),
64         REGULATOR_SUPPLY("vcore_audio_1v2", NULL),
65 };
66
67 static struct regulator_consumer_supply palmas_smps8_supply[] = {
68         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
69         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
70         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
71         REGULATOR_SUPPLY("avdd_osc", NULL),
72         REGULATOR_SUPPLY("vddio_sys", NULL),
73         REGULATOR_SUPPLY("vddio_bb", NULL),
74         REGULATOR_SUPPLY("pwrdet_bb", NULL),
75         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
76         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
77         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
78         REGULATOR_SUPPLY("vdd_emmc", "sdhci-tegra.3"),
79         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
80         REGULATOR_SUPPLY("vddio_audio", NULL),
81         REGULATOR_SUPPLY("pwrdet_audio", NULL),
82         REGULATOR_SUPPLY("vddio_uart", NULL),
83         REGULATOR_SUPPLY("pwrdet_uart", NULL),
84         REGULATOR_SUPPLY("vddio_gmi", NULL),
85         REGULATOR_SUPPLY("pwrdet_nand", NULL),
86         REGULATOR_SUPPLY("vddio_cam", "tegra_camera"),
87         REGULATOR_SUPPLY("pwrdet_cam", NULL),
88         REGULATOR_SUPPLY("vdd_gps", NULL),
89         REGULATOR_SUPPLY("vdd_nfc", NULL),
90         REGULATOR_SUPPLY("vdd_sensor", NULL),
91         REGULATOR_SUPPLY("vdd_dtv", NULL),
92         REGULATOR_SUPPLY("vdd_bb", NULL),
93         REGULATOR_SUPPLY("vcore1_lpddr", NULL),
94         REGULATOR_SUPPLY("vcore_lpddr", NULL),
95         REGULATOR_SUPPLY("vddio_lpddr", NULL),
96         REGULATOR_SUPPLY("vdd_rf", NULL),
97         REGULATOR_SUPPLY("vdd_modem2", NULL),
98         REGULATOR_SUPPLY("vdd_dbg", NULL),
99         REGULATOR_SUPPLY("vdd_sim_1v8", NULL),
100         REGULATOR_SUPPLY("vdd_sim1a_1v8", NULL),
101         REGULATOR_SUPPLY("vdd_sim1b_1v8", NULL),
102         REGULATOR_SUPPLY("dvdd_audio", NULL),
103         REGULATOR_SUPPLY("avdd_audio", NULL),
104         REGULATOR_SUPPLY("vdd_com_1v8", NULL),
105         REGULATOR_SUPPLY("vdd_bt_1v8", NULL),
106         REGULATOR_SUPPLY("vdd_ts_1v8", NULL),
107         REGULATOR_SUPPLY("avdd_pll_bb", NULL),
108 };
109
110 static struct regulator_consumer_supply palmas_smps9_supply[] = {
111         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
112         REGULATOR_SUPPLY("vdd_sim_mmc", NULL),
113         REGULATOR_SUPPLY("vdd_sim1a_mmc", NULL),
114         REGULATOR_SUPPLY("vdd_sim1b_mmc", NULL),
115 };
116
117 static struct regulator_consumer_supply palmas_smps10_supply[] = {
118         REGULATOR_SUPPLY("unused_smps10", NULL),
119         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
120         REGULATOR_SUPPLY("vdd_vbrtr", NULL),
121         REGULATOR_SUPPLY("vdd_lcd", NULL),
122 };
123
124 static struct regulator_consumer_supply palmas_ldo1_supply[] = {
125         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
126         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
127         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
128         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegra_camera"),
129         REGULATOR_SUPPLY("avdd_pllm", NULL),
130         REGULATOR_SUPPLY("avdd_pllu", NULL),
131         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
132         REGULATOR_SUPPLY("avdd_pllx", NULL),
133         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
134         REGULATOR_SUPPLY("avdd_plle", NULL),
135 };
136
137 static struct regulator_consumer_supply palmas_ldo2_supply[] = {
138         REGULATOR_SUPPLY("avdd_lcd", NULL),
139 };
140
141 static struct regulator_consumer_supply palmas_ldo3_supply[] = {
142         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
143         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
144         REGULATOR_SUPPLY("avdd_dsi_csi", "tegra_camera"),
145         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
146         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
147         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
148         REGULATOR_SUPPLY("vddio_hsic_bb", NULL),
149         REGULATOR_SUPPLY("vddio_hsic_modem2", NULL),
150 };
151
152 static struct regulator_consumer_supply palmas_ldo4_supply[] = {
153         REGULATOR_SUPPLY("vdd_spare", NULL),
154 };
155
156 static struct regulator_consumer_supply palmas_ldo5_supply[] = {
157         REGULATOR_SUPPLY("avdd_cam1", NULL),
158         REGULATOR_SUPPLY("vana", "2-0010"),
159 };
160
161 static struct regulator_consumer_supply palmas_ldo6_supply[] = {
162         REGULATOR_SUPPLY("vdd_temp", NULL),
163         REGULATOR_SUPPLY("vdd_mb", NULL),
164         REGULATOR_SUPPLY("avdd_ts_3v0", NULL),
165         REGULATOR_SUPPLY("avdd_backlight_3v0", "1-004d"),
166         REGULATOR_SUPPLY("vdd_nfc_3v0", NULL),
167         REGULATOR_SUPPLY("vdd_irled", NULL),
168         REGULATOR_SUPPLY("vdd_sensor_3v0", NULL),
169         REGULATOR_SUPPLY("vdd_3v0_pm", NULL),
170         REGULATOR_SUPPLY("vaux_3v3", NULL),
171         REGULATOR_SUPPLY("vdd", "0-0044"),
172         REGULATOR_SUPPLY("vdd", "0-004c"),
173 };
174
175 static struct regulator_consumer_supply palmas_ldo7_supply[] = {
176         REGULATOR_SUPPLY("vdd_af_cam1", NULL),
177         REGULATOR_SUPPLY("vdd", "2-000e"),
178 };
179 static struct regulator_consumer_supply palmas_ldo8_supply[] = {
180         REGULATOR_SUPPLY("vdd_rtc", NULL),
181 };
182 static struct regulator_consumer_supply palmas_ldo9_supply[] = {
183         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
184         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
185 };
186 static struct regulator_consumer_supply palmas_ldoln_supply[] = {
187         REGULATOR_SUPPLY("avdd_cam2", NULL),
188         REGULATOR_SUPPLY("vana", "2-0036"),
189 };
190
191 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
192         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
193         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
194         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
195         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
196         REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
197         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
198         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
199         REGULATOR_SUPPLY("pwrdet_hv", NULL),
200         REGULATOR_SUPPLY("vdd_dtv_3v3", NULL),
201
202 };
203
204 static struct regulator_consumer_supply palmas_regen1_supply[] = {
205         REGULATOR_SUPPLY("mic_ventral", NULL),
206 };
207
208 static struct regulator_consumer_supply palmas_regen2_supply[] = {
209         REGULATOR_SUPPLY("vdd_mic", NULL),
210 };
211
212 #define PALMAS_PDATA_INIT(_name, _minmv, _maxmv, _supply_reg, _always_on, \
213         _boot_on, _apply_uv)                                            \
214         static struct regulator_init_data reg_idata_##_name = {         \
215                 .constraints = {                                        \
216                         .name = palmas_rails(_name),                    \
217                         .min_uV = (_minmv)*1000,                        \
218                         .max_uV = (_maxmv)*1000,                        \
219                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
220                                         REGULATOR_MODE_STANDBY),        \
221                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
222                                         REGULATOR_CHANGE_STATUS |       \
223                                         REGULATOR_CHANGE_VOLTAGE),      \
224                         .always_on = _always_on,                        \
225                         .boot_on = _boot_on,                            \
226                         .apply_uV = _apply_uv,                          \
227                 },                                                      \
228                 .num_consumer_supplies =                                \
229                         ARRAY_SIZE(palmas_##_name##_supply),            \
230                 .consumer_supplies = palmas_##_name##_supply,           \
231                 .supply_regulator = _supply_reg,                        \
232         }
233
234 PALMAS_PDATA_INIT(smps123, 900,  1300, NULL, 0, 0, 0);
235 PALMAS_PDATA_INIT(smps45, 900,  1400, NULL, 0, 0, 0);
236 PALMAS_PDATA_INIT(smps6, 1100,  1100, NULL, 0, 0, 1);
237 PALMAS_PDATA_INIT(smps7, 1200,  1200, NULL, 0, 0, 1);
238 PALMAS_PDATA_INIT(smps8, 1800,  1800, NULL, 0, 1, 1);
239 PALMAS_PDATA_INIT(smps9, 2800,  2800, NULL, 0, 0, 1);
240 PALMAS_PDATA_INIT(smps10, 5000,  5000, NULL, 0, 0, 0);
241 PALMAS_PDATA_INIT(ldo1, 1050,  1050, palmas_rails(smps7), 0, 0, 1);
242 PALMAS_PDATA_INIT(ldo2, 2800,  3000, NULL, 0, 0, 0);
243 PALMAS_PDATA_INIT(ldo3, 1200,  1200, palmas_rails(smps8), 0, 1, 1);
244 PALMAS_PDATA_INIT(ldo4, 900,  3300, NULL, 0, 0, 0);
245 PALMAS_PDATA_INIT(ldo5, 2700,  2700, NULL, 0, 0, 1);
246 PALMAS_PDATA_INIT(ldo6, 3000,  3000, NULL, 0, 0, 1);
247 PALMAS_PDATA_INIT(ldo7, 2800,  2800, NULL, 0, 0, 1);
248 PALMAS_PDATA_INIT(ldo8, 900,  900, NULL, 1, 1, 1);
249 PALMAS_PDATA_INIT(ldo9, 1800,  3300, palmas_rails(smps9), 0, 0, 1);
250 PALMAS_PDATA_INIT(ldoln, 2700, 2700, NULL, 0, 0, 1);
251 PALMAS_PDATA_INIT(ldousb, 3300,  3300, NULL, 0, 0, 1);
252 PALMAS_PDATA_INIT(regen1, 4300,  4300, NULL, 0, 0, 0);
253 PALMAS_PDATA_INIT(regen2, 4300,  4300, palmas_rails(smps8), 0, 0, 0);
254
255 #define PALMAS_REG_PDATA(_sname) &reg_idata_##_sname
256
257 static struct regulator_init_data *pluto_reg_data[PALMAS_NUM_REGS] = {
258         NULL,
259         PALMAS_REG_PDATA(smps123),
260         NULL,
261         PALMAS_REG_PDATA(smps45),
262         NULL,
263         PALMAS_REG_PDATA(smps6),
264         PALMAS_REG_PDATA(smps7),
265         PALMAS_REG_PDATA(smps8),
266         PALMAS_REG_PDATA(smps9),
267         PALMAS_REG_PDATA(smps10),
268         PALMAS_REG_PDATA(ldo1),
269         PALMAS_REG_PDATA(ldo2),
270         PALMAS_REG_PDATA(ldo3),
271         PALMAS_REG_PDATA(ldo4),
272         PALMAS_REG_PDATA(ldo5),
273         PALMAS_REG_PDATA(ldo6),
274         PALMAS_REG_PDATA(ldo7),
275         PALMAS_REG_PDATA(ldo8),
276         PALMAS_REG_PDATA(ldo9),
277         PALMAS_REG_PDATA(ldoln),
278         PALMAS_REG_PDATA(ldousb),
279         PALMAS_REG_PDATA(regen1),
280         PALMAS_REG_PDATA(regen2),
281         NULL,
282         NULL,
283         NULL,
284 };
285
286 #define PALMAS_REG_INIT(_name, _warm_reset, _roof_floor, _mode_sleep,   \
287                 _tstep, _vsel)                                          \
288         static struct palmas_reg_init reg_init_data_##_name = {         \
289                 .warm_reset = _warm_reset,                              \
290                 .roof_floor =   _roof_floor,                            \
291                 .mode_sleep = _mode_sleep,              \
292                 .tstep = _tstep,                        \
293                 .vsel = _vsel,          \
294         }
295
296 PALMAS_REG_INIT(smps12, 0, 0, 0, 0, 0);
297 PALMAS_REG_INIT(smps123, 0, PALMAS_EXT_CONTROL_ENABLE1, 0, 0, 0);
298 PALMAS_REG_INIT(smps3, 0, 0, 0, 0, 0);
299 PALMAS_REG_INIT(smps45, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
300 PALMAS_REG_INIT(smps457, 0, 0, 0, 0, 0);
301 PALMAS_REG_INIT(smps6, 0, PALMAS_EXT_CONTROL_ENABLE2, 0, 0, 0);
302 PALMAS_REG_INIT(smps7, 0, 0, 0, 0, 0);
303 PALMAS_REG_INIT(smps8, 0, 0, 0, 0, 0);
304 PALMAS_REG_INIT(smps9, 0, 0, 0, 0, 0);
305 PALMAS_REG_INIT(smps10, 0, 0, 0, 0, 0);
306 PALMAS_REG_INIT(ldo1, 0, 0, 0, 0, 0);
307 PALMAS_REG_INIT(ldo2, 0, 0, 0, 0, 0);
308 PALMAS_REG_INIT(ldo3, 0, 0, 0, 0, 0);
309 PALMAS_REG_INIT(ldo4, 0, 0, 0, 0, 0);
310 PALMAS_REG_INIT(ldo5, 0, 0, 0, 0, 0);
311 PALMAS_REG_INIT(ldo6, 0, 0, 0, 0, 0);
312 PALMAS_REG_INIT(ldo7, 0, 0, 0, 0, 0);
313 PALMAS_REG_INIT(ldo8, 0, 0, 0, 0, 0);
314 PALMAS_REG_INIT(ldo9, 0, 0, 0, 0, 0);
315 PALMAS_REG_INIT(ldoln, 0, 0, 0, 0, 0);
316 PALMAS_REG_INIT(ldousb, 0, 0, 0, 0, 0);
317
318 #define PALMAS_REG_INIT_DATA(_sname) &reg_init_data_##_sname
319 static struct palmas_reg_init *pluto_reg_init[PALMAS_NUM_REGS] = {
320         PALMAS_REG_INIT_DATA(smps12),
321         PALMAS_REG_INIT_DATA(smps123),
322         PALMAS_REG_INIT_DATA(smps3),
323         PALMAS_REG_INIT_DATA(smps45),
324         PALMAS_REG_INIT_DATA(smps457),
325         PALMAS_REG_INIT_DATA(smps6),
326         PALMAS_REG_INIT_DATA(smps7),
327         PALMAS_REG_INIT_DATA(smps8),
328         PALMAS_REG_INIT_DATA(smps9),
329         PALMAS_REG_INIT_DATA(smps10),
330         PALMAS_REG_INIT_DATA(ldo1),
331         PALMAS_REG_INIT_DATA(ldo2),
332         PALMAS_REG_INIT_DATA(ldo3),
333         PALMAS_REG_INIT_DATA(ldo4),
334         PALMAS_REG_INIT_DATA(ldo5),
335         PALMAS_REG_INIT_DATA(ldo6),
336         PALMAS_REG_INIT_DATA(ldo7),
337         PALMAS_REG_INIT_DATA(ldo8),
338         PALMAS_REG_INIT_DATA(ldo9),
339         PALMAS_REG_INIT_DATA(ldoln),
340         PALMAS_REG_INIT_DATA(ldousb),
341 };
342
343 static int ac_online(void)
344 {
345         return 1;
346 }
347
348 static struct resource pluto_pda_resources[] = {
349         [0] = {
350                 .name   = "ac",
351         },
352 };
353
354 static struct pda_power_pdata pluto_pda_data = {
355         .is_ac_online   = ac_online,
356 };
357
358 static struct platform_device pluto_pda_power_device = {
359         .name           = "pda-power",
360         .id             = -1,
361         .resource       = pluto_pda_resources,
362         .num_resources  = ARRAY_SIZE(pluto_pda_resources),
363         .dev    = {
364                 .platform_data  = &pluto_pda_data,
365         },
366 };
367
368 /* Always ON /Battery regulator */
369 static struct regulator_consumer_supply fixed_reg_en_battery_supply[] = {
370                 REGULATOR_SUPPLY("vdd_sys_cam", NULL),
371                 REGULATOR_SUPPLY("vdd_sys_bl", NULL),
372                 REGULATOR_SUPPLY("vdd_sys_com", NULL),
373                 REGULATOR_SUPPLY("vdd_sys_gps", NULL),
374                 REGULATOR_SUPPLY("vdd_sys_bt", NULL),
375 };
376
377 static struct regulator_consumer_supply fixed_reg_en_vdd_1v8_cam_supply[] = {
378         REGULATOR_SUPPLY("vddio_cam_mb", NULL),
379         REGULATOR_SUPPLY("vdd_1v8_cam12", NULL),
380         REGULATOR_SUPPLY("vif", "2-0010"),
381         REGULATOR_SUPPLY("vif", "2-0036"),
382         REGULATOR_SUPPLY("vdd_i2c", "2-000e"),
383 };
384
385 static struct regulator_consumer_supply fixed_reg_en_vdd_1v2_cam_supply[] = {
386         REGULATOR_SUPPLY("vdd_1v2_cam", NULL),
387         REGULATOR_SUPPLY("vdig", "2-0010"),
388         REGULATOR_SUPPLY("vdig", "2-0036"),
389 };
390
391 static struct regulator_consumer_supply fixed_reg_en_avdd_usb3_1v05_supply[] = {
392         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
393         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
394 };
395
396 static struct regulator_consumer_supply fixed_reg_en_vdd_mmc_sdmmc3_supply[] = {
397         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
398 };
399
400 static struct regulator_consumer_supply fixed_reg_en_vdd_lcd_1v8_supply[] = {
401         REGULATOR_SUPPLY("vdd_lcd_1v8_s", NULL),
402 };
403
404 static struct regulator_consumer_supply fixed_reg_en_vdd_lcd_mmc_supply[] = {
405         REGULATOR_SUPPLY("vdd_lcd_mmc_s_f", NULL),
406 };
407
408 static struct regulator_consumer_supply fixed_reg_en_vdd_1v8_mic_supply[] = {
409         REGULATOR_SUPPLY("vdd_1v8_mic", NULL),
410 };
411
412 static struct regulator_consumer_supply fixed_reg_en_vdd_hdmi_5v0_supply[] = {
413         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
414 };
415
416 static struct regulator_consumer_supply fixed_reg_en_vpp_fuse_supply[] = {
417         REGULATOR_SUPPLY("vpp_fuse", NULL),
418         REGULATOR_SUPPLY("v_efuse", NULL),
419 };
420
421 /* Macro for defining fixed regulator sub device data */
422 #define FIXED_SUPPLY(_name) "fixed_reg_en"#_name
423 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,   \
424         _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts,  \
425         _sdelay)                                                        \
426         static struct regulator_init_data ri_data_##_var =              \
427         {                                                               \
428                 .supply_regulator = _in_supply,                         \
429                 .num_consumer_supplies =                                \
430                         ARRAY_SIZE(fixed_reg_en_##_name##_supply),      \
431                 .consumer_supplies = fixed_reg_en_##_name##_supply,     \
432                 .constraints = {                                        \
433                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
434                                         REGULATOR_MODE_STANDBY),        \
435                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
436                                         REGULATOR_CHANGE_STATUS |       \
437                                         REGULATOR_CHANGE_VOLTAGE),      \
438                         .always_on = _always_on,                        \
439                         .boot_on = _boot_on,                            \
440                 },                                                      \
441         };                                                              \
442         static struct fixed_voltage_config fixed_reg_en_##_var##_pdata = \
443         {                                                               \
444                 .supply_name = FIXED_SUPPLY(_name),                     \
445                 .microvolts = _millivolts * 1000,                       \
446                 .gpio = _gpio_nr,                                       \
447                 .gpio_is_open_drain = _open_drain,                      \
448                 .enable_high = _active_high,                            \
449                 .enabled_at_boot = _boot_state,                         \
450                 .init_data = &ri_data_##_var,                           \
451                 .startup_delay = _sdelay                                \
452         };                                                              \
453         static struct platform_device fixed_reg_en_##_var##_dev = {     \
454                 .name = "reg-fixed-voltage",                            \
455                 .id = _id,                                              \
456                 .dev = {                                                \
457                         .platform_data = &fixed_reg_en_##_var##_pdata,  \
458                 },                                                      \
459         }
460
461 FIXED_REG(0,    battery,        battery,
462         NULL,   0,      0,
463         -1,     false, true,    0,      3300,   0);
464
465 FIXED_REG(1,    vdd_1v8_cam,    vdd_1v8_cam,
466         palmas_rails(smps8),    0,      0,
467         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO1,  false, true,    0,      1800,
468         0);
469
470 FIXED_REG(2,    vdd_1v2_cam,    vdd_1v2_cam,
471         palmas_rails(smps7),    0,      0,
472         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO2,  false, true,    0,      1200,
473         0);
474
475 FIXED_REG(3,    avdd_usb3_1v05, avdd_usb3_1v05,
476         palmas_rails(smps8),    0,      0,
477         TEGRA_GPIO_PK5, false,  true,   0,      1050,   0);
478
479 FIXED_REG(4,    vdd_mmc_sdmmc3, vdd_mmc_sdmmc3,
480         palmas_rails(smps9),    0,      0,
481         TEGRA_GPIO_PK1, false,  true,   0,      3300,   0);
482
483 FIXED_REG(5,    vdd_lcd_1v8,    vdd_lcd_1v8,
484         palmas_rails(smps8),    0,      0,
485         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO4,  false,  true,   0,      1800,
486         0);
487
488 FIXED_REG(6,    vdd_lcd_mmc,    vdd_lcd_mmc,
489         palmas_rails(smps9),    0,      0,
490         TEGRA_GPIO_PI4, false,  true,   0,      1800,   0);
491
492 FIXED_REG(7,    vdd_1v8_mic,    vdd_1v8_mic,
493         palmas_rails(smps8),    0,      0,
494         -1,     false,  true,   0,      1800,   0);
495
496 FIXED_REG(8,    vdd_hdmi_5v0,   vdd_hdmi_5v0,
497         NULL,   0,      0,
498         TEGRA_GPIO_PK6, true,   true,   0,      5000,   5000);
499
500 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
501 FIXED_REG(9,    vpp_fuse,       vpp_fuse,
502         palmas_rails(smps8),    0,      0,
503         TEGRA_GPIO_PX4, false,  true,   0,      1800,   0);
504 #else
505 FIXED_REG(9,    vpp_fuse,       vpp_fuse,
506         palmas_rails(smps8),    0,      0,
507         TEGRA_GPIO_PX0, false,  true,   0,      1800,   0);
508 #endif
509
510 /*
511  * Creating the fixed regulator device tables
512  */
513 #define ADD_FIXED_REG(_name)    (&fixed_reg_en_##_name##_dev)
514
515 #define E1580_COMMON_FIXED_REG                  \
516         ADD_FIXED_REG(battery),                 \
517         ADD_FIXED_REG(vdd_1v8_cam),             \
518         ADD_FIXED_REG(vdd_1v2_cam),             \
519         ADD_FIXED_REG(avdd_usb3_1v05),          \
520         ADD_FIXED_REG(vdd_mmc_sdmmc3),          \
521         ADD_FIXED_REG(vdd_lcd_1v8),             \
522         ADD_FIXED_REG(vdd_lcd_mmc),             \
523         ADD_FIXED_REG(vdd_1v8_mic),             \
524         ADD_FIXED_REG(vdd_hdmi_5v0),
525
526 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
527 #define E1580_T114_FIXED_REG                    \
528         ADD_FIXED_REG(vpp_fuse),
529 #endif
530
531 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
532 #define E1580_T30_FIXED_REG                     \
533         ADD_FIXED_REG(vpp_fuse),
534 #endif
535
536 /* Gpio switch regulator platform data for Pluto E1580 */
537 static struct platform_device *pfixed_reg_devs[] = {
538         E1580_COMMON_FIXED_REG
539 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
540         E1580_T114_FIXED_REG
541 #endif
542 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
543         E1580_T30_FIXED_REG
544 #endif
545 };
546
547 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
548 /* board parameters for cpu dfll */
549 static struct tegra_cl_dvfs_cfg_param pluto_cl_dvfs_param = {
550         .sample_rate = 12500,
551
552         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
553         .cf = 10,
554         .ci = 0,
555         .cg = 2,
556
557         .droop_cut_value = 0xF,
558         .droop_restore_ramp = 0x0,
559         .scale_out_ramp = 0x0,
560 };
561 #endif
562
563 /* palmas: fixed 10mV steps from 600mV to 1400mV, with offset 0x10 */
564 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
565 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
566 static inline void fill_reg_map(void)
567 {
568         int i;
569         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
570                 pmu_cpu_vdd_map[i].reg_value = i + 0x10;
571                 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
572         }
573 }
574
575 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
576 static struct tegra_cl_dvfs_platform_data pluto_cl_dvfs_data = {
577         .dfll_clk_name = "dfll_cpu",
578         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
579         .u.pmu_i2c = {
580                 .fs_rate = 400000,
581                 .slave_addr = 0xb0,
582                 .reg = 0x23,
583         },
584         .vdd_map = pmu_cpu_vdd_map,
585         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
586
587         .cfg_param = &pluto_cl_dvfs_param,
588 };
589
590 static int __init pluto_cl_dvfs_init(void)
591 {
592         fill_reg_map();
593         tegra_cl_dvfs_device.dev.platform_data = &pluto_cl_dvfs_data;
594         platform_device_register(&tegra_cl_dvfs_device);
595
596         return 0;
597 }
598 #endif
599
600 static struct palmas_pmic_platform_data pmic_platform = {
601         .enable_ldo8_tracking = true,
602         .disabe_ldo8_tracking_suspend = true,
603 };
604
605 struct palmas_clk32k_init_data palmas_clk32k_idata[] = {
606         {
607                 .clk32k_id = PALMAS_CLOCK32KG,
608                 .enable = true,
609         }, {
610                 .clk32k_id = PALMAS_CLOCK32KG_AUDIO,
611                 .enable = true,
612         },
613 };
614
615 static struct palmas_platform_data palmas_pdata = {
616         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
617         .irq_base = PALMAS_TEGRA_IRQ_BASE,
618         .pmic_pdata = &pmic_platform,
619         .mux_from_pdata = true,
620         .pad1 = 0,
621         .pad2 = (PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK &
622                         (1 << PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT)),
623         .clk32k_init_data =  palmas_clk32k_idata,
624         .clk32k_init_data_size = ARRAY_SIZE(palmas_clk32k_idata),
625         .irq_type = IRQ_TYPE_LEVEL_HIGH,
626 };
627
628 static struct i2c_board_info palma_device[] = {
629         {
630                 I2C_BOARD_INFO("tps65913", 0x58),
631                 .irq            = INT_EXTERNAL_PMU,
632                 .platform_data  = &palmas_pdata,
633         },
634 };
635
636 int __init pluto_regulator_init(void)
637 {
638         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
639         u32 pmc_ctrl;
640         int i;
641
642 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
643         pluto_cl_dvfs_init();
644 #endif
645
646         /* TPS65913: Normal state of INT request line is LOW.
647          * configure the power management controller to trigger PMU
648          * interrupts when HIGH.
649          */
650         pmc_ctrl = readl(pmc + PMC_CTRL);
651         writel(pmc_ctrl & ~PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
652
653         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
654                 pmic_platform.reg_data[i] = pluto_reg_data[i];
655                 pmic_platform.reg_init[i] = pluto_reg_init[i];
656         }
657
658         platform_device_register(&pluto_pda_power_device);
659         i2c_register_board_info(4, palma_device,
660                         ARRAY_SIZE(palma_device));
661         return 0;
662 }
663
664 static int __init pluto_fixed_regulator_init(void)
665 {
666         if (!machine_is_tegra_pluto())
667                 return 0;
668
669         return platform_add_devices(pfixed_reg_devs,
670                         ARRAY_SIZE(pfixed_reg_devs));
671 }
672 subsys_initcall_sync(pluto_fixed_regulator_init);
673
674 static struct tegra_suspend_platform_data pluto_suspend_data = {
675         .cpu_timer      = 300,
676         .cpu_off_timer  = 300,
677         .suspend_mode   = TEGRA_SUSPEND_LP0,
678         .core_timer     = 0x157e,
679         .core_off_timer = 2000,
680         .corereq_high   = true,
681         .sysclkreq_high = true,
682         .min_residency_noncpu = 600,
683         .min_residency_crail = 1000,
684 };
685
686 int __init pluto_suspend_init(void)
687 {
688         tegra_init_suspend(&pluto_suspend_data);
689         return 0;
690 }
691
692 int __init pluto_edp_init(void)
693 {
694 #ifdef CONFIG_TEGRA_EDP_LIMITS
695         unsigned int regulator_mA;
696
697         regulator_mA = get_maximum_cpu_current_supported();
698         if (!regulator_mA)
699                 regulator_mA = 9000;
700
701         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
702
703         tegra_init_cpu_edp_limits(regulator_mA);
704 #endif
705         return 0;
706 }
707
708 static struct soctherm_platform_data pluto_soctherm_data = {
709         .soctherm_clk_rate = 136000000,
710         .tsensor_clk_rate = 500000,
711         .sensor_data = {
712                 [TSENSE_CPU0] = {
713                         .enable = true,
714                         .therm_a = 570,
715                         .therm_b = -744,
716                         .tall = 16300,
717                         .tiddq = 1,
718                         .ten_count = 1,
719                         .tsample = 163,
720                         .pdiv = 10,
721                 },
722                 [TSENSE_CPU1] = {
723                         .enable = true,
724                         .therm_a = 570,
725                         .therm_b = -744,
726                         .tall = 16300,
727                         .tiddq = 1,
728                         .ten_count = 1,
729                         .tsample = 163,
730                         .pdiv = 10,
731                 },
732                 [TSENSE_CPU2] = {
733                         .enable = true,
734                         .therm_a = 570,
735                         .therm_b = -744,
736                         .tall = 16300,
737                         .tiddq = 1,
738                         .ten_count = 1,
739                         .tsample = 163,
740                         .pdiv = 10,
741                 },
742                 [TSENSE_CPU3] = {
743                         .enable = true,
744                         .therm_a = 570,
745                         .therm_b = -744,
746                         .tall = 16300,
747                         .tiddq = 1,
748                         .ten_count = 1,
749                         .tsample = 163,
750                         .pdiv = 10,
751                 },
752                 [TSENSE_MEM0] = {
753                         .enable = true,
754                         .therm_a = 570,
755                         .therm_b = -744,
756                         .tall = 16300,
757                         .tiddq = 1,
758                         .ten_count = 1,
759                         .tsample = 163,
760                         .pdiv = 10,
761                 },
762                 [TSENSE_MEM1] = {
763                         .enable = true,
764                         .therm_a = 570,
765                         .therm_b = -744,
766                         .tall = 16300,
767                         .tiddq = 1,
768                         .ten_count = 1,
769                         .tsample = 163,
770                         .pdiv = 10,
771                 },
772                 [TSENSE_GPU] = {
773                         .enable = true,
774                         .therm_a = 570,
775                         .therm_b = -744,
776                         .tall = 16300,
777                         .tiddq = 1,
778                         .ten_count = 1,
779                         .tsample = 163,
780                         .pdiv = 10,
781                 },
782                 [TSENSE_PLLX] = {
783                         .enable = true,
784                         .therm_a = 570,
785                         .therm_b = -744,
786                         .tall = 16300,
787                         .tiddq = 1,
788                         .ten_count = 1,
789                         .tsample = 163,
790                         .pdiv = 10,
791                 },
792         },
793
794         .therm = {
795                 [THERM_CPU] = {
796                         .thermtrip = 90, /* in C */
797                         .hw_backstop = 37, /* in C */
798
799                         .trip_temp = 68000, /* in mC */
800                         .tc1 = 0,
801                         .tc2 = 1,
802                         .passive_delay = 2000,
803                 },
804         },
805
806         .throttle = {
807                 [THROTTLE_HEAVY] = {
808                         .priority = 1,
809                         .devs = {
810                                 [THROTTLE_DEV_CPU] = {
811                                         .enable = true,
812                                         .dividend = 1,
813                                         .divisor = 255,
814                                         .step = 0,
815                                         .duration = 65535,
816                                 },
817                         },
818                 },
819         },
820 };
821
822 static struct balanced_throttle tj_throttle = {
823         .throt_tab_size = 10,
824         .throt_tab = {
825                 {      0, 1000 },
826                 { 640000, 1000 },
827                 { 640000, 1000 },
828                 { 640000, 1000 },
829                 { 640000, 1000 },
830                 { 640000, 1000 },
831                 { 760000, 1000 },
832                 { 760000, 1050 },
833                 {1000000, 1050 },
834                 {1000000, 1100 },
835         },
836 };
837
838 static int __init pluto_soctherm_init(void)
839 {
840         pluto_soctherm_data.therm[THERM_CPU].cdev =
841                         balanced_throttle_register(&tj_throttle);
842
843         return tegra11_soctherm_init(&pluto_soctherm_data);
844 }
845 module_init(pluto_soctherm_init);