arm: tegra: soctherm: Register soctherm device as CPU zone
[linux-2.6.git] / arch / arm / mach-tegra / board-pluto-power.c
1 /*
2  * arch/arm/mach-tegra/board-pluto-power.c
3  *
4  * Copyright (C) 2012 NVIDIA Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
24 #include <linux/io.h>
25
26 #include <mach/iomap.h>
27 #include <mach/edp.h>
28 #include <mach/irqs.h>
29 #include <linux/regulator/fixed.h>
30 #include <linux/mfd/palmas.h>
31 #include <linux/regulator/machine.h>
32 #include <linux/irq.h>
33
34 #include <asm/mach-types.h>
35
36 #include "cpu-tegra.h"
37 #include "pm.h"
38 #include "board.h"
39 #include "board-pluto.h"
40 #include "tegra_cl_dvfs.h"
41 #include "devices.h"
42 #include "tegra11_soctherm.h"
43
44 #define PMC_CTRL                0x0
45 #define PMC_CTRL_INTR_LOW       (1 << 17)
46
47 /************************ Pluto based regulator ****************/
48 static struct regulator_consumer_supply palmas_smps123_supply[] = {
49         REGULATOR_SUPPLY("vdd_cpu", NULL),
50 };
51
52 static struct regulator_consumer_supply palmas_smps45_supply[] = {
53         REGULATOR_SUPPLY("vdd_core", NULL),
54 };
55
56 static struct regulator_consumer_supply palmas_smps6_supply[] = {
57         REGULATOR_SUPPLY("vdd_core_bb", NULL),
58 };
59
60 static struct regulator_consumer_supply palmas_smps7_supply[] = {
61         REGULATOR_SUPPLY("vddio_ddr", NULL),
62         REGULATOR_SUPPLY("vddio_lpddr3", NULL),
63         REGULATOR_SUPPLY("vcore2_lpddr3", NULL),
64         REGULATOR_SUPPLY("vcore_audio_1v2", NULL),
65 };
66
67 static struct regulator_consumer_supply palmas_smps8_supply[] = {
68         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
69         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
70         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
71         REGULATOR_SUPPLY("avdd_osc", NULL),
72         REGULATOR_SUPPLY("vddio_sys", NULL),
73         REGULATOR_SUPPLY("vddio_bb", NULL),
74         REGULATOR_SUPPLY("pwrdet_bb", NULL),
75         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
76         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
77         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
78         REGULATOR_SUPPLY("vdd_emmc", "sdhci-tegra.3"),
79         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
80         REGULATOR_SUPPLY("vddio_audio", NULL),
81         REGULATOR_SUPPLY("pwrdet_audio", NULL),
82         REGULATOR_SUPPLY("vddio_uart", NULL),
83         REGULATOR_SUPPLY("pwrdet_uart", NULL),
84         REGULATOR_SUPPLY("vddio_gmi", NULL),
85         REGULATOR_SUPPLY("pwrdet_nand", NULL),
86         REGULATOR_SUPPLY("vddio_cam", "tegra_camera"),
87         REGULATOR_SUPPLY("pwrdet_cam", NULL),
88         REGULATOR_SUPPLY("vdd_gps", NULL),
89         REGULATOR_SUPPLY("vdd_nfc", NULL),
90         REGULATOR_SUPPLY("vlogic", "0-0069"),
91         REGULATOR_SUPPLY("vdd_dtv", NULL),
92         REGULATOR_SUPPLY("vdd_bb", NULL),
93         REGULATOR_SUPPLY("vcore1_lpddr", NULL),
94         REGULATOR_SUPPLY("vcore_lpddr", NULL),
95         REGULATOR_SUPPLY("vddio_lpddr", NULL),
96         REGULATOR_SUPPLY("vdd_rf", NULL),
97         REGULATOR_SUPPLY("vdd_modem2", NULL),
98         REGULATOR_SUPPLY("vdd_dbg", NULL),
99         REGULATOR_SUPPLY("vdd_sim_1v8", NULL),
100         REGULATOR_SUPPLY("vdd_sim1a_1v8", NULL),
101         REGULATOR_SUPPLY("vdd_sim1b_1v8", NULL),
102         REGULATOR_SUPPLY("dvdd_audio", NULL),
103         REGULATOR_SUPPLY("avdd_audio", NULL),
104         REGULATOR_SUPPLY("vdd_com_1v8", NULL),
105         REGULATOR_SUPPLY("vdd_bt_1v8", NULL),
106         REGULATOR_SUPPLY("dvdd", "spi3.2"),
107         REGULATOR_SUPPLY("avdd_pll_bb", NULL),
108 };
109
110 static struct regulator_consumer_supply palmas_smps9_supply[] = {
111         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
112         REGULATOR_SUPPLY("vdd_sim_mmc", NULL),
113         REGULATOR_SUPPLY("vdd_sim1a_mmc", NULL),
114         REGULATOR_SUPPLY("vdd_sim1b_mmc", NULL),
115 };
116
117 static struct regulator_consumer_supply palmas_smps10_supply[] = {
118         REGULATOR_SUPPLY("unused_smps10", NULL),
119         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
120         REGULATOR_SUPPLY("vdd_vbrtr", NULL),
121         REGULATOR_SUPPLY("vdd_lcd", NULL),
122 };
123
124 static struct regulator_consumer_supply palmas_ldo1_supply[] = {
125         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
126         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
127         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
128         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegra_camera"),
129         REGULATOR_SUPPLY("avdd_pllm", NULL),
130         REGULATOR_SUPPLY("avdd_pllu", NULL),
131         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
132         REGULATOR_SUPPLY("avdd_pllx", NULL),
133         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
134         REGULATOR_SUPPLY("avdd_plle", NULL),
135 };
136
137 static struct regulator_consumer_supply palmas_ldo2_supply[] = {
138         REGULATOR_SUPPLY("avdd_lcd", NULL),
139 };
140
141 static struct regulator_consumer_supply palmas_ldo3_supply[] = {
142         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
143         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
144         REGULATOR_SUPPLY("avdd_dsi_csi", "tegra_camera"),
145         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
146         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
147         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
148         REGULATOR_SUPPLY("vddio_hsic_bb", NULL),
149         REGULATOR_SUPPLY("vddio_hsic_modem2", NULL),
150 };
151
152 static struct regulator_consumer_supply palmas_ldo4_supply[] = {
153         REGULATOR_SUPPLY("vdd_spare", NULL),
154 };
155
156 static struct regulator_consumer_supply palmas_ldo5_supply[] = {
157         REGULATOR_SUPPLY("avdd_cam1", NULL),
158         REGULATOR_SUPPLY("vana", "2-0010"),
159 };
160
161 static struct regulator_consumer_supply palmas_ldo6_supply[] = {
162         REGULATOR_SUPPLY("vdd_temp", NULL),
163         REGULATOR_SUPPLY("vdd_mb", NULL),
164         REGULATOR_SUPPLY("avdd_backlight_3v0", "1-004d"),
165         REGULATOR_SUPPLY("vdd_nfc_3v0", NULL),
166         REGULATOR_SUPPLY("vdd_irled", NULL),
167         REGULATOR_SUPPLY("vdd_sensor_3v0", NULL),
168         REGULATOR_SUPPLY("vdd_3v0_pm", NULL),
169         REGULATOR_SUPPLY("vaux_3v3", NULL),
170         REGULATOR_SUPPLY("vdd", "0-0044"),
171         REGULATOR_SUPPLY("vdd", "0-004c"),
172         REGULATOR_SUPPLY("avdd", "spi3.2"),
173         REGULATOR_SUPPLY("vdd", "0-0069"),
174 };
175
176 static struct regulator_consumer_supply palmas_ldo7_supply[] = {
177         REGULATOR_SUPPLY("vdd_af_cam1", NULL),
178         REGULATOR_SUPPLY("vdd", "2-000e"),
179 };
180 static struct regulator_consumer_supply palmas_ldo8_supply[] = {
181         REGULATOR_SUPPLY("vdd_rtc", NULL),
182 };
183 static struct regulator_consumer_supply palmas_ldo9_supply[] = {
184         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
185         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
186 };
187 static struct regulator_consumer_supply palmas_ldoln_supply[] = {
188         REGULATOR_SUPPLY("avdd_cam2", NULL),
189         REGULATOR_SUPPLY("vana", "2-0036"),
190 };
191
192 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
193         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
194         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
195         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
196         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
197         REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
198         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
199         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
200         REGULATOR_SUPPLY("pwrdet_hv", NULL),
201         REGULATOR_SUPPLY("vdd_dtv_3v3", NULL),
202
203 };
204
205 static struct regulator_consumer_supply palmas_regen1_supply[] = {
206         REGULATOR_SUPPLY("mic_ventral", NULL),
207 };
208
209 static struct regulator_consumer_supply palmas_regen2_supply[] = {
210         REGULATOR_SUPPLY("vdd_mic", NULL),
211 };
212
213 #define PALMAS_PDATA_INIT(_name, _minmv, _maxmv, _supply_reg, _always_on, \
214         _boot_on, _apply_uv)                                            \
215         static struct regulator_init_data reg_idata_##_name = {         \
216                 .constraints = {                                        \
217                         .name = palmas_rails(_name),                    \
218                         .min_uV = (_minmv)*1000,                        \
219                         .max_uV = (_maxmv)*1000,                        \
220                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
221                                         REGULATOR_MODE_STANDBY),        \
222                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
223                                         REGULATOR_CHANGE_STATUS |       \
224                                         REGULATOR_CHANGE_VOLTAGE),      \
225                         .always_on = _always_on,                        \
226                         .boot_on = _boot_on,                            \
227                         .apply_uV = _apply_uv,                          \
228                 },                                                      \
229                 .num_consumer_supplies =                                \
230                         ARRAY_SIZE(palmas_##_name##_supply),            \
231                 .consumer_supplies = palmas_##_name##_supply,           \
232                 .supply_regulator = _supply_reg,                        \
233         }
234
235 PALMAS_PDATA_INIT(smps123, 900,  1300, NULL, 0, 0, 0);
236 PALMAS_PDATA_INIT(smps45, 900,  1400, NULL, 0, 0, 0);
237 PALMAS_PDATA_INIT(smps6, 850,  850, NULL, 0, 0, 1);
238 PALMAS_PDATA_INIT(smps7, 1200,  1200, NULL, 0, 0, 1);
239 PALMAS_PDATA_INIT(smps8, 1800,  1800, NULL, 1, 1, 1);
240 PALMAS_PDATA_INIT(smps9, 2800,  2800, NULL, 1, 0, 1);
241 PALMAS_PDATA_INIT(smps10, 5000,  5000, NULL, 0, 0, 0);
242 PALMAS_PDATA_INIT(ldo1, 1050,  1050, palmas_rails(smps7), 0, 0, 1);
243 PALMAS_PDATA_INIT(ldo2, 2800,  3000, NULL, 0, 0, 0);
244 PALMAS_PDATA_INIT(ldo3, 1200,  1200, palmas_rails(smps8), 0, 1, 1);
245 PALMAS_PDATA_INIT(ldo4, 900,  3300, NULL, 0, 0, 0);
246 PALMAS_PDATA_INIT(ldo5, 2700,  2700, NULL, 0, 0, 1);
247 PALMAS_PDATA_INIT(ldo6, 3000,  3000, NULL, 1, 1, 1);
248 PALMAS_PDATA_INIT(ldo7, 2800,  2800, NULL, 0, 0, 1);
249 PALMAS_PDATA_INIT(ldo8, 900,  900, NULL, 1, 1, 1);
250 PALMAS_PDATA_INIT(ldo9, 1800,  3300, palmas_rails(smps9), 0, 0, 1);
251 PALMAS_PDATA_INIT(ldoln, 2700, 2700, NULL, 0, 0, 1);
252 PALMAS_PDATA_INIT(ldousb, 3300,  3300, NULL, 0, 0, 1);
253 PALMAS_PDATA_INIT(regen1, 4300,  4300, NULL, 0, 0, 0);
254 PALMAS_PDATA_INIT(regen2, 4300,  4300, palmas_rails(smps8), 0, 0, 0);
255
256 #define PALMAS_REG_PDATA(_sname) &reg_idata_##_sname
257
258 static struct regulator_init_data *pluto_reg_data[PALMAS_NUM_REGS] = {
259         NULL,
260         PALMAS_REG_PDATA(smps123),
261         NULL,
262         PALMAS_REG_PDATA(smps45),
263         NULL,
264         PALMAS_REG_PDATA(smps6),
265         PALMAS_REG_PDATA(smps7),
266         PALMAS_REG_PDATA(smps8),
267         PALMAS_REG_PDATA(smps9),
268         PALMAS_REG_PDATA(smps10),
269         PALMAS_REG_PDATA(ldo1),
270         PALMAS_REG_PDATA(ldo2),
271         PALMAS_REG_PDATA(ldo3),
272         PALMAS_REG_PDATA(ldo4),
273         PALMAS_REG_PDATA(ldo5),
274         PALMAS_REG_PDATA(ldo6),
275         PALMAS_REG_PDATA(ldo7),
276         PALMAS_REG_PDATA(ldo8),
277         PALMAS_REG_PDATA(ldo9),
278         PALMAS_REG_PDATA(ldoln),
279         PALMAS_REG_PDATA(ldousb),
280         PALMAS_REG_PDATA(regen1),
281         PALMAS_REG_PDATA(regen2),
282         NULL,
283         NULL,
284         NULL,
285 };
286
287 #define PALMAS_REG_INIT(_name, _warm_reset, _roof_floor, _mode_sleep,   \
288                 _tstep, _vsel)                                          \
289         static struct palmas_reg_init reg_init_data_##_name = {         \
290                 .warm_reset = _warm_reset,                              \
291                 .roof_floor =   _roof_floor,                            \
292                 .mode_sleep = _mode_sleep,              \
293                 .tstep = _tstep,                        \
294                 .vsel = _vsel,          \
295         }
296
297 PALMAS_REG_INIT(smps12, 0, 0, 0, 0, 0);
298 PALMAS_REG_INIT(smps123, 0, PALMAS_EXT_CONTROL_ENABLE1, 0, 0, 0);
299 PALMAS_REG_INIT(smps3, 0, 0, 0, 0, 0);
300 PALMAS_REG_INIT(smps45, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
301 PALMAS_REG_INIT(smps457, 0, 0, 0, 0, 0);
302 PALMAS_REG_INIT(smps6, 0, 0, 0, 0, 0);
303 PALMAS_REG_INIT(smps7, 0, 0, 0, 0, 0);
304 PALMAS_REG_INIT(smps8, 0, 0, 0, 0, 0);
305 PALMAS_REG_INIT(smps9, 0, 0, 0, 0, 0);
306 PALMAS_REG_INIT(smps10, 0, 0, 0, 0, 0);
307 PALMAS_REG_INIT(ldo1, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
308 PALMAS_REG_INIT(ldo2, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
309 PALMAS_REG_INIT(ldo3, 0, 0, 0, 0, 0);
310 PALMAS_REG_INIT(ldo4, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
311 PALMAS_REG_INIT(ldo5, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
312 PALMAS_REG_INIT(ldo6, 0, 0, 0, 0, 0);
313 PALMAS_REG_INIT(ldo7, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
314 PALMAS_REG_INIT(ldo8, 0, 0, 0, 0, 0);
315 PALMAS_REG_INIT(ldo9, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
316 PALMAS_REG_INIT(ldoln, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
317 PALMAS_REG_INIT(ldousb, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
318
319 #define PALMAS_REG_INIT_DATA(_sname) &reg_init_data_##_sname
320 static struct palmas_reg_init *pluto_reg_init[PALMAS_NUM_REGS] = {
321         PALMAS_REG_INIT_DATA(smps12),
322         PALMAS_REG_INIT_DATA(smps123),
323         PALMAS_REG_INIT_DATA(smps3),
324         PALMAS_REG_INIT_DATA(smps45),
325         PALMAS_REG_INIT_DATA(smps457),
326         PALMAS_REG_INIT_DATA(smps6),
327         PALMAS_REG_INIT_DATA(smps7),
328         PALMAS_REG_INIT_DATA(smps8),
329         PALMAS_REG_INIT_DATA(smps9),
330         PALMAS_REG_INIT_DATA(smps10),
331         PALMAS_REG_INIT_DATA(ldo1),
332         PALMAS_REG_INIT_DATA(ldo2),
333         PALMAS_REG_INIT_DATA(ldo3),
334         PALMAS_REG_INIT_DATA(ldo4),
335         PALMAS_REG_INIT_DATA(ldo5),
336         PALMAS_REG_INIT_DATA(ldo6),
337         PALMAS_REG_INIT_DATA(ldo7),
338         PALMAS_REG_INIT_DATA(ldo8),
339         PALMAS_REG_INIT_DATA(ldo9),
340         PALMAS_REG_INIT_DATA(ldoln),
341         PALMAS_REG_INIT_DATA(ldousb),
342 };
343
344 static int ac_online(void)
345 {
346         return 1;
347 }
348
349 static struct resource pluto_pda_resources[] = {
350         [0] = {
351                 .name   = "ac",
352         },
353 };
354
355 static struct pda_power_pdata pluto_pda_data = {
356         .is_ac_online   = ac_online,
357 };
358
359 static struct platform_device pluto_pda_power_device = {
360         .name           = "pda-power",
361         .id             = -1,
362         .resource       = pluto_pda_resources,
363         .num_resources  = ARRAY_SIZE(pluto_pda_resources),
364         .dev    = {
365                 .platform_data  = &pluto_pda_data,
366         },
367 };
368
369 /* Always ON /Battery regulator */
370 static struct regulator_consumer_supply fixed_reg_en_battery_supply[] = {
371                 REGULATOR_SUPPLY("vdd_sys_cam", NULL),
372                 REGULATOR_SUPPLY("vdd_sys_bl", NULL),
373                 REGULATOR_SUPPLY("vdd_sys_com", NULL),
374                 REGULATOR_SUPPLY("vdd_sys_gps", NULL),
375                 REGULATOR_SUPPLY("vdd_sys_bt", NULL),
376                 REGULATOR_SUPPLY("vdd_sys_audio", NULL),
377 };
378
379 static struct regulator_consumer_supply fixed_reg_en_vdd_1v8_cam_supply[] = {
380         REGULATOR_SUPPLY("vddio_cam_mb", NULL),
381         REGULATOR_SUPPLY("vdd_1v8_cam12", NULL),
382         REGULATOR_SUPPLY("vif", "2-0010"),
383         REGULATOR_SUPPLY("vif", "2-0036"),
384         REGULATOR_SUPPLY("vdd_i2c", "2-000e"),
385 };
386
387 static struct regulator_consumer_supply fixed_reg_en_vdd_1v2_cam_supply[] = {
388         REGULATOR_SUPPLY("vdd_1v2_cam", NULL),
389         REGULATOR_SUPPLY("vdig", "2-0010"),
390         REGULATOR_SUPPLY("vdig", "2-0036"),
391 };
392
393 static struct regulator_consumer_supply fixed_reg_en_avdd_usb3_1v05_supply[] = {
394         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
395         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
396 };
397
398 static struct regulator_consumer_supply fixed_reg_en_vdd_mmc_sdmmc3_supply[] = {
399         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
400 };
401
402 static struct regulator_consumer_supply fixed_reg_en_vdd_lcd_1v8_supply[] = {
403         REGULATOR_SUPPLY("vdd_lcd_1v8_s", NULL),
404 };
405
406 static struct regulator_consumer_supply fixed_reg_en_vdd_lcd_mmc_supply[] = {
407         REGULATOR_SUPPLY("vdd_lcd_mmc_s_f", NULL),
408 };
409
410 static struct regulator_consumer_supply fixed_reg_en_vdd_1v8_mic_supply[] = {
411         REGULATOR_SUPPLY("vdd_1v8_mic", NULL),
412 };
413
414 static struct regulator_consumer_supply fixed_reg_en_vdd_hdmi_5v0_supply[] = {
415         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
416 };
417
418 static struct regulator_consumer_supply fixed_reg_en_vpp_fuse_supply[] = {
419         REGULATOR_SUPPLY("vpp_fuse", NULL),
420         REGULATOR_SUPPLY("v_efuse", NULL),
421 };
422
423 /* Macro for defining fixed regulator sub device data */
424 #define FIXED_SUPPLY(_name) "fixed_reg_en"#_name
425 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,   \
426         _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts,  \
427         _sdelay)                                                        \
428         static struct regulator_init_data ri_data_##_var =              \
429         {                                                               \
430                 .supply_regulator = _in_supply,                         \
431                 .num_consumer_supplies =                                \
432                         ARRAY_SIZE(fixed_reg_en_##_name##_supply),      \
433                 .consumer_supplies = fixed_reg_en_##_name##_supply,     \
434                 .constraints = {                                        \
435                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
436                                         REGULATOR_MODE_STANDBY),        \
437                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
438                                         REGULATOR_CHANGE_STATUS |       \
439                                         REGULATOR_CHANGE_VOLTAGE),      \
440                         .always_on = _always_on,                        \
441                         .boot_on = _boot_on,                            \
442                 },                                                      \
443         };                                                              \
444         static struct fixed_voltage_config fixed_reg_en_##_var##_pdata = \
445         {                                                               \
446                 .supply_name = FIXED_SUPPLY(_name),                     \
447                 .microvolts = _millivolts * 1000,                       \
448                 .gpio = _gpio_nr,                                       \
449                 .gpio_is_open_drain = _open_drain,                      \
450                 .enable_high = _active_high,                            \
451                 .enabled_at_boot = _boot_state,                         \
452                 .init_data = &ri_data_##_var,                           \
453                 .startup_delay = _sdelay                                \
454         };                                                              \
455         static struct platform_device fixed_reg_en_##_var##_dev = {     \
456                 .name = "reg-fixed-voltage",                            \
457                 .id = _id,                                              \
458                 .dev = {                                                \
459                         .platform_data = &fixed_reg_en_##_var##_pdata,  \
460                 },                                                      \
461         }
462
463 FIXED_REG(0,    battery,        battery,
464         NULL,   0,      0,
465         -1,     false, true,    0,      3300,   0);
466
467 FIXED_REG(1,    vdd_1v8_cam,    vdd_1v8_cam,
468         palmas_rails(smps8),    0,      0,
469         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO1,  false, true,    0,      1800,
470         0);
471
472 FIXED_REG(2,    vdd_1v2_cam,    vdd_1v2_cam,
473         palmas_rails(smps7),    0,      0,
474         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO2,  false, true,    0,      1200,
475         0);
476
477 FIXED_REG(3,    avdd_usb3_1v05, avdd_usb3_1v05,
478         palmas_rails(smps8),    0,      0,
479         TEGRA_GPIO_PK5, false,  true,   0,      1050,   0);
480
481 FIXED_REG(4,    vdd_mmc_sdmmc3, vdd_mmc_sdmmc3,
482         palmas_rails(smps9),    0,      0,
483         TEGRA_GPIO_PK1, false,  true,   0,      3300,   0);
484
485 FIXED_REG(5,    vdd_lcd_1v8,    vdd_lcd_1v8,
486         palmas_rails(smps8),    0,      0,
487         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO4,  false,  true,   0,      1800,
488         0);
489
490 FIXED_REG(6,    vdd_lcd_mmc,    vdd_lcd_mmc,
491         palmas_rails(smps9),    0,      0,
492         TEGRA_GPIO_PI4, false,  true,   0,      1800,   0);
493
494 FIXED_REG(7,    vdd_1v8_mic,    vdd_1v8_mic,
495         palmas_rails(smps8),    0,      0,
496         -1,     false,  true,   0,      1800,   0);
497
498 FIXED_REG(8,    vdd_hdmi_5v0,   vdd_hdmi_5v0,
499         NULL,   0,      0,
500         TEGRA_GPIO_PK6, true,   true,   0,      5000,   5000);
501
502 FIXED_REG(9,    vpp_fuse,       vpp_fuse,
503         palmas_rails(smps8),    0,      0,
504         TEGRA_GPIO_PX4, false,  true,   0,      1800,   0);
505
506 /*
507  * Creating the fixed regulator device tables
508  */
509 #define ADD_FIXED_REG(_name)    (&fixed_reg_en_##_name##_dev)
510
511 #define E1580_COMMON_FIXED_REG                  \
512         ADD_FIXED_REG(battery),                 \
513         ADD_FIXED_REG(vdd_1v8_cam),             \
514         ADD_FIXED_REG(vdd_1v2_cam),             \
515         ADD_FIXED_REG(avdd_usb3_1v05),          \
516         ADD_FIXED_REG(vdd_mmc_sdmmc3),          \
517         ADD_FIXED_REG(vdd_lcd_1v8),             \
518         ADD_FIXED_REG(vdd_lcd_mmc),             \
519         ADD_FIXED_REG(vdd_1v8_mic),             \
520         ADD_FIXED_REG(vdd_hdmi_5v0),
521
522 #define E1580_T114_FIXED_REG                    \
523         ADD_FIXED_REG(vpp_fuse),
524
525 /* Gpio switch regulator platform data for Pluto E1580 */
526 static struct platform_device *pfixed_reg_devs[] = {
527         E1580_COMMON_FIXED_REG
528         E1580_T114_FIXED_REG
529 };
530
531 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
532 /* board parameters for cpu dfll */
533 static struct tegra_cl_dvfs_cfg_param pluto_cl_dvfs_param = {
534         .sample_rate = 12500,
535
536         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
537         .cf = 10,
538         .ci = 0,
539         .cg = 2,
540
541         .droop_cut_value = 0xF,
542         .droop_restore_ramp = 0x0,
543         .scale_out_ramp = 0x0,
544 };
545 #endif
546
547 /* palmas: fixed 10mV steps from 600mV to 1400mV, with offset 0x10 */
548 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
549 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
550 static inline void fill_reg_map(void)
551 {
552         int i;
553         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
554                 pmu_cpu_vdd_map[i].reg_value = i + 0x10;
555                 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
556         }
557 }
558
559 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
560 static struct tegra_cl_dvfs_platform_data pluto_cl_dvfs_data = {
561         .dfll_clk_name = "dfll_cpu",
562         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
563         .u.pmu_i2c = {
564                 .fs_rate = 400000,
565                 .slave_addr = 0xb0,
566                 .reg = 0x23,
567         },
568         .vdd_map = pmu_cpu_vdd_map,
569         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
570
571         .cfg_param = &pluto_cl_dvfs_param,
572 };
573
574 static int __init pluto_cl_dvfs_init(void)
575 {
576         fill_reg_map();
577         tegra_cl_dvfs_device.dev.platform_data = &pluto_cl_dvfs_data;
578         platform_device_register(&tegra_cl_dvfs_device);
579
580         return 0;
581 }
582 #endif
583
584 static struct palmas_dvfs_init_data palmas_dvfs_idata[] = {
585         {
586                 .en_pwm = false,
587         }, {
588                 .en_pwm = true,
589                 .ext_ctrl = PALMAS_EXT_CONTROL_ENABLE2,
590                 .reg_id = PALMAS_REG_SMPS6,
591                 .step_20mV = true,
592                 .base_voltage_uV = 500000,
593                 .max_voltage_uV = 1100000,
594         },
595 };
596
597 static struct palmas_pmic_platform_data pmic_platform = {
598         .enable_ldo8_tracking = true,
599         .disabe_ldo8_tracking_suspend = true,
600         .disable_smps10_boost_suspend = true,
601         .dvfs_init_data = palmas_dvfs_idata,
602         .dvfs_init_data_size = ARRAY_SIZE(palmas_dvfs_idata),
603 };
604
605 struct palmas_clk32k_init_data palmas_clk32k_idata[] = {
606         {
607                 .clk32k_id = PALMAS_CLOCK32KG,
608                 .enable = true,
609         }, {
610                 .clk32k_id = PALMAS_CLOCK32KG_AUDIO,
611                 .enable = true,
612         },
613 };
614
615 static struct palmas_platform_data palmas_pdata = {
616         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
617         .irq_base = PALMAS_TEGRA_IRQ_BASE,
618         .pmic_pdata = &pmic_platform,
619         .mux_from_pdata = true,
620         .pad1 = 0,
621         .pad2 = (PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK &
622                         (1 << PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT)),
623         .pad3 = PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2,
624         .clk32k_init_data =  palmas_clk32k_idata,
625         .clk32k_init_data_size = ARRAY_SIZE(palmas_clk32k_idata),
626         .irq_type = IRQ_TYPE_LEVEL_HIGH,
627         .use_power_off = true,
628 };
629
630 static struct i2c_board_info palma_device[] = {
631         {
632                 I2C_BOARD_INFO("tps65913", 0x58),
633                 .irq            = INT_EXTERNAL_PMU,
634                 .platform_data  = &palmas_pdata,
635         },
636 };
637
638 int __init pluto_regulator_init(void)
639 {
640         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
641         u32 pmc_ctrl;
642         int i;
643
644 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
645         pluto_cl_dvfs_init();
646 #endif
647
648         /* TPS65913: Normal state of INT request line is LOW.
649          * configure the power management controller to trigger PMU
650          * interrupts when HIGH.
651          */
652         pmc_ctrl = readl(pmc + PMC_CTRL);
653         writel(pmc_ctrl & ~PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
654
655         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
656                 pmic_platform.reg_data[i] = pluto_reg_data[i];
657                 pmic_platform.reg_init[i] = pluto_reg_init[i];
658         }
659
660         platform_device_register(&pluto_pda_power_device);
661         i2c_register_board_info(4, palma_device,
662                         ARRAY_SIZE(palma_device));
663         return 0;
664 }
665
666 static int __init pluto_fixed_regulator_init(void)
667 {
668         if (!machine_is_tegra_pluto())
669                 return 0;
670
671         return platform_add_devices(pfixed_reg_devs,
672                         ARRAY_SIZE(pfixed_reg_devs));
673 }
674 subsys_initcall_sync(pluto_fixed_regulator_init);
675
676 static struct tegra_suspend_platform_data pluto_suspend_data = {
677         .cpu_timer      = 300,
678         .cpu_off_timer  = 300,
679         .suspend_mode   = TEGRA_SUSPEND_LP0,
680         .core_timer     = 0x157e,
681         .core_off_timer = 2000,
682         .corereq_high   = true,
683         .sysclkreq_high = true,
684         .min_residency_noncpu = 600,
685         .min_residency_crail = 1000,
686 };
687
688 int __init pluto_suspend_init(void)
689 {
690         tegra_init_suspend(&pluto_suspend_data);
691         return 0;
692 }
693
694 int __init pluto_edp_init(void)
695 {
696         unsigned int regulator_mA;
697
698         regulator_mA = get_maximum_cpu_current_supported();
699         if (!regulator_mA)
700                 regulator_mA = 9000;
701
702         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
703         tegra_init_cpu_edp_limits(regulator_mA);
704
705         regulator_mA = get_maximum_core_current_supported();
706         if (!regulator_mA)
707                 regulator_mA = 4000;
708
709         pr_info("%s: core regulator %d mA\n", __func__, regulator_mA);
710         tegra_init_core_edp_limits(regulator_mA);
711
712         return 0;
713 }
714
715 static struct soctherm_platform_data pluto_soctherm_data = {
716         .soctherm_clk_rate = 136000000,
717         .tsensor_clk_rate = 500000,
718         .sensor_data = {
719                 [TSENSE_CPU0] = {
720                         .sensor_enable = true,
721                         .zone_enable = false,
722                         .tall = 16300,
723                         .tiddq = 1,
724                         .ten_count = 1,
725                         .tsample = 163,
726                         .pdiv = 10,
727                 },
728                 [TSENSE_CPU1] = {
729                         .sensor_enable = true,
730                         .zone_enable = false,
731                         .tall = 16300,
732                         .tiddq = 1,
733                         .ten_count = 1,
734                         .tsample = 163,
735                         .pdiv = 10,
736                 },
737                 [TSENSE_CPU2] = {
738                         .sensor_enable = true,
739                         .zone_enable = false,
740                         .tall = 16300,
741                         .tiddq = 1,
742                         .ten_count = 1,
743                         .tsample = 163,
744                         .pdiv = 10,
745                 },
746                 [TSENSE_CPU3] = {
747                         .sensor_enable = true,
748                         .zone_enable = false,
749                         .tall = 16300,
750                         .tiddq = 1,
751                         .ten_count = 1,
752                         .tsample = 163,
753                         .pdiv = 10,
754                 },
755                 [TSENSE_GPU] = {
756                         .sensor_enable = true,
757                         .zone_enable = false,
758                         .tall = 16300,
759                         .tiddq = 1,
760                         .ten_count = 1,
761                         .tsample = 163,
762                         .pdiv = 10,
763                 },
764                 [TSENSE_PLLX] = {
765                         .sensor_enable = true,
766                         .zone_enable = false,
767                         .tall = 16300,
768                         .tiddq = 1,
769                         .ten_count = 1,
770                         .tsample = 163,
771                         .pdiv = 10,
772                 },
773         },
774         .therm = {
775                 [THERM_CPU] = {
776                         .zone_enable = true,
777                         .cdev_type = "tegra-balanced",
778                         .thermtrip = 115,
779                         .trip_temp = 85000,
780                         .passive_delay = 1000,
781                         .hysteresis = 3000,
782                 },
783                 [THERM_GPU] = {
784                         .zone_enable = true,
785                 },
786                 [THERM_PLL] = {
787                         .zone_enable = true,
788                 },
789         },
790 };
791
792 int __init pluto_soctherm_init(void)
793 {
794         return tegra11_soctherm_init(&pluto_soctherm_data);
795 }