8b8903207867b37f169b0c706576fccf6b47e2b0
[linux-2.6.git] / arch / arm / mach-tegra / board-pluto-power.c
1 /*
2  * arch/arm/mach-tegra/board-pluto-power.c
3  *
4  * Copyright (C) 2012-2013 NVIDIA Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
24 #include <linux/io.h>
25
26 #include <mach/iomap.h>
27 #include <mach/edp.h>
28 #include <mach/irqs.h>
29 #include <mach/hardware.h>
30 #include <linux/regulator/fixed.h>
31 #include <linux/mfd/palmas.h>
32 #include <linux/regulator/machine.h>
33 #include <linux/irq.h>
34 #include <linux/platform_data/tegra_edp.h>
35
36 #include <asm/mach-types.h>
37
38 #include "cpu-tegra.h"
39 #include "pm.h"
40 #include "board.h"
41 #include "board-common.h"
42 #include "board-pluto.h"
43 #include "board-pmu-defines.h"
44 #include "tegra_cl_dvfs.h"
45 #include "devices.h"
46 #include "tegra11_soctherm.h"
47 #include "tegra3_tsensor.h"
48
49 #define PMC_CTRL                0x0
50 #define PMC_CTRL_INTR_LOW       (1 << 17)
51
52 /************************ Pluto based regulator ****************/
53 static struct regulator_consumer_supply palmas_smps123_supply[] = {
54         REGULATOR_SUPPLY("vdd_cpu", NULL),
55 };
56
57 static struct regulator_consumer_supply palmas_smps45_supply[] = {
58         REGULATOR_SUPPLY("vdd_core", NULL),
59         REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.0"),
60         REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.2"),
61         REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.3"),
62 };
63
64 static struct regulator_consumer_supply palmas_smps6_supply[] = {
65         REGULATOR_SUPPLY("vdd_core_bb", NULL),
66 };
67
68 static struct regulator_consumer_supply palmas_smps7_supply[] = {
69         REGULATOR_SUPPLY("vddio_ddr", NULL),
70         REGULATOR_SUPPLY("vddio_lpddr3", NULL),
71         REGULATOR_SUPPLY("vcore2_lpddr3", NULL),
72         REGULATOR_SUPPLY("vcore_audio_1v2", NULL),
73 };
74
75 static struct regulator_consumer_supply palmas_smps8_supply[] = {
76         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
77         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
78         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
79         REGULATOR_SUPPLY("avdd_osc", NULL),
80         REGULATOR_SUPPLY("vddio_sys", NULL),
81         REGULATOR_SUPPLY("vddio_bb", NULL),
82         REGULATOR_SUPPLY("pwrdet_bb", NULL),
83         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
84         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
85         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
86         REGULATOR_SUPPLY("vdd_emmc", "sdhci-tegra.3"),
87         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
88         REGULATOR_SUPPLY("vddio_audio", NULL),
89         REGULATOR_SUPPLY("pwrdet_audio", NULL),
90         REGULATOR_SUPPLY("vddio_uart", NULL),
91         REGULATOR_SUPPLY("pwrdet_uart", NULL),
92         REGULATOR_SUPPLY("vddio_gmi", NULL),
93         REGULATOR_SUPPLY("pwrdet_nand", NULL),
94         REGULATOR_SUPPLY("vddio_cam", "vi"),
95         REGULATOR_SUPPLY("pwrdet_cam", NULL),
96         REGULATOR_SUPPLY("vdd_gps", NULL),
97         REGULATOR_SUPPLY("vdd_nfc", NULL),
98         REGULATOR_SUPPLY("vlogic", "0-0069"),
99         REGULATOR_SUPPLY("vid", "0-000d"),
100         REGULATOR_SUPPLY("vddio", "0-0078"),
101         REGULATOR_SUPPLY("vdd_dtv", NULL),
102         REGULATOR_SUPPLY("vdd_bb", NULL),
103         REGULATOR_SUPPLY("vcore1_lpddr", NULL),
104         REGULATOR_SUPPLY("vcore_lpddr", NULL),
105         REGULATOR_SUPPLY("vddio_lpddr", NULL),
106         REGULATOR_SUPPLY("vdd_rf", NULL),
107         REGULATOR_SUPPLY("vdd_modem2", NULL),
108         REGULATOR_SUPPLY("vdd_dbg", NULL),
109         REGULATOR_SUPPLY("vdd_sim_1v8", NULL),
110         REGULATOR_SUPPLY("vdd_sim1a_1v8", NULL),
111         REGULATOR_SUPPLY("vdd_sim1b_1v8", NULL),
112         REGULATOR_SUPPLY("dvdd_audio", NULL),
113         REGULATOR_SUPPLY("avdd_audio", NULL),
114         REGULATOR_SUPPLY("vdd_com_1v8", NULL),
115         REGULATOR_SUPPLY("vdd_bt_1v8", NULL),
116         REGULATOR_SUPPLY("dvdd", "spi3.2"),
117         REGULATOR_SUPPLY("avdd_pll_bb", NULL),
118 };
119
120 static struct regulator_consumer_supply palmas_smps9_supply[] = {
121         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
122         REGULATOR_SUPPLY("vdd_sim_mmc", NULL),
123         REGULATOR_SUPPLY("vdd_sim1a_mmc", NULL),
124         REGULATOR_SUPPLY("vdd_sim1b_mmc", NULL),
125 };
126
127 static struct regulator_consumer_supply palmas_smps10_supply[] = {
128         REGULATOR_SUPPLY("unused_smps10", NULL),
129         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
130         REGULATOR_SUPPLY("avddio_usb", "tegra-xhci"),
131         REGULATOR_SUPPLY("usb_vbus", "tegra-xhci"),
132
133         REGULATOR_SUPPLY("vdd_lcd", NULL),
134 };
135
136 static struct regulator_consumer_supply palmas_ldo1_supply[] = {
137         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
138         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
139         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
140         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "vi"),
141         REGULATOR_SUPPLY("avdd_pllm", NULL),
142         REGULATOR_SUPPLY("avdd_pllu", NULL),
143         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
144         REGULATOR_SUPPLY("avdd_pllx", NULL),
145         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
146         REGULATOR_SUPPLY("avdd_plle", NULL),
147 };
148
149 static struct regulator_consumer_supply palmas_ldo2_supply[] = {
150         REGULATOR_SUPPLY("avdd_lcd", NULL),
151 };
152
153 static struct regulator_consumer_supply palmas_ldo3_supply[] = {
154         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
155         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
156         REGULATOR_SUPPLY("avdd_dsi_csi", "vi"),
157         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
158         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
159         REGULATOR_SUPPLY("vddio_hsic", "tegra-xhci"),
160         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
161         REGULATOR_SUPPLY("vddio_hsic_bb", NULL),
162         REGULATOR_SUPPLY("vddio_hsic_modem2", NULL),
163 };
164
165 static struct regulator_consumer_supply palmas_ldo4_supply[] = {
166         REGULATOR_SUPPLY("vdd_spare", NULL),
167 };
168
169 static struct regulator_consumer_supply palmas_ldo5_supply[] = {
170         REGULATOR_SUPPLY("avdd_cam1", NULL),
171         REGULATOR_SUPPLY("vana", "2-0010"),
172 };
173
174 static struct regulator_consumer_supply palmas_ldo6_supply[] = {
175         REGULATOR_SUPPLY("vdd_temp", NULL),
176         REGULATOR_SUPPLY("vdd_mb", NULL),
177         REGULATOR_SUPPLY("vin", "1-004d"),
178         REGULATOR_SUPPLY("vdd_nfc_3v0", NULL),
179         REGULATOR_SUPPLY("vdd_irled", NULL),
180         REGULATOR_SUPPLY("vdd_sensor_3v0", NULL),
181         REGULATOR_SUPPLY("vdd_3v0_pm", NULL),
182         REGULATOR_SUPPLY("vaux_3v3", NULL),
183         REGULATOR_SUPPLY("vdd", "0-0044"),
184         REGULATOR_SUPPLY("vdd", "0-004c"),
185         REGULATOR_SUPPLY("avdd", "spi3.2"),
186         REGULATOR_SUPPLY("vdd", "0-0069"),
187         REGULATOR_SUPPLY("vdd", "0-000d"),
188         REGULATOR_SUPPLY("vdd", "0-0078"),
189 };
190
191 static struct regulator_consumer_supply palmas_ldo7_supply[] = {
192         REGULATOR_SUPPLY("vdd_af_cam1", NULL),
193         REGULATOR_SUPPLY("vdd", "2-000e"),
194 };
195 static struct regulator_consumer_supply palmas_ldo8_supply[] = {
196         REGULATOR_SUPPLY("vdd_rtc", NULL),
197 };
198 static struct regulator_consumer_supply palmas_ldo9_supply[] = {
199         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
200         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
201 };
202 static struct regulator_consumer_supply palmas_ldoln_supply[] = {
203         REGULATOR_SUPPLY("avdd_cam2", NULL),
204         REGULATOR_SUPPLY("vana", "2-0036"),
205 };
206
207 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
208         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
209         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
210         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
211         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
212         REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
213         REGULATOR_SUPPLY("hvdd_usb", "tegra-xhci"),
214         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
215         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
216         REGULATOR_SUPPLY("pwrdet_hv", NULL),
217         REGULATOR_SUPPLY("vdd_dtv_3v3", NULL),
218
219 };
220
221 static struct regulator_consumer_supply palmas_regen1_supply[] = {
222         REGULATOR_SUPPLY("mic_ventral", NULL),
223 };
224
225 static struct regulator_consumer_supply palmas_regen2_supply[] = {
226         REGULATOR_SUPPLY("vdd_mic", NULL),
227 };
228
229 PALMAS_PDATA_INIT(smps123, 900,  1300, NULL, 0, 0, 0, NORMAL);
230 PALMAS_PDATA_INIT(smps45, 900,  1400, NULL, 0, 0, 0, NORMAL);
231 PALMAS_PDATA_INIT(smps6, 850,  850, NULL, 0, 0, 1, NORMAL);
232 PALMAS_PDATA_INIT(smps7, 1200,  1200, NULL, 0, 0, 1, NORMAL);
233 PALMAS_PDATA_INIT(smps8, 1800,  1800, NULL, 1, 1, 1, NORMAL);
234 PALMAS_PDATA_INIT(smps9, 2800,  2800, NULL, 1, 0, 1, NORMAL);
235 PALMAS_PDATA_INIT(smps10, 5000,  5000, NULL, 0, 0, 0, 0);
236 PALMAS_PDATA_INIT(ldo1, 1050,  1050, palmas_rails(smps7), 0, 0, 1, 0);
237 PALMAS_PDATA_INIT(ldo2, 2800,  3000, NULL, 0, 0, 0, 0);
238 PALMAS_PDATA_INIT(ldo3, 1200,  1200, palmas_rails(smps8), 0, 1, 1, 0);
239 PALMAS_PDATA_INIT(ldo4, 900,  3300, NULL, 0, 0, 0, 0);
240 PALMAS_PDATA_INIT(ldo5, 2700,  2700, NULL, 0, 0, 1, 0);
241 PALMAS_PDATA_INIT(ldo6, 3000,  3000, NULL, 1, 1, 1, 0);
242 PALMAS_PDATA_INIT(ldo7, 2800,  2800, NULL, 0, 0, 1, 0);
243 PALMAS_PDATA_INIT(ldo8, 900,  900, NULL, 1, 1, 1, 0);
244 PALMAS_PDATA_INIT(ldo9, 1800,  3300, palmas_rails(smps9), 0, 0, 1, 0);
245 PALMAS_PDATA_INIT(ldoln, 2700, 2700, NULL, 0, 0, 1, 0);
246 PALMAS_PDATA_INIT(ldousb, 3300,  3300, NULL, 0, 0, 1, 0);
247 PALMAS_PDATA_INIT(regen1, 4300,  4300, NULL, 0, 0, 0, 0);
248 PALMAS_PDATA_INIT(regen2, 4300,  4300, palmas_rails(smps8), 0, 0, 0, 0);
249
250 #define PALMAS_REG_PDATA(_sname) &reg_idata_##_sname
251
252 static struct regulator_init_data *pluto_reg_data[PALMAS_NUM_REGS] = {
253         NULL,
254         PALMAS_REG_PDATA(smps123),
255         NULL,
256         PALMAS_REG_PDATA(smps45),
257         NULL,
258         PALMAS_REG_PDATA(smps6),
259         PALMAS_REG_PDATA(smps7),
260         PALMAS_REG_PDATA(smps8),
261         PALMAS_REG_PDATA(smps9),
262         PALMAS_REG_PDATA(smps10),
263         PALMAS_REG_PDATA(ldo1),
264         PALMAS_REG_PDATA(ldo2),
265         PALMAS_REG_PDATA(ldo3),
266         PALMAS_REG_PDATA(ldo4),
267         PALMAS_REG_PDATA(ldo5),
268         PALMAS_REG_PDATA(ldo6),
269         PALMAS_REG_PDATA(ldo7),
270         PALMAS_REG_PDATA(ldo8),
271         PALMAS_REG_PDATA(ldo9),
272         PALMAS_REG_PDATA(ldoln),
273         PALMAS_REG_PDATA(ldousb),
274         PALMAS_REG_PDATA(regen1),
275         PALMAS_REG_PDATA(regen2),
276         NULL,
277         NULL,
278         NULL,
279 };
280
281 #define PALMAS_REG_INIT(_name, _warm_reset, _roof_floor, _mode_sleep,   \
282                 _tstep, _vsel)                                          \
283         static struct palmas_reg_init reg_init_data_##_name = {         \
284                 .warm_reset = _warm_reset,                              \
285                 .roof_floor =   _roof_floor,                            \
286                 .mode_sleep = _mode_sleep,              \
287                 .tstep = _tstep,                        \
288                 .vsel = _vsel,          \
289         }
290
291 PALMAS_REG_INIT(smps12, 0, 0, 0, 0, 0);
292 PALMAS_REG_INIT(smps123, 0, PALMAS_EXT_CONTROL_ENABLE1, 0, 0, 0);
293 PALMAS_REG_INIT(smps3, 0, 0, 0, 0, 0);
294 PALMAS_REG_INIT(smps45, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
295 PALMAS_REG_INIT(smps457, 0, 0, 0, 0, 0);
296 PALMAS_REG_INIT(smps6, 0, 0, 0, 0, 0);
297 PALMAS_REG_INIT(smps7, 0, 0, 0, 0, 0);
298 PALMAS_REG_INIT(smps8, 0, 0, 0, 0, 0);
299 PALMAS_REG_INIT(smps9, 0, 0, 0, 0, 0);
300 PALMAS_REG_INIT(smps10, 0, 0, 0, 0, 0);
301 PALMAS_REG_INIT(ldo1, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
302 PALMAS_REG_INIT(ldo2, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
303 PALMAS_REG_INIT(ldo3, 0, 0, 0, 0, 0);
304 PALMAS_REG_INIT(ldo4, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
305 PALMAS_REG_INIT(ldo5, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
306 PALMAS_REG_INIT(ldo6, 0, 0, 0, 0, 0);
307 PALMAS_REG_INIT(ldo7, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
308 PALMAS_REG_INIT(ldo8, 0, 0, 0, 0, 0);
309 PALMAS_REG_INIT(ldo9, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
310 PALMAS_REG_INIT(ldoln, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
311 PALMAS_REG_INIT(ldousb, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
312
313 #define PALMAS_REG_INIT_DATA(_sname) &reg_init_data_##_sname
314 static struct palmas_reg_init *pluto_reg_init[PALMAS_NUM_REGS] = {
315         PALMAS_REG_INIT_DATA(smps12),
316         PALMAS_REG_INIT_DATA(smps123),
317         PALMAS_REG_INIT_DATA(smps3),
318         PALMAS_REG_INIT_DATA(smps45),
319         PALMAS_REG_INIT_DATA(smps457),
320         PALMAS_REG_INIT_DATA(smps6),
321         PALMAS_REG_INIT_DATA(smps7),
322         PALMAS_REG_INIT_DATA(smps8),
323         PALMAS_REG_INIT_DATA(smps9),
324         PALMAS_REG_INIT_DATA(smps10),
325         PALMAS_REG_INIT_DATA(ldo1),
326         PALMAS_REG_INIT_DATA(ldo2),
327         PALMAS_REG_INIT_DATA(ldo3),
328         PALMAS_REG_INIT_DATA(ldo4),
329         PALMAS_REG_INIT_DATA(ldo5),
330         PALMAS_REG_INIT_DATA(ldo6),
331         PALMAS_REG_INIT_DATA(ldo7),
332         PALMAS_REG_INIT_DATA(ldo8),
333         PALMAS_REG_INIT_DATA(ldo9),
334         PALMAS_REG_INIT_DATA(ldoln),
335         PALMAS_REG_INIT_DATA(ldousb),
336 };
337
338 static int ac_online(void)
339 {
340         return 1;
341 }
342
343 static struct resource pluto_pda_resources[] = {
344         [0] = {
345                 .name   = "ac",
346         },
347 };
348
349 static struct pda_power_pdata pluto_pda_data = {
350         .is_ac_online   = ac_online,
351 };
352
353 static struct platform_device pluto_pda_power_device = {
354         .name           = "pda-power",
355         .id             = -1,
356         .resource       = pluto_pda_resources,
357         .num_resources  = ARRAY_SIZE(pluto_pda_resources),
358         .dev    = {
359                 .platform_data  = &pluto_pda_data,
360         },
361 };
362
363 /* Always ON /Battery regulator */
364 static struct regulator_consumer_supply fixed_reg_en_battery_supply[] = {
365                 REGULATOR_SUPPLY("vdd_sys_cam", NULL),
366                 REGULATOR_SUPPLY("vdd_sys_bl", NULL),
367                 REGULATOR_SUPPLY("vdd_sys_com", NULL),
368                 REGULATOR_SUPPLY("vdd_sys_gps", NULL),
369                 REGULATOR_SUPPLY("vdd_sys_bt", NULL),
370                 REGULATOR_SUPPLY("vdd_sys_audio", NULL),
371                 REGULATOR_SUPPLY("vdd_vbrtr", NULL),
372 };
373
374 static struct regulator_consumer_supply fixed_reg_en_vdd_1v8_cam_supply[] = {
375         REGULATOR_SUPPLY("vddio_cam_mb", NULL),
376         REGULATOR_SUPPLY("vdd_1v8_cam12", NULL),
377         REGULATOR_SUPPLY("vif", "2-0010"),
378         REGULATOR_SUPPLY("vif", "2-0036"),
379         REGULATOR_SUPPLY("vdd_i2c", "2-000e"),
380 };
381
382 static struct regulator_consumer_supply fixed_reg_en_vdd_1v2_cam_supply[] = {
383         REGULATOR_SUPPLY("vdd_1v2_cam", NULL),
384         REGULATOR_SUPPLY("vdig", "2-0010"),
385         REGULATOR_SUPPLY("vdig", "2-0036"),
386 };
387
388 static struct regulator_consumer_supply fixed_reg_en_avdd_usb3_1v05_supply[] = {
389         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
390         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
391         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-xhci"),
392 };
393
394 static struct regulator_consumer_supply fixed_reg_en_vdd_mmc_sdmmc3_supply[] = {
395         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
396 };
397
398 static struct regulator_consumer_supply fixed_reg_en_vdd_lcd_1v8_supply[] = {
399         REGULATOR_SUPPLY("vdd_lcd_1v8_s", NULL),
400 };
401
402 static struct regulator_consumer_supply fixed_reg_en_vdd_lcd_mmc_supply[] = {
403         REGULATOR_SUPPLY("vdd_lcd_mmc_s_f", NULL),
404 };
405
406 static struct regulator_consumer_supply fixed_reg_en_vdd_1v8_mic_supply[] = {
407         REGULATOR_SUPPLY("vdd_1v8_mic", NULL),
408 };
409
410 static struct regulator_consumer_supply fixed_reg_en_vdd_hdmi_5v0_supply[] = {
411         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
412 };
413
414 static struct regulator_consumer_supply fixed_reg_en_vpp_fuse_supply[] = {
415         REGULATOR_SUPPLY("vpp_fuse", NULL),
416         REGULATOR_SUPPLY("v_efuse", NULL),
417 };
418
419 /* Macro for defining fixed regulator sub device data */
420 #define FIXED_SUPPLY(_name) "fixed_reg_en"#_name
421 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,   \
422         _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts,  \
423         _sdelay)                                                        \
424         static struct regulator_init_data ri_data_##_var =              \
425         {                                                               \
426                 .supply_regulator = _in_supply,                         \
427                 .num_consumer_supplies =                                \
428                         ARRAY_SIZE(fixed_reg_en_##_name##_supply),      \
429                 .consumer_supplies = fixed_reg_en_##_name##_supply,     \
430                 .constraints = {                                        \
431                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
432                                         REGULATOR_MODE_STANDBY),        \
433                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
434                                         REGULATOR_CHANGE_STATUS |       \
435                                         REGULATOR_CHANGE_VOLTAGE),      \
436                         .always_on = _always_on,                        \
437                         .boot_on = _boot_on,                            \
438                 },                                                      \
439         };                                                              \
440         static struct fixed_voltage_config fixed_reg_en_##_var##_pdata = \
441         {                                                               \
442                 .supply_name = FIXED_SUPPLY(_name),                     \
443                 .microvolts = _millivolts * 1000,                       \
444                 .gpio = _gpio_nr,                                       \
445                 .gpio_is_open_drain = _open_drain,                      \
446                 .enable_high = _active_high,                            \
447                 .enabled_at_boot = _boot_state,                         \
448                 .init_data = &ri_data_##_var,                           \
449                 .startup_delay = _sdelay                                \
450         };                                                              \
451         static struct platform_device fixed_reg_en_##_var##_dev = {     \
452                 .name = "reg-fixed-voltage",                            \
453                 .id = _id,                                              \
454                 .dev = {                                                \
455                         .platform_data = &fixed_reg_en_##_var##_pdata,  \
456                 },                                                      \
457         }
458
459 FIXED_REG(0,    battery,        battery,
460         NULL,   0,      0,
461         -1,     false, true,    0,      3300,   0);
462
463 FIXED_REG(1,    vdd_1v8_cam,    vdd_1v8_cam,
464         palmas_rails(smps8),    0,      0,
465         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO1,  false, true,    0,      1800,
466         0);
467
468 FIXED_REG(2,    vdd_1v2_cam,    vdd_1v2_cam,
469         palmas_rails(smps7),    0,      0,
470         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO2,  false, true,    0,      1200,
471         0);
472
473 FIXED_REG(3,    avdd_usb3_1v05, avdd_usb3_1v05,
474         palmas_rails(smps8),    0,      0,
475         TEGRA_GPIO_PK5, false,  true,   0,      1050,   0);
476
477 FIXED_REG(4,    vdd_mmc_sdmmc3, vdd_mmc_sdmmc3,
478         palmas_rails(smps9),    0,      0,
479         TEGRA_GPIO_PK1, false,  true,   0,      3300,   0);
480
481 FIXED_REG(5,    vdd_lcd_1v8,    vdd_lcd_1v8,
482         palmas_rails(smps8),    0,      0,
483         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO4,  false,  true,   0,      1800,
484         0);
485
486 FIXED_REG(6,    vdd_lcd_mmc,    vdd_lcd_mmc,
487         palmas_rails(smps9),    0,      0,
488         TEGRA_GPIO_PI4, false,  true,   0,      1800,   0);
489
490 FIXED_REG(7,    vdd_1v8_mic,    vdd_1v8_mic,
491         palmas_rails(smps8),    0,      0,
492         -1,     false,  true,   0,      1800,   0);
493
494 FIXED_REG(8,    vdd_hdmi_5v0,   vdd_hdmi_5v0,
495         NULL,   0,      0,
496         TEGRA_GPIO_PK6, true,   true,   0,      5000,   5000);
497
498 FIXED_REG(9,    vpp_fuse,       vpp_fuse,
499         palmas_rails(smps8),    0,      0,
500         TEGRA_GPIO_PX4, false,  true,   0,      1800,   0);
501
502 /*
503  * Creating the fixed regulator device tables
504  */
505 #define ADD_FIXED_REG(_name)    (&fixed_reg_en_##_name##_dev)
506
507 #define E1580_COMMON_FIXED_REG                  \
508         ADD_FIXED_REG(battery),                 \
509         ADD_FIXED_REG(vdd_1v8_cam),             \
510         ADD_FIXED_REG(vdd_1v2_cam),             \
511         ADD_FIXED_REG(avdd_usb3_1v05),          \
512         ADD_FIXED_REG(vdd_mmc_sdmmc3),          \
513         ADD_FIXED_REG(vdd_lcd_1v8),             \
514         ADD_FIXED_REG(vdd_lcd_mmc),             \
515         ADD_FIXED_REG(vdd_1v8_mic),             \
516         ADD_FIXED_REG(vdd_hdmi_5v0),
517
518 #define E1580_T114_FIXED_REG                    \
519         ADD_FIXED_REG(vpp_fuse),
520
521 /* Gpio switch regulator platform data for Pluto E1580 */
522 static struct platform_device *pfixed_reg_devs[] = {
523         E1580_COMMON_FIXED_REG
524         E1580_T114_FIXED_REG
525 };
526
527 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
528 /* board parameters for cpu dfll */
529 static struct tegra_cl_dvfs_cfg_param pluto_cl_dvfs_param = {
530         .sample_rate = 12500,
531
532         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
533         .cf = 10,
534         .ci = 0,
535         .cg = 2,
536
537         .droop_cut_value = 0xF,
538         .droop_restore_ramp = 0x0,
539         .scale_out_ramp = 0x0,
540 };
541 #endif
542
543 /* palmas: fixed 10mV steps from 600mV to 1400mV, with offset 0x10 */
544 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
545 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
546 static inline void fill_reg_map(void)
547 {
548         int i;
549         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
550                 pmu_cpu_vdd_map[i].reg_value = i + 0x10;
551                 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
552         }
553 }
554
555 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
556 static struct tegra_cl_dvfs_platform_data pluto_cl_dvfs_data = {
557         .dfll_clk_name = "dfll_cpu",
558         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
559         .u.pmu_i2c = {
560                 .fs_rate = 400000,
561                 .slave_addr = 0xb0,
562                 .reg = 0x23,
563         },
564         .vdd_map = pmu_cpu_vdd_map,
565         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
566
567         .cfg_param = &pluto_cl_dvfs_param,
568 };
569
570 static int __init pluto_cl_dvfs_init(void)
571 {
572         fill_reg_map();
573         if (tegra_revision < TEGRA_REVISION_A02)
574                 pluto_cl_dvfs_data.out_quiet_then_disable = true;
575         tegra_cl_dvfs_device.dev.platform_data = &pluto_cl_dvfs_data;
576         platform_device_register(&tegra_cl_dvfs_device);
577
578         return 0;
579 }
580 #endif
581
582 static struct palmas_dvfs_init_data palmas_dvfs_idata[] = {
583         {
584                 .en_pwm = false,
585         }, {
586                 .en_pwm = true,
587                 .ext_ctrl = PALMAS_EXT_CONTROL_ENABLE2,
588                 .reg_id = PALMAS_REG_SMPS6,
589                 .step_20mV = true,
590                 .base_voltage_uV = 500000,
591                 .max_voltage_uV = 1100000,
592         },
593 };
594
595 static struct palmas_pmic_platform_data pmic_platform = {
596         .enable_ldo8_tracking = true,
597         .disabe_ldo8_tracking_suspend = true,
598         .disable_smps10_boost_suspend = true,
599         .dvfs_init_data = palmas_dvfs_idata,
600         .dvfs_init_data_size = ARRAY_SIZE(palmas_dvfs_idata),
601 };
602
603 struct palmas_clk32k_init_data palmas_clk32k_idata[] = {
604         {
605                 .clk32k_id = PALMAS_CLOCK32KG,
606                 .enable = true,
607         }, {
608                 .clk32k_id = PALMAS_CLOCK32KG_AUDIO,
609                 .enable = true,
610         },
611 };
612
613 static struct palmas_pinctrl_config palmas_pincfg[] = {
614         PALMAS_PINMUX(POWERGOOD, POWERGOOD, DEFAULT, DEFAULT),
615         PALMAS_PINMUX(VAC, VAC, DEFAULT, DEFAULT),
616         PALMAS_PINMUX(GPIO0, GPIO, DEFAULT, DEFAULT),
617         PALMAS_PINMUX(GPIO1, GPIO, DEFAULT, DEFAULT),
618         PALMAS_PINMUX(GPIO2, GPIO, DEFAULT, DEFAULT),
619         PALMAS_PINMUX(GPIO3, GPIO, DEFAULT, DEFAULT),
620         PALMAS_PINMUX(GPIO4, GPIO, DEFAULT, DEFAULT),
621         PALMAS_PINMUX(GPIO5, CLK32KGAUDIO, DEFAULT, DEFAULT),
622         PALMAS_PINMUX(GPIO6, GPIO, DEFAULT, DEFAULT),
623         PALMAS_PINMUX(GPIO7, GPIO, DEFAULT, DEFAULT),
624 };
625
626 static struct palmas_pinctrl_platform_data palmas_pinctrl_pdata = {
627         .pincfg = palmas_pincfg,
628         .num_pinctrl = ARRAY_SIZE(palmas_pincfg),
629         .dvfs1_enable = false,
630         .dvfs2_enable = true,
631 };
632
633 static struct palmas_platform_data palmas_pdata = {
634         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
635         .irq_base = PALMAS_TEGRA_IRQ_BASE,
636         .pmic_pdata = &pmic_platform,
637         .clk32k_init_data =  palmas_clk32k_idata,
638         .clk32k_init_data_size = ARRAY_SIZE(palmas_clk32k_idata),
639         .irq_type = IRQ_TYPE_LEVEL_HIGH,
640         .use_power_off = true,
641         .pinctrl_pdata = &palmas_pinctrl_pdata,
642 };
643
644 static struct i2c_board_info palma_device[] = {
645         {
646                 I2C_BOARD_INFO("tps65913", 0x58),
647                 .irq            = INT_EXTERNAL_PMU,
648                 .platform_data  = &palmas_pdata,
649         },
650 };
651
652 int __init pluto_regulator_init(void)
653 {
654         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
655         u32 pmc_ctrl;
656         int i;
657
658 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
659         pluto_cl_dvfs_init();
660 #endif
661
662         /* TPS65913: Normal state of INT request line is LOW.
663          * configure the power management controller to trigger PMU
664          * interrupts when HIGH.
665          */
666         pmc_ctrl = readl(pmc + PMC_CTRL);
667         writel(pmc_ctrl & ~PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
668
669         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
670                 pmic_platform.reg_data[i] = pluto_reg_data[i];
671                 pmic_platform.reg_init[i] = pluto_reg_init[i];
672         }
673
674         platform_device_register(&pluto_pda_power_device);
675         i2c_register_board_info(4, palma_device,
676                         ARRAY_SIZE(palma_device));
677         return 0;
678 }
679
680 static int __init pluto_fixed_regulator_init(void)
681 {
682         if (!machine_is_tegra_pluto())
683                 return 0;
684
685         return platform_add_devices(pfixed_reg_devs,
686                         ARRAY_SIZE(pfixed_reg_devs));
687 }
688 subsys_initcall_sync(pluto_fixed_regulator_init);
689
690 static struct tegra_suspend_platform_data pluto_suspend_data = {
691         .cpu_timer      = 300,
692         .cpu_off_timer  = 300,
693         .suspend_mode   = TEGRA_SUSPEND_LP0,
694         .core_timer     = 0x157e,
695         .core_off_timer = 2000,
696         .corereq_high   = true,
697         .sysclkreq_high = true,
698         .cpu_lp2_min_residency = 1000,
699         .min_residency_crail = 20000,
700 #ifdef CONFIG_TEGRA_LP1_LOW_COREVOLTAGE
701         .lp1_lowvolt_support = true,
702         .i2c_base_addr = TEGRA_I2C5_BASE,
703         .pmuslave_addr = 0xB0,
704         .core_reg_addr = 0x2B,
705         .lp1_core_volt_low = 0x33,
706         .lp1_core_volt_high = 0x42,
707 #endif
708 };
709
710 int __init pluto_suspend_init(void)
711 {
712         tegra_init_suspend(&pluto_suspend_data);
713         return 0;
714 }
715
716 int __init pluto_edp_init(void)
717 {
718         unsigned int regulator_mA;
719
720         regulator_mA = get_maximum_cpu_current_supported();
721         if (!regulator_mA)
722                 regulator_mA = 9000;
723
724         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
725         tegra_init_cpu_edp_limits(regulator_mA);
726
727         regulator_mA = get_maximum_core_current_supported();
728         if (!regulator_mA)
729                 regulator_mA = 4000;
730
731         pr_info("%s: core regulator %d mA\n", __func__, regulator_mA);
732         tegra_init_core_edp_limits(regulator_mA);
733
734         return 0;
735 }
736
737 static struct thermal_zone_params pluto_soctherm_therm_cpu_tzp = {
738         .governor_name = "pid_thermal_gov",
739 };
740
741 static struct tegra_tsensor_pmu_data tpdata_palmas = {
742         .reset_tegra = 1,
743         .pmu_16bit_ops = 0,
744         .controller_type = 0,
745         .pmu_i2c_addr = 0x58,
746         .i2c_controller_id = 4,
747         .poweroff_reg_addr = 0xa0,
748         .poweroff_reg_data = 0x0,
749 };
750
751 static struct soctherm_platform_data pluto_soctherm_data = {
752         .therm = {
753                 [THERM_CPU] = {
754                         .zone_enable = true,
755                         .passive_delay = 1000,
756                         .hotspot_offset = 6000,
757                         .num_trips = 3,
758                         .trips = {
759                                 {
760                                         .cdev_type = "tegra-balanced",
761                                         .trip_temp = 90000,
762                                         .trip_type = THERMAL_TRIP_PASSIVE,
763                                         .upper = THERMAL_NO_LIMIT,
764                                         .lower = THERMAL_NO_LIMIT,
765                                 },
766                                 {
767                                         .cdev_type = "tegra-heavy",
768                                         .trip_temp = 100000,
769                                         .trip_type = THERMAL_TRIP_HOT,
770                                         .upper = THERMAL_NO_LIMIT,
771                                         .lower = THERMAL_NO_LIMIT,
772                                 },
773                                 {
774                                         .cdev_type = "tegra-shutdown",
775                                         .trip_temp = 102000,
776                                         .trip_type = THERMAL_TRIP_CRITICAL,
777                                         .upper = THERMAL_NO_LIMIT,
778                                         .lower = THERMAL_NO_LIMIT,
779                                 },
780                         },
781                         .tzp = &pluto_soctherm_therm_cpu_tzp,
782                 },
783                 [THERM_GPU] = {
784                         .zone_enable = true,
785                         .passive_delay = 1000,
786                         .hotspot_offset = 6000,
787                         .num_trips = 3,
788                         .trips = {
789                                 {
790                                         .cdev_type = "tegra-balanced",
791                                         .trip_temp = 90000,
792                                         .trip_type = THERMAL_TRIP_PASSIVE,
793                                         .upper = THERMAL_NO_LIMIT,
794                                         .lower = THERMAL_NO_LIMIT,
795                                 },
796                                 {
797                                         .cdev_type = "tegra-heavy",
798                                         .trip_temp = 100000,
799                                         .trip_type = THERMAL_TRIP_HOT,
800                                         .upper = THERMAL_NO_LIMIT,
801                                         .lower = THERMAL_NO_LIMIT,
802                                 },
803                                 {
804                                         .cdev_type = "tegra-shutdown",
805                                         .trip_temp = 102000,
806                                         .trip_type = THERMAL_TRIP_CRITICAL,
807                                         .upper = THERMAL_NO_LIMIT,
808                                         .lower = THERMAL_NO_LIMIT,
809                                 },
810                         },
811                         .tzp = &pluto_soctherm_therm_cpu_tzp,
812                 },
813                 [THERM_PLL] = {
814                         .zone_enable = true,
815                 },
816         },
817         .throttle = {
818                 [THROTTLE_HEAVY] = {
819                         .priority = 100,
820                         .devs = {
821                                 [THROTTLE_DEV_CPU] = {
822                                         .enable = true,
823                                         .depth = 80,
824                                 },
825                         },
826                 },
827                 [THROTTLE_OC2] = {
828                         .throt_mode = BRIEF,
829                         .polarity = 0,
830                         .devs = {
831                                 [THROTTLE_DEV_CPU] = {
832                                         .enable = true,
833                                         .depth = 50,
834                                 },
835                                 [THROTTLE_DEV_GPU] = {
836                                         .enable = true,
837                                         .depth = 50,
838                                 },
839                         },
840                 },
841                 [THROTTLE_OC4] = {
842                         .throt_mode = BRIEF,
843                         .polarity = 1,
844                         .intr = true,
845                         .devs = {
846                                 [THROTTLE_DEV_CPU] = {
847                                         .enable = true,
848                                         .depth = 50,
849                                 },
850                                 [THROTTLE_DEV_GPU] = {
851                                         .enable = true,
852                                         .depth = 50,
853                                 },
854                         },
855                 },
856         },
857         .tshut_pmu_trip_data = &tpdata_palmas,
858 };
859
860 int __init pluto_soctherm_init(void)
861 {
862         tegra_platform_edp_init(pluto_soctherm_data.therm[THERM_CPU].trips,
863                         &pluto_soctherm_data.therm[THERM_CPU].num_trips,
864                         8000);  /* edp temperature margin */
865         tegra_add_tj_trips(pluto_soctherm_data.therm[THERM_CPU].trips,
866                         &pluto_soctherm_data.therm[THERM_CPU].num_trips);
867         tegra_add_vc_trips(pluto_soctherm_data.therm[THERM_CPU].trips,
868                         &pluto_soctherm_data.therm[THERM_CPU].num_trips);
869
870         return tegra11_soctherm_init(&pluto_soctherm_data);
871 }
872
873 static struct tegra_sysedp_corecap pluto_sysedp_corecap[] = {
874         {  1000,    0, {   748, 240, 204 }, {   748, 240, 204 } },
875         {  2000,    0, {   748, 240, 204 }, {   748, 240, 204 } },
876         {  3000,    0, {   748, 240, 204 }, {   748, 240, 204 } },
877         {  4000,    0, {   748, 240, 204 }, {   748, 240, 204 } },
878         {  5000,    0, {   748, 240, 204 }, {   748, 240, 204 } },
879         {  6000,    0, {  1748, 240, 204 }, {  1748, 240, 204 } },
880         {  7000,    0, {  2748, 240, 204 }, {  2748, 240, 204 } },
881         {  7000, 1000, {  3748, 240, 204 }, {  3748, 240, 204 } },
882         {  7000, 2000, {  4748, 240, 204 }, {  4696, 324, 204 } },
883         {  7000, 3000, {  4843, 240, 624 }, {  4913, 420, 408 } },
884         {  7000, 4000, {  5843, 240, 624 }, {  5306, 420, 624 } },
885         {  8000,    0, {  3748, 240, 204 }, {  3748, 240, 204 } },
886         {  8000, 1000, {  4748, 240, 204 }, {  4696, 324, 204 } },
887         {  8000, 2000, {  4843, 240, 624 }, {  4975, 324, 408 } },
888         {  8000, 3000, {  5843, 240, 624 }, {  5913, 420, 408 } },
889         {  8000, 4000, {  6843, 240, 624 }, {  5895, 528, 624 } },
890         {  9000,    0, {  4748, 240, 204 }, {  3975, 324, 408 } },
891         {  9000, 1000, {  4843, 240, 624 }, {  4975, 324, 408 } },
892         {  9000, 2000, {  5843, 240, 624 }, {  5913, 420, 408 } },
893         {  9000, 3000, {  6565, 240, 792 }, {  5895, 528, 624 } },
894         {  9000, 4000, {  7565, 240, 792 }, {  6405, 600, 624 } },
895         { 10000,    0, {  4565, 240, 792 }, {  3895, 528, 624 } },
896         { 10000, 1000, {  5565, 240, 792 }, {  4895, 528, 624 } },
897         { 10000, 2000, {  6565, 240, 792 }, {  5405, 600, 624 } },
898         { 10000, 3000, {  7565, 240, 792 }, {  5277, 600, 792 } },
899         { 10000, 4000, {  8565, 240, 792 }, {  6277, 600, 792 } },
900         { 11000,    0, {  5565, 240, 792 }, {  5553, 324, 624 } },
901         { 11000, 1000, {  6565, 240, 792 }, {  5405, 600, 624 } },
902         { 11000, 2000, {  7565, 240, 792 }, {  5277, 600, 792 } },
903         { 11000, 3000, {  8565, 240, 792 }, {  6277, 600, 792 } },
904         { 11000, 4000, {  9565, 240, 792 }, {  7277, 600, 792 } },
905         { 12000,    0, {  6565, 240, 792 }, {  5405, 600, 624 } },
906         { 12000, 1000, {  7565, 240, 792 }, {  5277, 600, 792 } },
907         { 12000, 2000, {  8565, 240, 792 }, {  6277, 600, 792 } },
908         { 12000, 3000, {  9565, 240, 792 }, {  7277, 600, 792 } },
909         { 12000, 4000, { 10565, 240, 792 }, {  8277, 600, 792 } },
910         { 13000,    0, {  7565, 240, 792 }, {  6405, 600, 624 } },
911         { 13000, 1000, {  8565, 240, 792 }, {  6277, 600, 792 } },
912         { 13000, 2000, {  9565, 240, 792 }, {  7277, 600, 792 } },
913         { 13000, 3000, { 10565, 240, 792 }, {  8277, 600, 792 } },
914         { 13000, 4000, { 11565, 240, 792 }, {  9277, 600, 792 } },
915         { 14000,    0, {  8565, 240, 792 }, {  6277, 600, 792 } },
916         { 14000, 1000, {  9565, 240, 792 }, {  7277, 600, 792 } },
917         { 14000, 2000, { 10565, 240, 792 }, {  8277, 600, 792 } },
918         { 14000, 3000, { 11565, 240, 792 }, {  9277, 600, 792 } },
919         { 14000, 4000, { 12565, 240, 792 }, { 10277, 600, 792 } },
920         { 15000,    0, {  9565, 240, 792 }, {  7277, 600, 792 } },
921         { 15000, 1000, { 10565, 240, 792 }, {  8277, 600, 792 } },
922         { 15000, 2000, { 11565, 240, 792 }, {  9277, 600, 792 } },
923         { 15000, 3000, { 12565, 240, 792 }, { 10277, 600, 792 } },
924         { 15000, 4000, { 13565, 240, 792 }, { 11277, 600, 792 } },
925         { 16000,    0, { 10565, 240, 792 }, {  8277, 600, 792 } },
926         { 16000, 1000, { 11565, 240, 792 }, {  9277, 600, 792 } },
927         { 16000, 2000, { 12565, 240, 792 }, { 10277, 600, 792 } },
928         { 16000, 3000, { 13565, 240, 792 }, { 11277, 600, 792 } },
929         { 16000, 4000, { 14565, 240, 792 }, { 12277, 600, 792 } },
930         { 17000,    0, { 11565, 240, 792 }, {  9277, 600, 792 } },
931         { 17000, 1000, { 12565, 240, 792 }, { 10277, 600, 792 } },
932         { 17000, 2000, { 13565, 240, 792 }, { 11277, 600, 792 } },
933         { 17000, 3000, { 14565, 240, 792 }, { 12277, 600, 792 } },
934         { 17000, 4000, { 15565, 240, 792 }, { 13277, 600, 792 } },
935         { 18000,    0, { 12565, 240, 792 }, { 10277, 600, 792 } },
936         { 18000, 1000, { 13565, 240, 792 }, { 11277, 600, 792 } },
937         { 18000, 2000, { 14565, 240, 792 }, { 12277, 600, 792 } },
938         { 18000, 3000, { 15565, 240, 792 }, { 13277, 600, 792 } },
939         { 18000, 4000, { 16565, 240, 792 }, { 14277, 600, 792 } },
940         { 19000,    0, { 13565, 240, 792 }, { 11277, 600, 792 } },
941         { 19000, 1000, { 14565, 240, 792 }, { 12277, 600, 792 } },
942         { 19000, 2000, { 15565, 240, 792 }, { 13277, 600, 792 } },
943         { 19000, 3000, { 16565, 240, 792 }, { 14277, 600, 792 } },
944         { 19000, 4000, { 17565, 240, 792 }, { 15277, 600, 792 } },
945         { 23000,    0, { 15277, 600, 792 }, { 15277, 600, 792 } }
946 };
947
948 static struct tegra_sysedp_platform_data pluto_sysedp_platdata = {
949         .corecap = pluto_sysedp_corecap,
950         .corecap_size = ARRAY_SIZE(pluto_sysedp_corecap)
951 };
952
953 static struct platform_device pluto_sysedp_device = {
954         .name = "tegra_sysedp",
955         .id = -1,
956         .dev = { .platform_data = &pluto_sysedp_platdata }
957 };
958
959 static __init int pluto_sysedp_init(void)
960 {
961         pluto_sysedp_platdata.cpufreq_lim = tegra_get_system_edp_entries(
962                         &pluto_sysedp_platdata.cpufreq_lim_size);
963         if (!pluto_sysedp_platdata.cpufreq_lim) {
964                 WARN_ON(1);
965                 return -ENODEV;
966         }
967
968         return platform_device_register(&pluto_sysedp_device);
969 }
970 late_initcall(pluto_sysedp_init);