ARM: tegra3: p1852: clock: changed p1852 clocks
[linux-2.6.git] / arch / arm / mach-tegra / board-p1852.c
1 /*
2  * arch/arm/mach-tegra/board-p1852.c
3  *
4  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  *
18  */
19
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/slab.h>
23 #include <linux/ctype.h>
24 #include <linux/platform_device.h>
25 #include <linux/clk.h>
26 #include <linux/serial_8250.h>
27 #include <linux/i2c.h>
28 #include <linux/i2c/panjit_ts.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/delay.h>
31 #include <linux/i2c-tegra.h>
32 #include <linux/gpio.h>
33 #include <linux/input.h>
34 #include <linux/platform_data/tegra_usb.h>
35 #include <linux/platform_data/tegra_nor.h>
36 #include <linux/spi/spi.h>
37 #include <linux/mtd/partitions.h>
38 #include <mach/clk.h>
39 #include <mach/iomap.h>
40 #include <mach/irqs.h>
41 #include <mach/pinmux.h>
42 #include <mach/iomap.h>
43 #include <mach/io.h>
44 #include <mach/pci.h>
45 #include <mach/audio.h>
46 #include <mach/tegra_p1852_pdata.h>
47 #include <asm/mach/flash.h>
48 #include <asm/mach-types.h>
49 #include <asm/mach/arch.h>
50 #include <mach/usb_phy.h>
51 #include <sound/wm8903.h>
52 #include <mach/tsensor.h>
53 #include "board.h"
54 #include "clock.h"
55 #include "board-p1852.h"
56 #include "devices.h"
57 #include "gpio-names.h"
58 #include "fuse.h"
59
60 static struct tegra_utmip_config utmi_phy_config[] = {
61         [0] = {
62                         .hssync_start_delay = 0,
63                         .idle_wait_delay = 17,
64                         .elastic_limit = 16,
65                         .term_range_adj = 6,
66                         .xcvr_setup = 15,
67                         .xcvr_setup_offset = 0,
68                         .xcvr_use_fuses = 1,
69                         .xcvr_lsfslew = 2,
70                         .xcvr_lsrslew = 2,
71         },
72         [1] = {
73                         .hssync_start_delay = 0,
74                         .idle_wait_delay = 17,
75                         .elastic_limit = 16,
76                         .term_range_adj = 6,
77                         .xcvr_setup = 15,
78                         .xcvr_setup_offset = 0,
79                         .xcvr_use_fuses = 1,
80                         .xcvr_lsfslew = 2,
81                         .xcvr_lsrslew = 2,
82         },
83         [2] = {
84                         .hssync_start_delay = 0,
85                         .idle_wait_delay = 17,
86                         .elastic_limit = 16,
87                         .term_range_adj = 6,
88                         .xcvr_setup = 8,
89                         .xcvr_setup_offset = 0,
90                         .xcvr_use_fuses = 1,
91                         .xcvr_lsfslew = 2,
92                         .xcvr_lsrslew = 2,
93         },
94 };
95
96 static __initdata struct tegra_clk_init_table p1852_clk_init_table[] = {
97         /* name         parent          rate            enabled */
98         { "pll_m",              NULL,           0,              true},
99         { "hda",                "pll_p",        108000000,      false},
100         { "hda2codec_2x",       "pll_p",        48000000,       false},
101         { "pwm",                "clk_32k",      32768,          false},
102         { "blink",              "clk_32k",      32768,          true},
103         { "pll_a",              NULL,           552960000,      false},
104         { "pll_a_out0",         NULL,           12288000,       false},
105         { "d_audio",            "pll_a_out0",   12288000,       false},
106         { "nor",                "pll_p",        86500000,       true},
107         { "uarta",              "pll_p",        480000000,      true},
108         { "uarte",              "pll_p",        480000000,      true},
109         { "sdmmc2",             "pll_p",        52000000,       true},
110         { "sbc1",               "pll_m",        100000000,      true},
111         { "sbc2",               "pll_m",        100000000,      true},
112         { "sbc3",               "pll_m",        100000000,      true},
113         { "sbc4",               "pll_m",        100000000,      true},
114         { "sbc5",               "pll_m",        100000000,      true},
115         { "sbc6",               "pll_m",        100000000,      true},
116         { "cpu_g",              "cclk_g",       900000000,      true},
117         { "i2s0",               "pll_a_out0",   12288000,       false},
118         { "i2s1",               "pll_a_out0",   12288000,       false},
119         { "i2s2",               "pll_a_out0",   12288000,       false},
120         { "i2s3",               "pll_a_out0",   12288000,       false},
121         { "i2s4",               "pll_a_out0",   12288000,       false},
122         { "audio0",             "i2s0_sync",    12288000,       false},
123         { "audio1",             "i2s1_sync",    12288000,       false},
124         { "audio2",             "i2s2_sync",    12288000,       false},
125         { "audio3",             "i2s3_sync",    12288000,       false},
126         { "audio4",             "i2s4_sync",    12288000,       false},
127         { "apbif",              "clk_m",        12000000,       false},
128         { "dam0",               "clk_m",        12000000,       true},
129         { "dam1",               "clk_m",        12000000,       true},
130         { "dam2",               "clk_m",        12000000,       true},
131         { "vi",                 "pll_p",        470000000,      false},
132         { "vi_sensor",          "pll_p",        150000000,      false},
133         { "vde",                "pll_c",        484000000,      true},
134         { "host1x",             "pll_c",        242000000,      true},
135         { "mpe",                "pll_c",        484000000,      true},
136         { "se",                 "pll_m",        625000000,      true},
137         { "i2c1",               "pll_p",        3200000,        true},
138         { "i2c2",               "pll_p",        3200000,        true},
139         { "i2c3",               "pll_p",        3200000,        true},
140         { "i2c4",               "pll_p",        3200000,        true},
141         { "i2c5",               "pll_p",        3200000,        true},
142         { "sdmmc2",             "pll_p",        104000000,      false},
143         { NULL,                 NULL,           0,              0},
144 };
145
146 static struct tegra_i2c_platform_data p1852_i2c1_platform_data = {
147         .adapter_nr     = 0,
148         .bus_count      = 1,
149         .bus_clk_rate   = { 100000, 0 },
150 };
151
152 static struct tegra_i2c_platform_data p1852_i2c2_platform_data = {
153         .adapter_nr     = 1,
154         .bus_count      = 1,
155         .bus_clk_rate   = { 100000, 0 },
156         .is_clkon_always = true,
157 };
158
159 static struct tegra_i2c_platform_data p1852_i2c4_platform_data = {
160         .adapter_nr     = 3,
161         .bus_count      = 1,
162         .bus_clk_rate   = { 100000, 0 },
163 };
164
165 static struct tegra_i2c_platform_data p1852_i2c5_platform_data = {
166         .adapter_nr     = 4,
167         .bus_count      = 1,
168         .bus_clk_rate   = { 100000, 0 },
169 };
170
171 static struct tegra_pci_platform_data p1852_pci_platform_data = {
172         .port_status[0] = 0,
173         .port_status[1] = 1,
174         .port_status[2] = 1,
175         .use_dock_detect = 0,
176         .gpio           = 0,
177 };
178
179 static void p1852_pcie_init(void)
180 {
181         tegra_pci_device.dev.platform_data = &p1852_pci_platform_data;
182         platform_device_register(&tegra_pci_device);
183 }
184
185 static void p1852_i2c_init(void)
186 {
187         tegra_i2c_device1.dev.platform_data = &p1852_i2c1_platform_data;
188         tegra_i2c_device2.dev.platform_data = &p1852_i2c2_platform_data;
189         tegra_i2c_device4.dev.platform_data = &p1852_i2c4_platform_data;
190         tegra_i2c_device5.dev.platform_data = &p1852_i2c5_platform_data;
191
192         platform_device_register(&tegra_i2c_device5);
193         platform_device_register(&tegra_i2c_device4);
194         platform_device_register(&tegra_i2c_device2);
195         platform_device_register(&tegra_i2c_device1);
196 }
197
198 static struct platform_device *p1852_uart_devices[] __initdata = {
199         &tegra_uarta_device,
200         &tegra_uartb_device,
201         &tegra_uarte_device,
202 };
203 static struct clk *debug_uart_clk;
204
205 static void __init uart_debug_init(void)
206 {
207         /* Use skuinfo to decide debug uart */
208         /* UARTB is the debug port. */
209         pr_info("Selecting UARTB as the debug console\n");
210         p1852_uart_devices[1] = &debug_uartb_device;
211         debug_uart_clk = clk_get_sys("serial8250.0", "uartb");
212 }
213
214 static void __init p1852_uart_init(void)
215 {
216         /* Register low speed only if it is selected */
217         if (!is_tegra_debug_uartport_hs()) {
218                 uart_debug_init();
219                 /* Clock enable for the debug channel */
220                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
221                         pr_info("The debug console clock name is %s\n",
222                                                 debug_uart_clk->name);
223                         clk_enable(debug_uart_clk);
224                         clk_set_rate(debug_uart_clk, 408000000);
225                 } else {
226                         pr_err("Not getting the clock %s for debug console\n",
227                                         debug_uart_clk->name);
228                 }
229         }
230
231         platform_add_devices(p1852_uart_devices,
232                                 ARRAY_SIZE(p1852_uart_devices));
233 }
234
235 static struct tegra_p1852_platform_data p1852_audio_pdata = {
236         .codec_info[0] = {
237                 .codec_dai_name = "dit-hifi",
238                 .cpu_dai_name = "tegra30-i2s.0",
239                 .codec_name = "spdif-dit.0",
240                 .name = "tegra-i2s-1",
241                 .i2s_format = format_i2s,
242                 .master = 1,
243         },
244         .codec_info[1] = {
245                 .codec_dai_name = "dit-hifi",
246                 .cpu_dai_name = "tegra30-i2s.1",
247                 .codec_name = "spdif-dit.1",
248                 .name = "tegra-i2s-2",
249                 .i2s_format = format_i2s,
250                 .master = 0,
251         },
252
253 };
254
255 static struct platform_device generic_codec_1 = {
256         .name           = "spdif-dit",
257         .id                     = 0,
258 };
259 static struct platform_device generic_codec_2 = {
260         .name           = "spdif-dit",
261         .id                     = 1,
262 };
263
264 static struct platform_device tegra_snd_p1852 = {
265         .name       = "tegra-snd-p1852",
266         .id = 0,
267         .dev    = {
268             .platform_data = &p1852_audio_pdata,
269         },
270 };
271
272 static void p1852_i2s_audio_init(void)
273 {
274         platform_device_register(&tegra_pcm_device);
275         platform_device_register(&generic_codec_1);
276         platform_device_register(&generic_codec_2);
277         platform_device_register(&tegra_i2s_device0);
278         platform_device_register(&tegra_i2s_device1);
279         platform_device_register(&tegra_ahub_device);
280         platform_device_register(&tegra_snd_p1852);
281 }
282
283
284 #if defined(CONFIG_SPI_TEGRA) && defined(CONFIG_SPI_SPIDEV)
285 static struct spi_board_info tegra_spi_devices[] __initdata = {
286         {
287                 .modalias = "spidev",
288                 .bus_num = 0,
289                 .chip_select = 0,
290                 .mode = SPI_MODE_0,
291                 .max_speed_hz = 18000000,
292                 .platform_data = NULL,
293                 .irq = 0,
294         },
295         {
296                 .modalias = "spidev",
297                 .bus_num = 1,
298                 .chip_select = 1,
299                 .mode = SPI_MODE_0,
300                 .max_speed_hz = 18000000,
301                 .platform_data = NULL,
302                 .irq = 0,
303         },
304         {
305                 .modalias = "spidev",
306                 .bus_num = 3,
307                 .chip_select = 1,
308                 .mode = SPI_MODE_0,
309                 .max_speed_hz = 18000000,
310                 .platform_data = NULL,
311                 .irq = 0,
312         },
313 };
314
315 static void __init p852_register_spidev(void)
316 {
317         spi_register_board_info(tegra_spi_devices,
318                         ARRAY_SIZE(tegra_spi_devices));
319 }
320 #else
321 #define p852_register_spidev() do {} while (0)
322 #endif
323
324
325 static void p1852_spi_init(void)
326 {
327         tegra_spi_device2.name = "spi_slave_tegra";
328         platform_device_register(&tegra_spi_device1);
329         platform_device_register(&tegra_spi_device2);
330         platform_device_register(&tegra_spi_device4);
331         p852_register_spidev();
332 }
333
334 static struct platform_device *p1852_devices[] __initdata = {
335 #if defined(CONFIG_TEGRA_IOVMM_SMMU)
336         &tegra_smmu_device,
337 #endif
338 #if defined(CONFIG_TEGRA_AVP)
339         &tegra_avp_device,
340 #endif
341 };
342
343 static struct usb_phy_plat_data tegra_usb_phy_pdata[] = {
344         [0] = {
345                         .instance = 0,
346                         .vbus_gpio = -1,
347                         .vbus_reg_supply = NULL,
348         },
349         [1] = {
350                         .instance = 1,
351                         .vbus_gpio = -1,
352         },
353         [2] = {
354                         .instance = 2,
355                         .vbus_gpio = -1,
356                         .vbus_reg_supply = NULL,
357         },
358 };
359
360 static struct tegra_ehci_platform_data tegra_ehci_pdata[] = {
361         [0] = {
362                         .phy_config = &utmi_phy_config[0],
363                         .operating_mode = TEGRA_USB_HOST,
364                         .power_down_on_bus_suspend = 1,
365         },
366         [1] = {
367                         .phy_config = &utmi_phy_config[1],
368                         .operating_mode = TEGRA_USB_HOST,
369                         .power_down_on_bus_suspend = 1,
370         },
371         [2] = {
372                         .phy_config = &utmi_phy_config[2],
373                         .operating_mode = TEGRA_USB_HOST,
374                         .power_down_on_bus_suspend = 1,
375         },
376 };
377
378 static void p1852_usb_init(void)
379 {
380         /* Need to parse sku info to decide host/device mode */
381         tegra_usb_phy_init(tegra_usb_phy_pdata,
382                                 ARRAY_SIZE(tegra_usb_phy_pdata));
383
384         tegra_ehci1_device.dev.platform_data = &tegra_ehci_pdata[0];
385         platform_device_register(&tegra_ehci1_device);
386
387         tegra_ehci2_device.dev.platform_data = &tegra_ehci_pdata[1];
388         platform_device_register(&tegra_ehci2_device);
389
390         tegra_ehci3_device.dev.platform_data = &tegra_ehci_pdata[2];
391         platform_device_register(&tegra_ehci3_device);
392
393 }
394
395 static struct tegra_nor_platform_data p1852_nor_data = {
396         .flash = {
397                 .map_name = "cfi_probe",
398                 .width = 2,
399         },
400         .chip_parms = {
401                 /* FIXME: Need to use characterized value */
402                 .timing_default = {
403                         .timing0 = 0xA0400273,
404                         .timing1 = 0x00030402,
405                 },
406                 .timing_read = {
407                         .timing0 = 0xA0400273,
408                         .timing1 = 0x00030402,
409                 },
410         },
411 };
412
413 static void p1852_nor_init(void)
414 {
415         tegra_nor_device.resource[2].end = TEGRA_NOR_FLASH_BASE + SZ_64M - 1;
416         tegra_nor_device.dev.platform_data = &p1852_nor_data;
417         platform_device_register(&tegra_nor_device);
418 }
419
420 static void __init tegra_p1852_init(void)
421 {
422         tegra_init_board_info();
423         tegra_clk_init_from_table(p1852_clk_init_table);
424         tegra_enable_pinmux();
425         p1852_pinmux_init();
426         p1852_i2c_init();
427         p1852_i2s_audio_init();
428         p1852_gpio_init();
429         p1852_uart_init();
430         p1852_usb_init();
431         p1852_sdhci_init();
432         p1852_spi_init();
433         platform_add_devices(p1852_devices, ARRAY_SIZE(p1852_devices));
434         p1852_panel_init();
435         p1852_nor_init();
436         p1852_pcie_init();
437 }
438
439 static void __init tegra_p1852_reserve(void)
440 {
441 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
442         tegra_reserve(0, SZ_8M, 0);
443 #else
444         tegra_reserve(SZ_128M, SZ_8M, 0);
445 #endif
446 }
447
448 MACHINE_START(P1852, "p1852")
449         .boot_params    = 0x80000100,
450         .init_irq       = tegra_init_irq,
451         .init_early     = tegra_init_early,
452         .init_machine   = tegra_p1852_init,
453         .map_io         = tegra_map_common_io,
454         .reserve        = tegra_p1852_reserve,
455         .timer          = &tegra_timer,
456 MACHINE_END