ARM: tegra3: usb: USB1_UTMIP_XCVR_CFG0_0 value changed
[linux-2.6.git] / arch / arm / mach-tegra / board-p1852.c
1 /*
2  * arch/arm/mach-tegra/board-p1852.c
3  *
4  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  *
18  */
19
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/slab.h>
23 #include <linux/ctype.h>
24 #include <linux/platform_device.h>
25 #include <linux/clk.h>
26 #include <linux/serial_8250.h>
27 #include <linux/i2c.h>
28 #include <linux/i2c/panjit_ts.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/delay.h>
31 #include <linux/i2c-tegra.h>
32 #include <linux/gpio.h>
33 #include <linux/input.h>
34 #include <linux/platform_data/tegra_usb.h>
35 #include <linux/platform_data/tegra_nor.h>
36 #include <linux/spi/spi.h>
37 #include <linux/mtd/partitions.h>
38 #include <mach/clk.h>
39 #include <mach/iomap.h>
40 #include <mach/irqs.h>
41 #include <mach/pinmux.h>
42 #include <mach/iomap.h>
43 #include <mach/io.h>
44 #include <mach/pci.h>
45 #include <mach/audio.h>
46 #include <mach/tegra_p1852_pdata.h>
47 #include <asm/mach/flash.h>
48 #include <asm/mach-types.h>
49 #include <asm/mach/arch.h>
50 #include <mach/usb_phy.h>
51 #include <sound/wm8903.h>
52 #include <mach/tsensor.h>
53 #include "board.h"
54 #include "clock.h"
55 #include "board-p1852.h"
56 #include "devices.h"
57 #include "gpio-names.h"
58 #include "fuse.h"
59
60 static __initdata struct tegra_clk_init_table p1852_clk_init_table[] = {
61         /* name         parent          rate            enabled */
62         { "pll_m",              NULL,           0,              true},
63         { "hda",                "pll_p",        108000000,      false},
64         { "hda2codec_2x",       "pll_p",        48000000,       false},
65         { "pwm",                "clk_32k",      32768,          false},
66         { "blink",              "clk_32k",      32768,          true},
67         { "pll_a",              NULL,           552960000,      false},
68         /* audio cif clock should be faster than i2s */
69         { "pll_a_out0",         NULL,           24576000,       false},
70         { "d_audio",            "pll_a_out0",   24576000,       false},
71         { "nor",                "pll_p",        86500000,       true},
72         { "uarta",              "pll_p",        480000000,      true},
73         { "uartd",              "pll_p",        480000000,      true},
74         { "uarte",              "pll_p",        480000000,      true},
75         { "sdmmc2",             "pll_p",        52000000,       true},
76         { "sbc1",               "pll_m",        100000000,      true},
77         { "sbc2",               "pll_m",        100000000,      true},
78         { "sbc3",               "pll_m",        100000000,      true},
79         { "sbc4",               "pll_m",        100000000,      true},
80         { "sbc5",               "pll_m",        100000000,      true},
81         { "sbc6",               "pll_m",        100000000,      true},
82         { "cpu_g",              "cclk_g",       900000000,      true},
83         { "i2s0",               "pll_a_out0",   24576000,       false},
84         { "i2s1",               "pll_a_out0",   24576000,       false},
85         { "i2s2",               "pll_a_out0",   24576000,       false},
86         { "i2s3",               "pll_a_out0",   24576000,       false},
87         { "i2s4",               "pll_a_out0",   24576000,       false},
88         { "audio0",             "i2s0_sync",    12288000,       false},
89         { "audio1",             "i2s1_sync",    12288000,       false},
90         { "audio2",             "i2s2_sync",    12288000,       false},
91         { "audio3",             "i2s3_sync",    12288000,       false},
92         { "audio4",             "i2s4_sync",    12288000,       false},
93         { "apbif",              "clk_m",        12000000,       false},
94         { "dam0",               "clk_m",        12000000,       true},
95         { "dam1",               "clk_m",        12000000,       true},
96         { "dam2",               "clk_m",        12000000,       true},
97         { "vi",                 "pll_p",        470000000,      false},
98         { "vi_sensor",          "pll_p",        150000000,      false},
99         { "vde",                "pll_c",        484000000,      true},
100         { "host1x",             "pll_c",        242000000,      true},
101         { "mpe",                "pll_c",        484000000,      true},
102         { "se",                 "pll_m",        625000000,      true},
103         { "i2c1",               "pll_p",        3200000,        true},
104         { "i2c2",               "pll_p",        3200000,        true},
105         { "i2c3",               "pll_p",        3200000,        true},
106         { "i2c4",               "pll_p",        3200000,        true},
107         { "i2c5",               "pll_p",        3200000,        true},
108         { "sdmmc2",             "pll_p",        104000000,      false},
109         {"wake.sclk",           NULL,           334000000,      true },
110         { NULL,                 NULL,           0,              0},
111 };
112
113 static struct tegra_i2c_platform_data p1852_i2c1_platform_data = {
114         .adapter_nr     = 0,
115         .bus_count      = 1,
116         .bus_clk_rate   = { 100000, 0 },
117 };
118
119 static struct tegra_i2c_platform_data p1852_i2c2_platform_data = {
120         .adapter_nr     = 1,
121         .bus_count      = 1,
122         .bus_clk_rate   = { 100000, 0 },
123         .is_clkon_always = true,
124 };
125
126 static struct tegra_i2c_platform_data p1852_i2c4_platform_data = {
127         .adapter_nr     = 3,
128         .bus_count      = 1,
129         .bus_clk_rate   = { 100000, 0 },
130 };
131
132 static struct tegra_i2c_platform_data p1852_i2c5_platform_data = {
133         .adapter_nr     = 4,
134         .bus_count      = 1,
135         .bus_clk_rate   = { 100000, 0 },
136 };
137
138 static struct tegra_pci_platform_data p1852_pci_platform_data = {
139         .port_status[0] = 0,
140         .port_status[1] = 1,
141         .port_status[2] = 1,
142         .use_dock_detect = 0,
143         .gpio           = 0,
144 };
145
146 static void p1852_pcie_init(void)
147 {
148         tegra_pci_device.dev.platform_data = &p1852_pci_platform_data;
149         platform_device_register(&tegra_pci_device);
150 }
151
152 static void p1852_i2c_init(void)
153 {
154         tegra_i2c_device1.dev.platform_data = &p1852_i2c1_platform_data;
155         tegra_i2c_device2.dev.platform_data = &p1852_i2c2_platform_data;
156         tegra_i2c_device4.dev.platform_data = &p1852_i2c4_platform_data;
157         tegra_i2c_device5.dev.platform_data = &p1852_i2c5_platform_data;
158
159         platform_device_register(&tegra_i2c_device5);
160         platform_device_register(&tegra_i2c_device4);
161         platform_device_register(&tegra_i2c_device2);
162         platform_device_register(&tegra_i2c_device1);
163 }
164
165 static struct platform_device *p1852_uart_devices[] __initdata = {
166         &tegra_uarta_device,
167         &tegra_uartb_device,
168         &tegra_uartd_device,
169         &tegra_uarte_device,
170 };
171 static struct clk *debug_uart_clk;
172
173 static void __init uart_debug_init(void)
174 {
175         /* Use skuinfo to decide debug uart */
176         /* UARTB is the debug port. */
177         pr_info("Selecting UARTB as the debug console\n");
178         p1852_uart_devices[1] = &debug_uartb_device;
179         debug_uart_clk = clk_get_sys("serial8250.0", "uartb");
180 }
181
182 static void __init p1852_uart_init(void)
183 {
184         /* Register low speed only if it is selected */
185         if (!is_tegra_debug_uartport_hs()) {
186                 uart_debug_init();
187                 /* Clock enable for the debug channel */
188                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
189                         pr_info("The debug console clock name is %s\n",
190                                                 debug_uart_clk->name);
191                         clk_enable(debug_uart_clk);
192                         clk_set_rate(debug_uart_clk, 408000000);
193                 } else {
194                         pr_err("Not getting the clock %s for debug console\n",
195                                         debug_uart_clk->name);
196                 }
197         }
198
199         platform_add_devices(p1852_uart_devices,
200                                 ARRAY_SIZE(p1852_uart_devices));
201 }
202
203 #if defined(CONFIG_TEGRA_P1852_TDM)
204 static struct tegra_p1852_platform_data p1852_audio_tdm_pdata = {
205         .codec_info[0] = {
206                 .codec_dai_name = "dit-hifi",
207                 .cpu_dai_name = "tegra30-i2s.0",
208                 .codec_name = "spdif-dit.0",
209                 .name = "tegra-i2s-1",
210                 .pcm_driver = "tegra-tdm-pcm-audio",
211                 .i2s_format = format_tdm,
212                 .master = 1,
213                 .num_slots = 4,
214                 .slot_width = 32,
215                 .tx_mask = 0x0f,
216                 .rx_mask = 0x0f,
217         },
218         .codec_info[1] = {
219                 .codec_dai_name = "dit-hifi",
220                 .cpu_dai_name = "tegra30-i2s.4",
221                 .codec_name = "spdif-dit.1",
222                 .name = "tegra-i2s-2",
223                 .pcm_driver = "tegra-tdm-pcm-audio",
224                 .i2s_format = format_tdm,
225                 .master = 1,
226                 .num_slots = 8,
227                 .slot_width = 32,
228                 .tx_mask = 0xff,
229                 .rx_mask = 0xff,
230         },
231 };
232 #else
233 static struct tegra_p1852_platform_data p1852_audio_i2s_pdata = {
234         .codec_info[0] = {
235                 .codec_dai_name = "dit-hifi",
236                 .cpu_dai_name = "tegra30-i2s.0",
237                 .codec_name = "spdif-dit.0",
238                 .name = "tegra-i2s-1",
239                 .pcm_driver = "tegra-pcm-audio",
240                 .i2s_format = format_i2s,
241                 .master = 1,
242         },
243         .codec_info[1] = {
244                 .codec_dai_name = "dit-hifi",
245                 .cpu_dai_name = "tegra30-i2s.4",
246                 .codec_name = "spdif-dit.1",
247                 .name = "tegra-i2s-2",
248                 .pcm_driver = "tegra-pcm-audio",
249                 .i2s_format = format_i2s,
250                 .master = 0,
251         },
252 };
253 #endif
254 static struct platform_device generic_codec_1 = {
255         .name           = "spdif-dit",
256         .id                     = 0,
257 };
258 static struct platform_device generic_codec_2 = {
259         .name           = "spdif-dit",
260         .id                     = 1,
261 };
262
263 static struct platform_device tegra_snd_p1852 = {
264         .name       = "tegra-snd-p1852",
265         .id = 0,
266         .dev    = {
267 #if defined(CONFIG_TEGRA_P1852_TDM)
268                 .platform_data = &p1852_audio_tdm_pdata,
269 #else
270                 .platform_data = &p1852_audio_i2s_pdata,
271 #endif
272         },
273 };
274
275 static void p1852_i2s_audio_init(void)
276 {
277         platform_device_register(&tegra_pcm_device);
278         platform_device_register(&tegra_tdm_pcm_device);
279         platform_device_register(&generic_codec_1);
280         platform_device_register(&generic_codec_2);
281         platform_device_register(&tegra_i2s_device0);
282         platform_device_register(&tegra_i2s_device4);
283         platform_device_register(&tegra_ahub_device);
284         platform_device_register(&tegra_snd_p1852);
285 }
286
287
288 #if defined(CONFIG_SPI_TEGRA) && defined(CONFIG_SPI_SPIDEV)
289 static struct spi_board_info tegra_spi_devices[] __initdata = {
290         {
291                 .modalias = "spidev",
292                 .bus_num = 0,
293                 .chip_select = 0,
294                 .mode = SPI_MODE_0,
295                 .max_speed_hz = 18000000,
296                 .platform_data = NULL,
297                 .irq = 0,
298         },
299         {
300                 .modalias = "spidev",
301                 .bus_num = 1,
302                 .chip_select = 1,
303                 .mode = SPI_MODE_0,
304                 .max_speed_hz = 18000000,
305                 .platform_data = NULL,
306                 .irq = 0,
307         },
308         {
309                 .modalias = "spidev",
310                 .bus_num = 3,
311                 .chip_select = 1,
312                 .mode = SPI_MODE_0,
313                 .max_speed_hz = 18000000,
314                 .platform_data = NULL,
315                 .irq = 0,
316         },
317 };
318
319 static void __init p852_register_spidev(void)
320 {
321         spi_register_board_info(tegra_spi_devices,
322                         ARRAY_SIZE(tegra_spi_devices));
323 }
324 #else
325 #define p852_register_spidev() do {} while (0)
326 #endif
327
328
329 static void p1852_spi_init(void)
330 {
331         tegra_spi_device2.name = "spi_slave_tegra";
332         platform_device_register(&tegra_spi_device1);
333         platform_device_register(&tegra_spi_device2);
334         p852_register_spidev();
335 }
336
337 static struct platform_device tegra_camera = {
338         .name = "tegra_camera",
339         .id = -1,
340 };
341
342 static struct platform_device *p1852_devices[] __initdata = {
343 #if defined(CONFIG_TEGRA_IOVMM_SMMU)
344         &tegra_smmu_device,
345 #endif
346 #if defined(CONFIG_TEGRA_AVP)
347         &tegra_avp_device,
348 #endif
349         &tegra_camera,
350         &tegra_wdt_device
351 };
352
353 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
354         .port_otg = false,
355         .has_hostpc = true,
356         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
357         .op_mode = TEGRA_USB_OPMODE_HOST,
358         .u_data.host = {
359                 .vbus_gpio = -1,
360                 .vbus_reg = NULL,
361                 .hot_plug = false,
362                 .remote_wakeup_supported = true,
363                 .power_off_on_suspend = true,
364         },
365         .u_cfg.utmi = {
366                 .hssync_start_delay = 0,
367                 .idle_wait_delay = 17,
368                 .elastic_limit = 16,
369                 .term_range_adj = 6,
370                 .xcvr_setup = 63,
371                 .xcvr_setup_offset = 6,
372                 .xcvr_use_fuses = 1,
373                 .xcvr_lsfslew = 2,
374                 .xcvr_lsrslew = 2,
375                 .xcvr_use_lsb = 1,
376         },
377 };
378
379 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
380         .port_otg = false,
381         .has_hostpc = true,
382         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
383         .op_mode = TEGRA_USB_OPMODE_HOST,
384         .u_data.host = {
385                 .vbus_gpio = -1,
386                 .vbus_reg = NULL,
387                 .hot_plug = false,
388                 .remote_wakeup_supported = true,
389                 .power_off_on_suspend = true,
390         },
391         .u_cfg.utmi = {
392                 .hssync_start_delay = 0,
393                 .idle_wait_delay = 17,
394                 .elastic_limit = 16,
395                 .term_range_adj = 6,
396                 .xcvr_setup = 63,
397                 .xcvr_setup_offset = 6,
398                 .xcvr_use_fuses = 1,
399                 .xcvr_lsfslew = 2,
400                 .xcvr_lsrslew = 2,
401                 .xcvr_use_lsb = 1,
402         },
403 };
404
405 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
406         .port_otg = false,
407         .has_hostpc = true,
408         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
409         .op_mode = TEGRA_USB_OPMODE_HOST,
410         .u_data.host = {
411                 .vbus_gpio = -1,
412                 .vbus_reg = NULL,
413                 .hot_plug = false,
414                 .remote_wakeup_supported = true,
415                 .power_off_on_suspend = true,
416         },
417         .u_cfg.utmi = {
418                 .hssync_start_delay = 0,
419                 .idle_wait_delay = 17,
420                 .elastic_limit = 16,
421                 .term_range_adj = 6,
422                 .xcvr_setup = 63,
423                 .xcvr_setup_offset = 6,
424                 .xcvr_use_fuses = 1,
425                 .xcvr_lsfslew = 2,
426                 .xcvr_lsrslew = 2,
427                 .xcvr_use_lsb = 1,
428         },
429 };
430
431 static void p1852_usb_init(void)
432 {
433         tegra_ehci1_device.dev.platform_data = &tegra_ehci1_utmi_pdata;
434         platform_device_register(&tegra_ehci1_device);
435
436         tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata;
437         platform_device_register(&tegra_ehci2_device);
438
439         tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
440         platform_device_register(&tegra_ehci3_device);
441 }
442
443 static struct tegra_nor_platform_data p1852_nor_data = {
444         .flash = {
445                 .map_name = "cfi_probe",
446                 .width = 2,
447         },
448         .chip_parms = {
449                 /* FIXME: Need to use characterized value */
450                 .timing_default = {
451                         .timing0 = 0x30300263,
452                         .timing1 = 0x00030302,
453                 },
454                 .timing_read = {
455                         .timing0 = 0x30300263,
456                         .timing1 = 0x00030302,
457                 },
458         },
459 };
460
461 static void p1852_nor_init(void)
462 {
463         tegra_nor_device.resource[2].end = TEGRA_NOR_FLASH_BASE + SZ_64M - 1;
464         tegra_nor_device.dev.platform_data = &p1852_nor_data;
465         platform_device_register(&tegra_nor_device);
466 }
467
468 static void __init tegra_p1852_init(void)
469 {
470         tegra_init_board_info();
471         tegra_clk_init_from_table(p1852_clk_init_table);
472         tegra_enable_pinmux();
473         p1852_pinmux_init();
474         p1852_i2c_init();
475         p1852_i2s_audio_init();
476         p1852_gpio_init();
477         p1852_uart_init();
478         p1852_usb_init();
479         p1852_sdhci_init();
480         p1852_spi_init();
481         platform_add_devices(p1852_devices, ARRAY_SIZE(p1852_devices));
482         p1852_panel_init();
483         p1852_nor_init();
484         p1852_pcie_init();
485 }
486
487 static void __init tegra_p1852_reserve(void)
488 {
489 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
490         tegra_reserve(0, SZ_8M, 0);
491 #else
492         tegra_reserve(SZ_128M, SZ_8M, 0);
493 #endif
494 }
495
496 MACHINE_START(P1852, "p1852")
497         .boot_params    = 0x80000100,
498         .init_irq       = tegra_init_irq,
499         .init_early     = tegra_init_early,
500         .init_machine   = tegra_p1852_init,
501         .map_io         = tegra_map_common_io,
502         .reserve        = tegra_p1852_reserve,
503         .timer          = &tegra_timer,
504 MACHINE_END