e3c017431366876d3d0580b16a764d00b8d05a25
[linux-2.6.git] / arch / arm / mach-tegra / board-p1852.c
1 /*
2  * arch/arm/mach-tegra/board-p1852.c
3  *
4  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  *
18  */
19
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/slab.h>
23 #include <linux/ctype.h>
24 #include <linux/platform_device.h>
25 #include <linux/clk.h>
26 #include <linux/serial_8250.h>
27 #include <linux/i2c.h>
28 #include <linux/i2c/panjit_ts.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/delay.h>
31 #include <linux/i2c-tegra.h>
32 #include <linux/gpio.h>
33 #include <linux/input.h>
34 #include <linux/platform_data/tegra_usb.h>
35 #include <linux/platform_data/tegra_nor.h>
36 #include <linux/spi/spi.h>
37 #include <linux/mtd/partitions.h>
38 #if defined(CONFIG_TOUCHSCREEN_ATMEL_MXT)
39 #include <linux/i2c/atmel_mxt_ts.h>
40 #endif
41 #include <mach/clk.h>
42 #include <mach/iomap.h>
43 #include <mach/irqs.h>
44 #include <mach/pinmux.h>
45 #include <mach/iomap.h>
46 #include <mach/io_dpd.h>
47 #include <mach/io.h>
48 #include <mach/pci.h>
49 #include <mach/audio.h>
50 #include <mach/tegra_p1852_pdata.h>
51 #include <asm/mach/flash.h>
52 #include <asm/mach-types.h>
53 #include <asm/mach/arch.h>
54 #include <mach/usb_phy.h>
55 #include <mach/tegra_fiq_debugger.h>
56 #include <sound/wm8903.h>
57 #include <mach/tsensor.h>
58 #include "board.h"
59 #include "clock.h"
60 #include "board-p1852.h"
61 #include "devices.h"
62 #include "gpio-names.h"
63 #include "fuse.h"
64 #include "common.h"
65
66 static __initdata struct tegra_clk_init_table p1852_clk_init_table[] = {
67         /* name         parent          rate            enabled */
68         { "pll_m",              NULL,           0,              true},
69         { "hda",                "pll_p",        108000000,      false},
70         { "hda2codec_2x",       "pll_p",        48000000,       false},
71         { "pwm",                "clk_32k",      32768,          false},
72         { "blink",              "clk_32k",      32768,          true},
73         { "pll_a",              NULL,           552960000,      false},
74         /* audio cif clock should be faster than i2s */
75         { "pll_a_out0",         NULL,           24576000,       false},
76         { "d_audio",            "pll_a_out0",   24576000,       false},
77         { "nor",                "pll_p",        102000000,      true},
78         { "uarta",              "pll_p",        480000000,      true},
79         { "uartd",              "pll_p",        480000000,      true},
80         { "uarte",              "pll_p",        480000000,      true},
81         { "sdmmc2",             "pll_p",        52000000,       true},
82         { "sbc1",               "pll_m",        100000000,      true},
83         { "sbc2",               "pll_m",        100000000,      true},
84         { "sbc3",               "pll_m",        100000000,      true},
85         { "sbc4",               "pll_m",        100000000,      true},
86         { "sbc5",               "pll_m",        100000000,      true},
87         { "sbc6",               "pll_m",        100000000,      true},
88         { "cpu_g",              "cclk_g",       900000000,      true},
89         { "i2s0",               "pll_a_out0",   24576000,       false},
90         { "i2s1",               "pll_a_out0",   24576000,       false},
91         { "i2s2",               "pll_a_out0",   24576000,       false},
92         { "i2s3",               "pll_a_out0",   24576000,       false},
93         { "i2s4",               "pll_a_out0",   24576000,       false},
94         { "apbif",              "clk_m",        12000000,       false},
95         { "dam0",               "clk_m",        12000000,       true},
96         { "dam1",               "clk_m",        12000000,       true},
97         { "dam2",               "clk_m",        12000000,       true},
98         { "vi",                 "pll_p",        470000000,      false},
99         { "vi_sensor",          "pll_p",        150000000,      false},
100         { "vde",                "pll_c",        484000000,      true},
101         { "mpe",                "pll_c",        484000000,      true},
102         { "se",                 "pll_m",        625000000,      true},
103         { "i2c1",               "pll_p",        3200000,        true},
104         { "i2c2",               "pll_p",        3200000,        true},
105         { "i2c3",               "pll_p",        3200000,        true},
106         { "i2c4",               "pll_p",        3200000,        true},
107         { "i2c5",               "pll_p",        3200000,        true},
108         { "sdmmc2",             "pll_p",        104000000,      false},
109         {"wake.sclk",           NULL,           334000000,      true },
110         { NULL,                 NULL,           0,              0},
111 };
112
113 static struct tegra_i2c_platform_data p1852_i2c1_platform_data = {
114         .adapter_nr     = 0,
115         .bus_count      = 1,
116         .bus_clk_rate   = { 100000, 0 },
117 };
118
119 static struct tegra_i2c_platform_data p1852_i2c2_platform_data = {
120         .adapter_nr     = 1,
121         .bus_count      = 1,
122         .bus_clk_rate   = { 100000, 0 },
123         .is_clkon_always = true,
124 };
125
126 static struct tegra_i2c_platform_data p1852_i2c4_platform_data = {
127         .adapter_nr     = 3,
128         .bus_count      = 1,
129         .bus_clk_rate   = { 100000, 0 },
130 };
131
132 static struct tegra_i2c_platform_data p1852_i2c5_platform_data = {
133         .adapter_nr     = 4,
134         .bus_count      = 1,
135         .bus_clk_rate   = { 100000, 0 },
136 };
137
138 static struct tegra_pci_platform_data p1852_pci_platform_data = {
139         .port_status[0] = 0,
140         .port_status[1] = 1,
141         .port_status[2] = 1,
142         .use_dock_detect = 0,
143         .gpio           = 0,
144 };
145
146 static void p1852_pcie_init(void)
147 {
148         tegra_pci_device.dev.platform_data = &p1852_pci_platform_data;
149         platform_device_register(&tegra_pci_device);
150 }
151
152 static void p1852_i2c_init(void)
153 {
154         tegra_i2c_device1.dev.platform_data = &p1852_i2c1_platform_data;
155         tegra_i2c_device2.dev.platform_data = &p1852_i2c2_platform_data;
156         tegra_i2c_device4.dev.platform_data = &p1852_i2c4_platform_data;
157         tegra_i2c_device5.dev.platform_data = &p1852_i2c5_platform_data;
158
159         platform_device_register(&tegra_i2c_device5);
160         platform_device_register(&tegra_i2c_device4);
161         platform_device_register(&tegra_i2c_device2);
162         platform_device_register(&tegra_i2c_device1);
163 }
164
165 static struct platform_device *p1852_uart_devices[] __initdata = {
166         &tegra_uarta_device,
167         &tegra_uartb_device,
168         &tegra_uartd_device,
169         &tegra_uarte_device,
170 };
171 static struct clk *debug_uart_clk;
172
173 static void __init uart_debug_init(void)
174 {
175         /* Use skuinfo to decide debug uart */
176         /* UARTB is the debug port. */
177         pr_info("Selecting UARTB as the debug console\n");
178         p1852_uart_devices[1] = &debug_uartb_device;
179         debug_uart_clk = clk_get_sys("serial8250.0", "uartb");
180 }
181
182 static void __init p1852_uart_init(void)
183 {
184         /* Register low speed only if it is selected */
185         if (!is_tegra_debug_uartport_hs()) {
186                 uart_debug_init();
187                 /* Clock enable for the debug channel */
188                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
189                         pr_info("The debug console clock name is %s\n",
190                                                 debug_uart_clk->name);
191                         clk_enable(debug_uart_clk);
192                         clk_set_rate(debug_uart_clk, 408000000);
193                 } else {
194                         pr_err("Not getting the clock %s for debug console\n",
195                                         debug_uart_clk->name);
196                 }
197         }
198
199         platform_add_devices(p1852_uart_devices,
200                                 ARRAY_SIZE(p1852_uart_devices));
201 }
202 #if defined(CONFIG_TEGRA_P1852_TDM)
203 static struct tegra_p1852_platform_data p1852_audio_tdm_pdata = {
204         .codec_info[0] = {
205                 .codec_dai_name = "dit-hifi",
206                 .cpu_dai_name = "tegra30-i2s.0",
207                 .codec_name = "spdif-dit.0",
208                 .name = "tegra-i2s-1",
209                 .pcm_driver = "tegra-tdm-pcm-audio",
210                 .i2s_format = format_tdm,
211                 /* Defines whether the Codec Chip is Master or Slave */
212                 .master = 1,
213                 /* Defines the number of TDM slots */
214                 .num_slots = 8,
215                 /* Defines the width of each slot */
216                 .slot_width = 32,
217                 /* Defines which slots are enabled */
218                 .tx_mask = 0xff,
219                 .rx_mask = 0xff,
220         },
221         .codec_info[1] = {
222                 .codec_dai_name = "dit-hifi",
223                 .cpu_dai_name = "tegra30-i2s.4",
224                 .codec_name = "spdif-dit.1",
225                 .name = "tegra-i2s-2",
226                 .pcm_driver = "tegra-tdm-pcm-audio",
227                 .i2s_format = format_tdm,
228                 .master = 1,
229                 .num_slots = 8,
230                 .slot_width = 32,
231                 .tx_mask = 0xff,
232                 .rx_mask = 0xff,
233         },
234 };
235 #else
236 static struct tegra_p1852_platform_data p1852_audio_i2s_pdata = {
237         .codec_info[0] = {
238                 .codec_dai_name = "dit-hifi",
239                 .cpu_dai_name = "tegra30-i2s.0",
240                 .codec_name = "spdif-dit.0",
241                 .name = "tegra-i2s-1",
242                 .pcm_driver = "tegra-pcm-audio",
243                 .i2s_format = format_i2s,
244                 /* Defines whether the Audio codec chip is master or slave */
245                 .master = 1,
246         },
247         .codec_info[1] = {
248                 .codec_dai_name = "dit-hifi",
249                 .cpu_dai_name = "tegra30-i2s.4",
250                 .codec_name = "spdif-dit.1",
251                 .name = "tegra-i2s-2",
252                 .pcm_driver = "tegra-pcm-audio",
253                 .i2s_format = format_i2s,
254                 /* Defines whether the Audio codec chip is master or slave */
255                 .master = 0,
256         },
257 };
258 #endif
259 static struct platform_device generic_codec_1 = {
260         .name           = "spdif-dit",
261         .id                     = 0,
262 };
263 static struct platform_device generic_codec_2 = {
264         .name           = "spdif-dit",
265         .id                     = 1,
266 };
267
268 static struct platform_device tegra_snd_p1852 = {
269         .name       = "tegra-snd-p1852",
270         .id = 0,
271         .dev    = {
272 #if defined(CONFIG_TEGRA_P1852_TDM)
273                 .platform_data = &p1852_audio_tdm_pdata,
274 #else
275                 .platform_data = &p1852_audio_i2s_pdata,
276 #endif
277         },
278 };
279
280 static void p1852_i2s_audio_init(void)
281 {
282         struct tegra_p1852_platform_data *pdata;
283
284         platform_device_register(&tegra_pcm_device);
285         platform_device_register(&tegra_tdm_pcm_device);
286         platform_device_register(&generic_codec_1);
287         platform_device_register(&generic_codec_2);
288         platform_device_register(&tegra_i2s_device0);
289         platform_device_register(&tegra_i2s_device4);
290         platform_device_register(&tegra_ahub_device);
291         platform_device_register(&tegra_snd_p1852);
292
293         /* Change pinmux of I2S4 for master mode */
294         pdata = tegra_snd_p1852.dev.platform_data;
295         if (!pdata->codec_info[1].master)
296                 p1852_pinmux_set_i2s4_master();
297 }
298
299
300 #if defined(CONFIG_SPI_TEGRA) && defined(CONFIG_SPI_SPIDEV)
301 static struct spi_board_info tegra_spi_devices[] __initdata = {
302         {
303                 .modalias = "spidev",
304                 .bus_num = 0,
305                 .chip_select = 0,
306                 .mode = SPI_MODE_0,
307                 .max_speed_hz = 18000000,
308                 .platform_data = NULL,
309                 .irq = 0,
310         },
311         {
312                 .modalias = "spidev",
313                 .bus_num = 1,
314                 .chip_select = 1,
315                 .mode = SPI_MODE_0,
316                 .max_speed_hz = 18000000,
317                 .platform_data = NULL,
318                 .irq = 0,
319         },
320         {
321                 .modalias = "spidev",
322                 .bus_num = 2,
323                 .chip_select = 0,
324                 .mode = SPI_MODE_0,
325                 .max_speed_hz = 18000000,
326                 .platform_data = NULL,
327                 .irq = 0,
328         },
329         {
330                 .modalias = "spidev",
331                 .bus_num = 3,
332                 .chip_select = 1,
333                 .mode = SPI_MODE_0,
334                 .max_speed_hz = 18000000,
335                 .platform_data = NULL,
336                 .irq = 0,
337         },
338 };
339
340 static void __init p852_register_spidev(void)
341 {
342         spi_register_board_info(tegra_spi_devices,
343                         ARRAY_SIZE(tegra_spi_devices));
344 }
345 #else
346 #define p852_register_spidev() do {} while (0)
347 #endif
348
349
350 static void p1852_spi_init(void)
351 {
352         tegra_spi_device2.name = "spi_slave_tegra";
353         platform_device_register(&tegra_spi_device1);
354         platform_device_register(&tegra_spi_device2);
355         platform_device_register(&tegra_spi_device3);
356         p852_register_spidev();
357 }
358
359 static struct platform_device tegra_camera = {
360         .name = "tegra_camera",
361         .id = -1,
362 };
363
364 static struct platform_device *p1852_devices[] __initdata = {
365 #if defined(CONFIG_TEGRA_IOVMM_SMMU) || defined(CONFIG_TEGRA_IOMMU_SMMU)
366         &tegra_smmu_device,
367 #endif
368 #if defined(CONFIG_TEGRA_AVP)
369         &tegra_avp_device,
370 #endif
371         &tegra_camera,
372         &tegra_wdt0_device,
373         &tegra_wdt1_device,
374         &tegra_wdt2_device
375 };
376
377
378 #ifdef CONFIG_TOUCHSCREEN_ATMEL_MXT
379
380 #define MXT_CONFIG_CRC  0xD62DE8
381 static const u8 config[] = {
382         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
383         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
384         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
385         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
386         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
387         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
388         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
389         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
390         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
391         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
392         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
393         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
394         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
395         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
396         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
397         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
398         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
399         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
400         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
401         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
402 };
403
404 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
405 static const u8 config_sku2000[] = {
406         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
407         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
408         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
409         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
410         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
411         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
412         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
413         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
414         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
415         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
416         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
417         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
418         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
419         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
420         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
421         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
422         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
423         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
424         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
425         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
426 };
427
428 static struct mxt_platform_data atmel_mxt_info = {
429         .x_line         = 27,
430         .y_line         = 42,
431         .x_size         = 768,
432         .y_size         = 1366,
433         .blen           = 0x20,
434         .threshold      = 0x3C,
435         .voltage        = 3300000,              /* 3.3V */
436         .orient         = 5,
437         .config         = config,
438         .config_length  = 157,
439         .config_crc     = MXT_CONFIG_CRC,
440         .irqflags       = IRQF_TRIGGER_FALLING,
441 /*      .read_chg       = &read_chg, */
442         .read_chg       = NULL,
443 };
444
445 static struct i2c_board_info __initdata atmel_i2c_info[] = {
446         {
447                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
448                 .irq = TEGRA_GPIO_TO_IRQ(TOUCH_GPIO_IRQ_ATMEL_T9),
449                 .platform_data = &atmel_mxt_info,
450         }
451 };
452
453 static __initdata struct tegra_clk_init_table spi_clk_init_table[] = {
454         /* name         parent          rate            enabled */
455         { "sbc1",       "pll_p",        52000000,       true},
456         { NULL,         NULL,           0,              0},
457 };
458
459 static int __init p1852_touch_init(void)
460 {
461         gpio_request(TOUCH_GPIO_IRQ_ATMEL_T9, "atmel-irq");
462         gpio_direction_input(TOUCH_GPIO_IRQ_ATMEL_T9);
463
464         gpio_request(TOUCH_GPIO_RST_ATMEL_T9, "atmel-reset");
465         gpio_direction_output(TOUCH_GPIO_RST_ATMEL_T9, 0);
466         msleep(1);
467         gpio_set_value(TOUCH_GPIO_RST_ATMEL_T9, 1);
468         msleep(100);
469
470         atmel_mxt_info.config = config_sku2000;
471         atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
472
473         i2c_register_board_info(TOUCH_BUS_ATMEL_T9, atmel_i2c_info, 1);
474
475         return 0;
476 }
477
478 #endif // CONFIG_TOUCHSCREEN_ATMEL_MXT
479
480 #if defined(CONFIG_USB_G_ANDROID)
481 static struct tegra_usb_platform_data tegra_udc_pdata = {
482         .port_otg = false,
483         .has_hostpc = true,
484         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
485         .op_mode = TEGRA_USB_OPMODE_DEVICE,
486         .u_data.dev = {
487                 .vbus_pmu_irq = 0,
488                 .vbus_gpio = -1,
489                 .charging_supported = false,
490                 .remote_wakeup_supported = false,
491         },
492         .u_cfg.utmi = {
493                 .hssync_start_delay = 0,
494                 .idle_wait_delay = 17,
495                 .elastic_limit = 16,
496                 .term_range_adj = 6,
497                 .xcvr_setup = 63,
498                 .xcvr_setup_offset = 6,
499                 .xcvr_use_fuses = 1,
500                 .xcvr_lsfslew = 2,
501                 .xcvr_lsrslew = 2,
502                 .xcvr_use_lsb = 1,
503         },
504 };
505 #else
506 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
507         .port_otg = false,
508         .has_hostpc = true,
509         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
510         .op_mode = TEGRA_USB_OPMODE_HOST,
511         .u_data.host = {
512                 .vbus_gpio = -1,
513                 .vbus_reg = NULL,
514                 .hot_plug = false,
515                 .remote_wakeup_supported = true,
516                 .power_off_on_suspend = true,
517         },
518         .u_cfg.utmi = {
519                 .hssync_start_delay = 0,
520                 .idle_wait_delay = 17,
521                 .elastic_limit = 16,
522                 .term_range_adj = 6,
523                 .xcvr_setup = 63,
524                 .xcvr_setup_offset = 6,
525                 .xcvr_use_fuses = 1,
526                 .xcvr_lsfslew = 2,
527                 .xcvr_lsrslew = 2,
528                 .xcvr_use_lsb = 1,
529         },
530 };
531 #endif
532
533 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
534         .port_otg = false,
535         .has_hostpc = true,
536         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
537         .op_mode = TEGRA_USB_OPMODE_HOST,
538         .u_data.host = {
539                 .vbus_gpio = -1,
540                 .vbus_reg = NULL,
541                 .hot_plug = false,
542                 .remote_wakeup_supported = true,
543                 .power_off_on_suspend = true,
544         },
545         .u_cfg.utmi = {
546                 .hssync_start_delay = 0,
547                 .idle_wait_delay = 17,
548                 .elastic_limit = 16,
549                 .term_range_adj = 6,
550                 .xcvr_setup = 63,
551                 .xcvr_setup_offset = 6,
552                 .xcvr_use_fuses = 1,
553                 .xcvr_lsfslew = 2,
554                 .xcvr_lsrslew = 2,
555                 .xcvr_use_lsb = 1,
556         },
557 };
558
559 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
560         .port_otg = false,
561         .has_hostpc = true,
562         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
563         .op_mode = TEGRA_USB_OPMODE_HOST,
564         .u_data.host = {
565                 .vbus_gpio = -1,
566                 .vbus_reg = NULL,
567                 .hot_plug = false,
568                 .remote_wakeup_supported = true,
569                 .power_off_on_suspend = true,
570         },
571         .u_cfg.utmi = {
572                 .hssync_start_delay = 0,
573                 .idle_wait_delay = 17,
574                 .elastic_limit = 16,
575                 .term_range_adj = 6,
576                 .xcvr_setup = 63,
577                 .xcvr_setup_offset = 6,
578                 .xcvr_use_fuses = 1,
579                 .xcvr_lsfslew = 2,
580                 .xcvr_lsrslew = 2,
581                 .xcvr_use_lsb = 1,
582         },
583 };
584
585 static void p1852_usb_init(void)
586 {
587         /* Need to parse sku info to decide host/device mode */
588
589         /* G_ANDROID require device mode */
590 #if defined(CONFIG_USB_G_ANDROID)
591         tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
592         platform_device_register(&tegra_udc_device);
593 #else
594         tegra_ehci1_device.dev.platform_data = &tegra_ehci1_utmi_pdata;
595         platform_device_register(&tegra_ehci1_device);
596 #endif
597         tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata;
598         platform_device_register(&tegra_ehci2_device);
599
600         tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
601         platform_device_register(&tegra_ehci3_device);
602 }
603
604 static struct tegra_nor_platform_data p1852_nor_data = {
605         .flash = {
606                 .map_name = "cfi_probe",
607                 .width = 2,
608         },
609         .chip_parms = {
610                 /* FIXME: Need to use characterized value */
611                 .timing_default = {
612                         .timing0 = 0x30300263,
613                         .timing1 = 0x00030302,
614                 },
615                 .timing_read = {
616                         .timing0 = 0x30300263,
617                         .timing1 = 0x00030302,
618                 },
619         },
620 };
621
622 static void p1852_nor_init(void)
623 {
624         tegra_nor_device.resource[2].end = TEGRA_NOR_FLASH_BASE + SZ_64M - 1;
625         tegra_nor_device.dev.platform_data = &p1852_nor_data;
626         platform_device_register(&tegra_nor_device);
627 }
628
629 static void __init tegra_p1852_init(void)
630 {
631         tegra_init_board_info();
632         tegra_clk_init_from_table(p1852_clk_init_table);
633         tegra_enable_pinmux();
634         p1852_pinmux_init();
635         p1852_i2c_init();
636         p1852_i2s_audio_init();
637         p1852_gpio_init();
638         p1852_uart_init();
639         p1852_usb_init();
640         tegra_io_dpd_init();
641         p1852_sdhci_init();
642         p1852_spi_init();
643         platform_add_devices(p1852_devices, ARRAY_SIZE(p1852_devices));
644 #ifdef CONFIG_TOUCHSCREEN_ATMEL_MXT
645         p1852_touch_init();
646 #endif
647         p1852_panel_init();
648         p1852_nor_init();
649         p1852_pcie_init();
650         tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
651 }
652
653 static void __init tegra_p1852_reserve(void)
654 {
655 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
656         tegra_reserve(0, SZ_8M, SZ_8M);
657 #else
658         tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
659 #endif
660 }
661
662 int p1852_get_skuid()
663 {
664         switch (system_rev) {
665         case TEGRA_P1852_SKU2_A00:
666         case TEGRA_P1852_SKU2_B00:
667                 return 2;
668         case TEGRA_P1852_SKU5_A00:
669         case TEGRA_P1852_SKU5_B00:
670                 return 5;
671         case TEGRA_P1852_SKU8_A00:
672         case TEGRA_P1852_SKU8_B00:
673                 return 8;
674         default:
675                 return -1;
676         }
677 }
678
679 MACHINE_START(P1852, "p1852")
680         .atag_offset    = 0x100,
681         .soc            = &tegra_soc_desc,
682         .init_irq       = tegra_init_irq,
683         .init_early     = tegra_init_early,
684         .init_machine   = tegra_p1852_init,
685         .map_io         = tegra_map_common_io,
686         .reserve        = tegra_p1852_reserve,
687         .timer          = &tegra_timer,
688 MACHINE_END