video: tegra: host: Register devices in SoC files
[linux-2.6.git] / arch / arm / mach-tegra / board-p1852-panel.c
1 /*
2  * arch/arm/mach-tegra/board-p1852-panel.c
3  *
4  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/resource.h>
20 #include <asm/mach-types.h>
21 #include <linux/platform_device.h>
22 #include <linux/nvhost.h>
23 #include <linux/nvmap.h>
24 #include <mach/irqs.h>
25 #include <mach/iomap.h>
26 #include <mach/dc.h>
27 #include <mach/fb.h>
28
29 #include "board.h"
30 #include "devices.h"
31 #include "tegra3_host1x_devices.h"
32
33 static int p1852_panel_enable(void)
34 {
35         return 0;
36 }
37
38 static int p1852_panel_disable(void)
39 {
40         return 0;
41 }
42
43 static struct tegra_dc_mode p1852_panel_modes[] = {
44         {
45                 /* 800x480@60 */
46                 .pclk = 32460000,
47                 .h_ref_to_sync = 1,
48                 .v_ref_to_sync = 1,
49                 .h_sync_width = 64,
50                 .v_sync_width = 3,
51                 .h_back_porch = 128,
52                 .v_back_porch = 22,
53                 .h_front_porch = 64,
54                 .v_front_porch = 20,
55                 .h_active = 800,
56                 .v_active = 480,
57         },
58 };
59
60 static struct tegra_fb_data p1852_fb_data = {
61         .win            = 0,
62         .xres           = 800,
63         .yres           = 480,
64         .bits_per_pixel = 32,
65 };
66
67 static struct tegra_dc_out p1852_disp1_out = {
68         .align          = TEGRA_DC_ALIGN_MSB,
69         .order          = TEGRA_DC_ORDER_RED_BLUE,
70         .type           = TEGRA_DC_OUT_RGB,
71         .modes          = p1852_panel_modes,
72         .n_modes        = ARRAY_SIZE(p1852_panel_modes),
73         .enable         = p1852_panel_enable,
74         .disable        = p1852_panel_disable,
75 };
76
77 static struct tegra_dc_platform_data p1852_disp1_pdata = {
78         .flags          = TEGRA_DC_FLAG_ENABLED,
79         .default_out    = &p1852_disp1_out,
80         .emc_clk_rate   = 300000000,
81         .fb             = &p1852_fb_data,
82 };
83
84 static struct nvmap_platform_carveout p1852_carveouts[] = {
85         [0] = {
86                 .name           = "iram",
87                 .usage_mask     = NVMAP_HEAP_CARVEOUT_IRAM,
88                 .base           = TEGRA_IRAM_BASE + TEGRA_RESET_HANDLER_SIZE,
89                 .size           = TEGRA_IRAM_SIZE - TEGRA_RESET_HANDLER_SIZE,
90                 .buddy_size     = 0, /* no buddy allocation for IRAM */
91         },
92         [1] = {
93                 .name           = "generic-0",
94                 .usage_mask     = NVMAP_HEAP_CARVEOUT_GENERIC,
95                 .base           = 0,    /* Filled in by p1852_panel_init() */
96                 .size           = 0,    /* Filled in by p1852_panel_init() */
97                 .buddy_size     = SZ_32K,
98         },
99 };
100
101 static struct nvmap_platform_data p1852_nvmap_data = {
102         .carveouts      = p1852_carveouts,
103         .nr_carveouts   = ARRAY_SIZE(p1852_carveouts),
104 };
105
106 static struct platform_device *p1852_gfx_devices[] __initdata = {
107         &tegra_nvmap_device,
108 };
109
110 int __init p1852_panel_init(void)
111 {
112         int err;
113         struct resource *res;
114
115         p1852_carveouts[1].base = tegra_carveout_start;
116         p1852_carveouts[1].size = tegra_carveout_size;
117         tegra_nvmap_device.dev.platform_data = &p1852_nvmap_data;
118         tegra_disp1_device.dev.platform_data = &p1852_disp1_pdata;
119
120         res = nvhost_get_resource_byname(&tegra_disp1_device,
121                                          IORESOURCE_MEM, "fbmem");
122         if (!res) {
123                 pr_err("No memory resources\n");
124                 return -ENODEV;
125         }
126         res->start = tegra_fb_start;
127         res->end = tegra_fb_start + tegra_fb_size - 1;
128
129 #ifdef CONFIG_TEGRA_GRHOST
130         err = tegra3_register_host1x_devices();
131         if (err)
132                 return err;
133 #endif
134
135         err = platform_add_devices(p1852_gfx_devices,
136                                 ARRAY_SIZE(p1852_gfx_devices));
137         if (!err)
138                 err = nvhost_device_register(&tegra_disp1_device);
139
140 #if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_NVAVP)
141         if (!err)
142                 err = nvhost_device_register(&nvavp_device);
143 #endif
144         return err;
145 }