2 * arch/arm/mach-tegra/board-macallan-power.c
4 * Copyright (C) 2012-2013 NVIDIA Corporation. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
25 #include <linux/regulator/machine.h>
26 #include <linux/regulator/driver.h>
27 #include <linux/regulator/fixed.h>
28 #include <linux/mfd/palmas.h>
29 #include <linux/mfd/bq2419x.h>
30 #include <linux/max17048_battery.h>
31 #include <linux/gpio.h>
32 #include <linux/interrupt.h>
33 #include <linux/regulator/userspace-consumer.h>
35 #include <asm/mach-types.h>
36 #include <linux/power/sbs-battery.h>
38 #include <mach/iomap.h>
39 #include <mach/irqs.h>
40 #include <mach/hardware.h>
42 #include <mach/gpio-tegra.h>
44 #include "cpu-tegra.h"
46 #include "tegra-board-id.h"
48 #include "gpio-names.h"
49 #include "board-common.h"
50 #include "board-macallan.h"
51 #include "tegra_cl_dvfs.h"
53 #include "tegra11_soctherm.h"
54 #include "tegra3_tsensor.h"
57 #define PMC_CTRL_INTR_LOW (1 << 17)
59 /* BQ2419X VBUS regulator */
60 static struct regulator_consumer_supply bq2419x_vbus_supply[] = {
61 REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
64 static struct regulator_init_data bq2419x_init_data = {
66 .name = "bq2419x_vbus",
69 .valid_modes_mask = (REGULATOR_MODE_NORMAL |
70 REGULATOR_MODE_STANDBY),
71 .valid_ops_mask = (REGULATOR_CHANGE_MODE |
72 REGULATOR_CHANGE_STATUS |
73 REGULATOR_CHANGE_VOLTAGE),
75 .num_consumer_supplies = ARRAY_SIZE(bq2419x_vbus_supply),
76 .consumer_supplies = bq2419x_vbus_supply,
79 static struct bq2419x_regulator_platform_data bq2419x_reg_pdata = {
80 .reg_init_data = &bq2419x_init_data,
81 .gpio_otg_iusb = TEGRA_GPIO_PI4,
84 struct bq2419x_platform_data macallan_bq2419x_pdata = {
85 .reg_pdata = &bq2419x_reg_pdata,
86 .disable_watchdog = true,
89 static struct i2c_board_info __initdata bq2419x_boardinfo[] = {
91 I2C_BOARD_INFO("bq2419x", 0x6b),
92 .platform_data = &macallan_bq2419x_pdata,
97 /************************ Macallan based regulator ****************/
98 static struct regulator_consumer_supply palmas_smps123_supply[] = {
99 REGULATOR_SUPPLY("vdd_cpu", NULL),
102 static struct regulator_consumer_supply palmas_smps45_supply[] = {
103 REGULATOR_SUPPLY("vdd_core", NULL),
104 REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.0"),
105 REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.3"),
108 static struct regulator_consumer_supply palmas_smps6_supply[] = {
109 REGULATOR_SUPPLY("vdd_lcd_hv", NULL),
110 REGULATOR_SUPPLY("avdd_lcd", NULL),
111 REGULATOR_SUPPLY("avdd", "spi0.0"),
114 static struct regulator_consumer_supply palmas_smps7_supply[] = {
115 REGULATOR_SUPPLY("vddio_ddr", NULL),
118 static struct regulator_consumer_supply palmas_smps8_supply[] = {
119 REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
120 REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
121 REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
122 REGULATOR_SUPPLY("avdd_osc", NULL),
123 REGULATOR_SUPPLY("vddio_sys", NULL),
124 REGULATOR_SUPPLY("vddio_bb", NULL),
125 REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
126 REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
127 REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
128 REGULATOR_SUPPLY("vdd_emmc", "sdhci-tegra.3"),
129 REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
130 REGULATOR_SUPPLY("vddio_audio", NULL),
131 REGULATOR_SUPPLY("pwrdet_audio", NULL),
132 REGULATOR_SUPPLY("vddio_uart", NULL),
133 REGULATOR_SUPPLY("pwrdet_uart", NULL),
134 REGULATOR_SUPPLY("vddio_gmi", NULL),
135 REGULATOR_SUPPLY("vlogic", "0-0069"),
138 static struct regulator_consumer_supply palmas_smps9_supply[] = {
139 REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
142 static struct regulator_consumer_supply palmas_smps10_supply[] = {
145 static struct regulator_consumer_supply palmas_ldo1_supply[] = {
146 REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
147 REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
148 REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
149 REGULATOR_SUPPLY("avdd_csi_dsi_pll", "vi"),
150 REGULATOR_SUPPLY("avdd_pllm", NULL),
151 REGULATOR_SUPPLY("avdd_pllu", NULL),
152 REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
153 REGULATOR_SUPPLY("avdd_pllx", NULL),
154 REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
155 REGULATOR_SUPPLY("avdd_plle", NULL),
158 static struct regulator_consumer_supply palmas_ldo2_supply[] = {
159 REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
160 REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
161 REGULATOR_SUPPLY("avdd_dsi_csi", "vi"),
162 REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
163 REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
166 static struct regulator_consumer_supply palmas_ldo3_supply[] = {
167 REGULATOR_SUPPLY("vpp_fuse", NULL),
170 static struct regulator_consumer_supply palmas_ldo4_supply[] = {
171 REGULATOR_SUPPLY("vdd_1v2_cam", NULL),
172 REGULATOR_SUPPLY("dvdd", "2-0010"),
173 REGULATOR_SUPPLY("vdig", "2-0036"),
176 static struct regulator_consumer_supply palmas_ldo5_supply[] = {
177 REGULATOR_SUPPLY("avdd_cam2", NULL),
178 REGULATOR_SUPPLY("avdd", "2-0010"),
181 static struct regulator_consumer_supply palmas_ldo6_supply[] = {
182 REGULATOR_SUPPLY("vdd", "0-0069"),
185 static struct regulator_consumer_supply palmas_ldo7_supply[] = {
186 REGULATOR_SUPPLY("avdd_2v8_cam_af", NULL),
187 REGULATOR_SUPPLY("vdd_af_cam1", NULL),
188 REGULATOR_SUPPLY("avdd_cam1", NULL),
189 REGULATOR_SUPPLY("vana", "2-0036"),
190 REGULATOR_SUPPLY("vdd", "2-000e"),
193 static struct regulator_consumer_supply palmas_ldo8_supply[] = {
194 REGULATOR_SUPPLY("vdd_rtc", NULL),
196 static struct regulator_consumer_supply palmas_ldo9_supply[] = {
197 REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
198 REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
200 static struct regulator_consumer_supply palmas_ldoln_supply[] = {
201 REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
204 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
205 REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
206 REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
207 REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
208 REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
209 REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
213 static struct regulator_consumer_supply palmas_regen1_supply[] = {
216 static struct regulator_consumer_supply palmas_regen2_supply[] = {
219 #define PALMAS_PDATA_INIT(_name, _minmv, _maxmv, _supply_reg, _always_on, \
220 _boot_on, _apply_uv) \
221 static struct regulator_init_data reg_idata_##_name = { \
223 .name = palmas_rails(_name), \
224 .min_uV = (_minmv)*1000, \
225 .max_uV = (_maxmv)*1000, \
226 .valid_modes_mask = (REGULATOR_MODE_NORMAL | \
227 REGULATOR_MODE_STANDBY), \
228 .valid_ops_mask = (REGULATOR_CHANGE_MODE | \
229 REGULATOR_CHANGE_STATUS | \
230 REGULATOR_CHANGE_VOLTAGE), \
231 .always_on = _always_on, \
232 .boot_on = _boot_on, \
233 .apply_uV = _apply_uv, \
235 .num_consumer_supplies = \
236 ARRAY_SIZE(palmas_##_name##_supply), \
237 .consumer_supplies = palmas_##_name##_supply, \
238 .supply_regulator = _supply_reg, \
241 PALMAS_PDATA_INIT(smps123, 900, 1300, NULL, 0, 0, 0);
242 PALMAS_PDATA_INIT(smps45, 900, 1400, NULL, 0, 0, 0);
243 PALMAS_PDATA_INIT(smps6, 3200, 3200, NULL, 0, 0, 1);
244 PALMAS_PDATA_INIT(smps7, 1350, 1350, NULL, 0, 0, 1);
245 PALMAS_PDATA_INIT(smps8, 1800, 1800, NULL, 1, 1, 1);
246 PALMAS_PDATA_INIT(smps9, 2900, 2900, NULL, 1, 0, 1);
247 PALMAS_PDATA_INIT(smps10, 5000, 5000, NULL, 0, 0, 0);
248 PALMAS_PDATA_INIT(ldo1, 1050, 1050, palmas_rails(smps7), 1, 0, 1);
249 PALMAS_PDATA_INIT(ldo2, 1200, 1200, palmas_rails(smps7), 0, 1, 1);
250 PALMAS_PDATA_INIT(ldo3, 1800, 1800, NULL, 0, 0, 0);
251 PALMAS_PDATA_INIT(ldo4, 1200, 1200, palmas_rails(smps8), 0, 0, 0);
252 PALMAS_PDATA_INIT(ldo5, 2700, 2700, palmas_rails(smps9), 0, 0, 1);
253 PALMAS_PDATA_INIT(ldo6, 2850, 2850, palmas_rails(smps9), 1, 1, 1);
254 PALMAS_PDATA_INIT(ldo7, 2700, 2700, palmas_rails(smps9), 0, 0, 1);
255 PALMAS_PDATA_INIT(ldo8, 1100, 1100, NULL, 1, 1, 1);
256 PALMAS_PDATA_INIT(ldo9, 1800, 2900, palmas_rails(smps9), 0, 0, 1);
257 PALMAS_PDATA_INIT(ldoln, 3300, 3300, NULL, 0, 0, 1);
258 PALMAS_PDATA_INIT(ldousb, 3300, 3300, NULL, 0, 0, 1);
259 PALMAS_PDATA_INIT(regen1, 4200, 4200, NULL, 0, 0, 0);
260 PALMAS_PDATA_INIT(regen2, 4200, 4200, palmas_rails(smps8), 0, 0, 0);
262 #define PALMAS_REG_PDATA(_sname) (®_idata_##_sname)
263 static struct regulator_init_data *macallan_reg_data[PALMAS_NUM_REGS] = {
265 PALMAS_REG_PDATA(smps123),
267 PALMAS_REG_PDATA(smps45),
269 PALMAS_REG_PDATA(smps6),
270 PALMAS_REG_PDATA(smps7),
271 PALMAS_REG_PDATA(smps8),
272 PALMAS_REG_PDATA(smps9),
273 PALMAS_REG_PDATA(smps10),
274 PALMAS_REG_PDATA(ldo1),
275 PALMAS_REG_PDATA(ldo2),
276 PALMAS_REG_PDATA(ldo3),
277 PALMAS_REG_PDATA(ldo4),
278 PALMAS_REG_PDATA(ldo5),
279 PALMAS_REG_PDATA(ldo6),
280 PALMAS_REG_PDATA(ldo7),
281 PALMAS_REG_PDATA(ldo8),
282 PALMAS_REG_PDATA(ldo9),
283 PALMAS_REG_PDATA(ldoln),
284 PALMAS_REG_PDATA(ldousb),
285 PALMAS_REG_PDATA(regen1),
286 PALMAS_REG_PDATA(regen2),
292 #define PALMAS_REG_INIT(_name, _warm_reset, _roof_floor, _mode_sleep, \
294 static struct palmas_reg_init reg_init_data_##_name = { \
295 .warm_reset = _warm_reset, \
296 .roof_floor = _roof_floor, \
297 .mode_sleep = _mode_sleep, \
302 PALMAS_REG_INIT(smps12, 0, 0, 0, 0, 0);
303 PALMAS_REG_INIT(smps123, 0, PALMAS_EXT_CONTROL_ENABLE1, 0, 0, 0);
304 PALMAS_REG_INIT(smps3, 0, 0, 0, 0, 0);
305 PALMAS_REG_INIT(smps45, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
306 PALMAS_REG_INIT(smps457, 0, 0, 0, 0, 0);
307 PALMAS_REG_INIT(smps6, 0, 0, 0, 0, 0);
308 PALMAS_REG_INIT(smps7, 0, 0, 0, 0, 0);
309 PALMAS_REG_INIT(smps8, 0, 0, 0, 0, 0);
310 PALMAS_REG_INIT(smps9, 0, 0, 0, 0, 0);
311 PALMAS_REG_INIT(smps10, 0, 0, 0, 0, 0);
312 PALMAS_REG_INIT(ldo1, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
313 PALMAS_REG_INIT(ldo2, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
314 PALMAS_REG_INIT(ldo3, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
315 PALMAS_REG_INIT(ldo4, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
316 PALMAS_REG_INIT(ldo5, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
317 PALMAS_REG_INIT(ldo6, 0, 0, 0, 0, 0);
318 PALMAS_REG_INIT(ldo7, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
319 PALMAS_REG_INIT(ldo8, 0, 0, 0, 0, 0);
320 PALMAS_REG_INIT(ldo9, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
321 PALMAS_REG_INIT(ldoln, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
322 PALMAS_REG_INIT(ldousb, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
324 #define PALMAS_REG_INIT_DATA(_sname) (®_init_data_##_sname)
325 static struct palmas_reg_init *macallan_reg_init[PALMAS_NUM_REGS] = {
326 PALMAS_REG_INIT_DATA(smps12),
327 PALMAS_REG_INIT_DATA(smps123),
328 PALMAS_REG_INIT_DATA(smps3),
329 PALMAS_REG_INIT_DATA(smps45),
330 PALMAS_REG_INIT_DATA(smps457),
331 PALMAS_REG_INIT_DATA(smps6),
332 PALMAS_REG_INIT_DATA(smps7),
333 PALMAS_REG_INIT_DATA(smps8),
334 PALMAS_REG_INIT_DATA(smps9),
335 PALMAS_REG_INIT_DATA(smps10),
336 PALMAS_REG_INIT_DATA(ldo1),
337 PALMAS_REG_INIT_DATA(ldo2),
338 PALMAS_REG_INIT_DATA(ldo3),
339 PALMAS_REG_INIT_DATA(ldo4),
340 PALMAS_REG_INIT_DATA(ldo5),
341 PALMAS_REG_INIT_DATA(ldo6),
342 PALMAS_REG_INIT_DATA(ldo7),
343 PALMAS_REG_INIT_DATA(ldo8),
344 PALMAS_REG_INIT_DATA(ldo9),
345 PALMAS_REG_INIT_DATA(ldoln),
346 PALMAS_REG_INIT_DATA(ldousb),
349 static struct palmas_pmic_platform_data pmic_platform = {
350 .enable_ldo8_tracking = true,
351 .disabe_ldo8_tracking_suspend = true,
352 .disable_smps10_boost_suspend = true,
355 static struct palmas_platform_data palmas_pdata = {
356 .gpio_base = PALMAS_TEGRA_GPIO_BASE,
357 .irq_base = PALMAS_TEGRA_IRQ_BASE,
358 .pmic_pdata = &pmic_platform,
359 .mux_from_pdata = true,
362 .pad3 = PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1,
363 .use_power_off = true,
366 static struct i2c_board_info palma_device[] = {
368 I2C_BOARD_INFO("tps65913", 0x58),
369 .irq = INT_EXTERNAL_PMU,
370 .platform_data = &palmas_pdata,
374 static struct regulator_consumer_supply fixed_reg_dvdd_lcd_1v8_supply[] = {
375 REGULATOR_SUPPLY("dvdd_lcd", NULL),
378 static struct regulator_consumer_supply fixed_reg_vdd_lcd_bl_en_supply[] = {
379 REGULATOR_SUPPLY("vdd_lcd_bl_en", NULL),
382 /* EN_1V8_TS From TEGRA_GPIO_PH4 */
383 static struct regulator_consumer_supply fixed_reg_dvdd_ts_supply[] = {
384 REGULATOR_SUPPLY("dvdd", "spi0.0"),
387 /* ENABLE 5v0 for HDMI */
388 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = {
389 REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
392 static struct regulator_consumer_supply fixed_reg_vddio_sd_slot_supply[] = {
393 REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
396 static struct regulator_consumer_supply fixed_reg_vd_cam_1v8_supply[] = {
397 REGULATOR_SUPPLY("vdd_cam_1v8", NULL),
398 REGULATOR_SUPPLY("vi2c", "2-0030"),
399 REGULATOR_SUPPLY("vif", "2-0036"),
400 REGULATOR_SUPPLY("dovdd", "2-0010"),
401 REGULATOR_SUPPLY("vdd_i2c", "2-000e"),
404 /* Macro for defining fixed regulator sub device data */
405 #define FIXED_SUPPLY(_name) "fixed_reg_"#_name
406 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on, \
407 _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts) \
408 static struct regulator_init_data ri_data_##_var = \
410 .supply_regulator = _in_supply, \
411 .num_consumer_supplies = \
412 ARRAY_SIZE(fixed_reg_##_name##_supply), \
413 .consumer_supplies = fixed_reg_##_name##_supply, \
415 .valid_modes_mask = (REGULATOR_MODE_NORMAL | \
416 REGULATOR_MODE_STANDBY), \
417 .valid_ops_mask = (REGULATOR_CHANGE_MODE | \
418 REGULATOR_CHANGE_STATUS | \
419 REGULATOR_CHANGE_VOLTAGE), \
420 .always_on = _always_on, \
421 .boot_on = _boot_on, \
424 static struct fixed_voltage_config fixed_reg_##_var##_pdata = \
426 .supply_name = FIXED_SUPPLY(_name), \
427 .microvolts = _millivolts * 1000, \
429 .gpio_is_open_drain = _open_drain, \
430 .enable_high = _active_high, \
431 .enabled_at_boot = _boot_state, \
432 .init_data = &ri_data_##_var, \
434 static struct platform_device fixed_reg_##_var##_dev = { \
435 .name = "reg-fixed-voltage", \
438 .platform_data = &fixed_reg_##_var##_pdata, \
443 * Creating the fixed regulator device table
446 FIXED_REG(1, dvdd_lcd_1v8, dvdd_lcd_1v8,
447 palmas_rails(smps8), 0, 1,
448 PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO4, false, true, 1, 1800);
450 FIXED_REG(2, vdd_lcd_bl_en, vdd_lcd_bl_en,
452 TEGRA_GPIO_PH2, false, true, 1, 3700);
454 FIXED_REG(3, dvdd_ts, dvdd_ts,
455 palmas_rails(smps8), 0, 0,
456 TEGRA_GPIO_PH4, false, false, 1, 1800);
458 FIXED_REG(4, vdd_hdmi_5v0, vdd_hdmi_5v0,
459 palmas_rails(smps10), 0, 0,
460 TEGRA_GPIO_PK6, false, true, 0, 5000);
462 FIXED_REG(5, vddio_sd_slot, vddio_sd_slot,
463 palmas_rails(smps9), 0, 0,
464 TEGRA_GPIO_PK1, false, true, 0, 2900);
466 FIXED_REG(6, vd_cam_1v8, vd_cam_1v8,
467 palmas_rails(smps8), 0, 0,
468 PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO6, false, true, 0, 1800);
470 #define ADD_FIXED_REG(_name) (&fixed_reg_##_name##_dev)
472 /* Gpio switch regulator platform data for Macallan E1545 */
473 static struct platform_device *fixed_reg_devs[] = {
474 ADD_FIXED_REG(dvdd_lcd_1v8),
475 ADD_FIXED_REG(vdd_lcd_bl_en),
476 ADD_FIXED_REG(dvdd_ts),
477 ADD_FIXED_REG(vdd_hdmi_5v0),
478 ADD_FIXED_REG(vddio_sd_slot),
479 ADD_FIXED_REG(vd_cam_1v8),
483 int __init macallan_palmas_regulator_init(void)
485 void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
489 /* TPS65913: Normal state of INT request line is LOW.
490 * configure the power management controller to trigger PMU
491 * interrupts when HIGH.
493 pmc_ctrl = readl(pmc + PMC_CTRL);
494 writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
495 for (i = 0; i < PALMAS_NUM_REGS ; i++) {
496 pmic_platform.reg_data[i] = macallan_reg_data[i];
497 pmic_platform.reg_init[i] = macallan_reg_init[i];
500 i2c_register_board_info(4, palma_device,
501 ARRAY_SIZE(palma_device));
502 i2c_register_board_info(0, bq2419x_boardinfo,
503 ARRAY_SIZE(bq2419x_boardinfo));
508 static int ac_online(void)
513 static struct resource macallan_pda_resources[] = {
519 static struct pda_power_pdata macallan_pda_data = {
520 .is_ac_online = ac_online,
523 static struct platform_device macallan_pda_power_device = {
526 .resource = macallan_pda_resources,
527 .num_resources = ARRAY_SIZE(macallan_pda_resources),
529 .platform_data = &macallan_pda_data,
533 static struct tegra_suspend_platform_data macallan_suspend_data = {
535 .cpu_off_timer = 300,
536 .suspend_mode = TEGRA_SUSPEND_LP0,
537 .core_timer = 0x157e,
538 .core_off_timer = 2000,
539 .corereq_high = true,
540 .sysclkreq_high = true,
541 .cpu_lp2_min_residency = 1000,
542 .min_residency_crail = 20000,
544 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
545 /* board parameters for cpu dfll */
546 static struct tegra_cl_dvfs_cfg_param macallan_cl_dvfs_param = {
547 .sample_rate = 12500,
549 .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
554 .droop_cut_value = 0xF,
555 .droop_restore_ramp = 0x0,
556 .scale_out_ramp = 0x0,
560 /* palmas: fixed 10mV steps from 600mV to 1400mV, with offset 0x10 */
561 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
562 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
563 static inline void fill_reg_map(void)
566 for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
567 pmu_cpu_vdd_map[i].reg_value = i + 0x10;
568 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
572 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
573 static struct tegra_cl_dvfs_platform_data macallan_cl_dvfs_data = {
574 .dfll_clk_name = "dfll_cpu",
575 .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
581 .vdd_map = pmu_cpu_vdd_map,
582 .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
584 .cfg_param = &macallan_cl_dvfs_param,
587 static int __init macallan_cl_dvfs_init(void)
590 if (tegra_revision < TEGRA_REVISION_A02)
591 macallan_cl_dvfs_data.out_quiet_then_disable = true;
592 tegra_cl_dvfs_device.dev.platform_data = &macallan_cl_dvfs_data;
593 platform_device_register(&tegra_cl_dvfs_device);
599 static int __init macallan_fixed_regulator_init(void)
601 if (!machine_is_macallan())
604 return platform_add_devices(fixed_reg_devs,
605 ARRAY_SIZE(fixed_reg_devs));
607 subsys_initcall_sync(macallan_fixed_regulator_init);
609 int __init macallan_regulator_init(void)
612 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
613 macallan_cl_dvfs_init();
615 macallan_palmas_regulator_init();
617 platform_device_register(&macallan_pda_power_device);
622 int __init macallan_suspend_init(void)
624 tegra_init_suspend(&macallan_suspend_data);
628 int __init macallan_edp_init(void)
630 unsigned int regulator_mA;
632 regulator_mA = get_maximum_cpu_current_supported();
634 regulator_mA = 15000;
636 pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
637 tegra_init_cpu_edp_limits(regulator_mA);
639 regulator_mA = get_maximum_core_current_supported();
643 pr_info("%s: core regulator %d mA\n", __func__, regulator_mA);
644 tegra_init_core_edp_limits(regulator_mA);
649 static struct thermal_zone_params macallan_soctherm_therm_cpu_tzp = {
650 .governor_name = "pid_thermal_gov",
653 static struct tegra_tsensor_pmu_data tpdata_palmas = {
656 .controller_type = 0,
657 .pmu_i2c_addr = 0x58,
658 .i2c_controller_id = 4,
659 .poweroff_reg_addr = 0xa0,
660 .poweroff_reg_data = 0x0,
663 static struct soctherm_platform_data macallan_soctherm_data = {
667 .passive_delay = 1000,
671 .cdev_type = "tegra-balanced",
673 .trip_type = THERMAL_TRIP_PASSIVE,
674 .upper = THERMAL_NO_LIMIT,
675 .lower = THERMAL_NO_LIMIT,
678 .cdev_type = "tegra-heavy",
680 .trip_type = THERMAL_TRIP_HOT,
681 .upper = THERMAL_NO_LIMIT,
682 .lower = THERMAL_NO_LIMIT,
685 .cdev_type = "tegra-shutdown",
687 .trip_type = THERMAL_TRIP_CRITICAL,
688 .upper = THERMAL_NO_LIMIT,
689 .lower = THERMAL_NO_LIMIT,
692 .tzp = &macallan_soctherm_therm_cpu_tzp,
704 [THROTTLE_DEV_CPU] = {
710 .tshut_pmu_trip_data = &tpdata_palmas,
713 int __init macallan_soctherm_init(void)
715 tegra_platform_edp_init(macallan_soctherm_data.therm[THERM_CPU].trips,
716 &macallan_soctherm_data.therm[THERM_CPU].num_trips,
717 8000); /* edp temperature margin */
718 tegra_add_tj_trips(macallan_soctherm_data.therm[THERM_CPU].trips,
719 &macallan_soctherm_data.therm[THERM_CPU].num_trips);
721 return tegra11_soctherm_init(&macallan_soctherm_data);