touch: raydium: Update to board files
[linux-2.6.git] / arch / arm / mach-tegra / board-kai-power.c
1 /*
2  * arch/arm/mach-tegra/board-kai-power.c
3  *
4  * Copyright (C) 2012 NVIDIA, Inc.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
18  * 02111-1307, USA
19  */
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
24 #include <linux/regulator/machine.h>
25 #include <linux/mfd/max77663-core.h>
26 #include <linux/regulator/max77663-regulator.h>
27 #include <linux/gpio.h>
28 #include <linux/io.h>
29 #include <linux/regulator/fixed.h>
30 #include <linux/power/gpio-charger.h>
31
32 #include <asm/mach-types.h>
33
34 #include <mach/iomap.h>
35 #include <mach/irqs.h>
36 #include <mach/pinmux.h>
37 #include <mach/edp.h>
38 #include <mach/gpio-tegra.h>
39
40 #include "gpio-names.h"
41 #include "board.h"
42 #include "board-kai.h"
43 #include "pm.h"
44 #include "tegra3_tsensor.h"
45
46 #define PMC_CTRL                0x0
47 #define PMC_CTRL_INTR_LOW       (1 << 17)
48
49 static struct regulator_consumer_supply max77663_sd0_supply[] = {
50         REGULATOR_SUPPLY("vdd_cpu", NULL),
51 };
52
53 static struct regulator_consumer_supply max77663_sd1_supply[] = {
54         REGULATOR_SUPPLY("vdd_core", NULL),
55 };
56
57 static struct regulator_consumer_supply max77663_sd2_supply[] = {
58         REGULATOR_SUPPLY("vdd_gen1v8", NULL),
59         REGULATOR_SUPPLY("avdd_hdmi_pll", NULL),
60         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
61         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
62         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
63         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
64         REGULATOR_SUPPLY("avdd_osc", NULL),
65         REGULATOR_SUPPLY("vddio_sys", NULL),
66         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
67         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
68         REGULATOR_SUPPLY("vddio_uart", NULL),
69         REGULATOR_SUPPLY("pwrdet_uart", NULL),
70         REGULATOR_SUPPLY("vddio_bb", NULL),
71         REGULATOR_SUPPLY("pwrdet_bb", NULL),
72         REGULATOR_SUPPLY("vddio_lcd_pmu", NULL),
73         REGULATOR_SUPPLY("pwrdet_lcd", NULL),
74         REGULATOR_SUPPLY("vddio_audio", NULL),
75         REGULATOR_SUPPLY("pwrdet_audio", NULL),
76         REGULATOR_SUPPLY("vddio_cam", NULL),
77         REGULATOR_SUPPLY("pwrdet_cam", NULL),
78         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
79         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
80         REGULATOR_SUPPLY("vddio_vi", NULL),
81         REGULATOR_SUPPLY("pwrdet_vi", NULL),
82         REGULATOR_SUPPLY("vcore_nand", NULL),
83         REGULATOR_SUPPLY("pwrdet_nand", NULL),
84         REGULATOR_SUPPLY("vlogic", "0-0068"),
85         REGULATOR_SUPPLY("dvdd", "spi0.0"),
86 };
87
88 static struct regulator_consumer_supply max77663_sd3_supply[] = {
89         REGULATOR_SUPPLY("vdd_ddr3l_1v35", NULL),
90 };
91
92 static struct regulator_consumer_supply max77663_ldo0_supply[] = {
93         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
94 };
95
96 static struct regulator_consumer_supply max77663_ldo1_supply[] = {
97 };
98
99 static struct regulator_consumer_supply max77663_ldo2_supply[] = {
100         REGULATOR_SUPPLY("vdd_ddr_rx", NULL),
101 };
102
103 static struct regulator_consumer_supply max77663_ldo3_supply[] = {
104 };
105
106 static struct regulator_consumer_supply max77663_ldo4_supply[] = {
107         REGULATOR_SUPPLY("vdd_rtc", NULL),
108 };
109
110 static struct regulator_consumer_supply max77663_ldo5_supply[] = {
111         REGULATOR_SUPPLY("vdd_sensor_2v8", NULL),
112         REGULATOR_SUPPLY("vdd", "0-0068"),
113 };
114
115 static struct regulator_consumer_supply max77663_ldo6_supply[] = {
116         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
117         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
118 };
119
120 static struct regulator_consumer_supply max77663_ldo7_supply[] = {
121         REGULATOR_SUPPLY("avdd_dsi_csi", NULL),
122         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
123 };
124
125 static struct regulator_consumer_supply max77663_ldo8_supply[] = {
126         REGULATOR_SUPPLY("avdd_plla_p_c_s", NULL),
127         REGULATOR_SUPPLY("avdd_pllm", NULL),
128         REGULATOR_SUPPLY("avdd_pllu_d", NULL),
129         REGULATOR_SUPPLY("avdd_pllu_d2", NULL),
130         REGULATOR_SUPPLY("avdd_pllx", NULL),
131 };
132
133 static struct max77663_regulator_fps_cfg max77663_fps_cfgs[] = {
134         {
135                 .src = FPS_SRC_0,
136                 .en_src = FPS_EN_SRC_EN0,
137                 .time_period = FPS_TIME_PERIOD_DEF,
138         },
139         {
140                 .src = FPS_SRC_1,
141                 .en_src = FPS_EN_SRC_EN1,
142                 .time_period = FPS_TIME_PERIOD_DEF,
143         },
144         {
145                 .src = FPS_SRC_2,
146                 .en_src = FPS_EN_SRC_EN0,
147                 .time_period = FPS_TIME_PERIOD_DEF,
148         },
149 };
150
151 #define MAX77663_PDATA_INIT(_rid, _id, _min_uV, _max_uV, _supply_reg,   \
152                             _always_on, _boot_on, _apply_uV,            \
153                             _fps_src, _fps_pu_period, _fps_pd_period, _flags) \
154         static struct regulator_init_data max77663_regulator_idata_##_id = {  \
155                 .supply_regulator = _supply_reg,                        \
156                 .constraints = {                                        \
157                         .name = max77663_rails(_id),                    \
158                         .min_uV = _min_uV,                              \
159                         .max_uV = _max_uV,                              \
160                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
161                                              REGULATOR_MODE_STANDBY),   \
162                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
163                                            REGULATOR_CHANGE_STATUS |    \
164                                            REGULATOR_CHANGE_VOLTAGE),   \
165                         .always_on = _always_on,                        \
166                         .boot_on = _boot_on,                            \
167                         .apply_uV = _apply_uV,                          \
168                 },                                                      \
169                 .num_consumer_supplies =                                \
170                                 ARRAY_SIZE(max77663_##_id##_supply),    \
171                 .consumer_supplies = max77663_##_id##_supply,           \
172         };                                                              \
173         static struct max77663_regulator_platform_data max77663_regulator_pdata_##_id = \
174         {                                                               \
175                 .reg_init_data = &max77663_regulator_idata_##_id,       \
176                 .id = MAX77663_REGULATOR_ID_##_rid,                     \
177                 .fps_src = _fps_src,                                    \
178                 .fps_pu_period = _fps_pu_period,                        \
179                 .fps_pd_period = _fps_pd_period,                        \
180                 .fps_cfgs = max77663_fps_cfgs,                          \
181                 .flags = _flags,                                        \
182         }
183
184 MAX77663_PDATA_INIT(SD0, sd0,  600000, 3387500, NULL, 1, 0, 0,
185                     FPS_SRC_NONE, -1, -1, EN2_CTRL_SD0);
186
187 MAX77663_PDATA_INIT(SD1, sd1,  800000, 1587500, NULL, 1, 1, 0,
188                     FPS_SRC_1, FPS_POWER_PERIOD_1, FPS_POWER_PERIOD_6, 0);
189
190 MAX77663_PDATA_INIT(SD2, sd2,  1800000, 1800000, NULL, 1, 1, 0,
191                     FPS_SRC_0, -1, -1, 0);
192
193 MAX77663_PDATA_INIT(SD3, sd3,  600000, 3387500, NULL, 1, 1, 0,
194                     FPS_SRC_0, -1, -1, 0);
195
196 MAX77663_PDATA_INIT(LDO0, ldo0, 800000, 2350000, max77663_rails(sd3), 1, 1, 0,
197                     FPS_SRC_1, -1, -1, 0);
198
199 MAX77663_PDATA_INIT(LDO1, ldo1, 800000, 2350000, max77663_rails(sd3), 0, 0, 0,
200                     FPS_SRC_NONE, -1, -1, 0);
201
202 MAX77663_PDATA_INIT(LDO2, ldo2, 800000, 3950000, NULL, 1, 1, 0,
203                     FPS_SRC_1, -1, -1, 0);
204
205 MAX77663_PDATA_INIT(LDO3, ldo3, 800000, 3950000, NULL, 1, 1, 0,
206                     FPS_SRC_1, -1, -1, 0);
207
208 MAX77663_PDATA_INIT(LDO4, ldo4, 1000000, 1000000, NULL, 0, 1, 0,
209                     FPS_SRC_0, -1, -1, LDO4_EN_TRACKING);
210
211 MAX77663_PDATA_INIT(LDO5, ldo5, 800000, 2800000, NULL, 0, 1, 0,
212                     FPS_SRC_NONE, -1, -1, 0);
213
214 MAX77663_PDATA_INIT(LDO6, ldo6, 800000, 3950000, NULL, 0, 0, 0,
215                     FPS_SRC_NONE, -1, -1, 0);
216
217 MAX77663_PDATA_INIT(LDO7, ldo7, 800000, 3950000, max77663_rails(sd3), 0, 0, 0,
218                     FPS_SRC_NONE, -1, -1, 0);
219
220 MAX77663_PDATA_INIT(LDO8, ldo8, 800000, 3950000, max77663_rails(sd3), 0, 1, 0,
221                     FPS_SRC_1, -1, -1, 0);
222
223 #define MAX77663_REG(_id, _data) &max77663_regulator_pdata_##_data
224
225 static struct max77663_regulator_platform_data  *max77663_reg_pdata[] = {
226         MAX77663_REG(SD0, sd0),
227         MAX77663_REG(SD1, sd1),
228         MAX77663_REG(SD2, sd2),
229         MAX77663_REG(SD3, sd3),
230         MAX77663_REG(LDO0, ldo0),
231         MAX77663_REG(LDO1, ldo1),
232         MAX77663_REG(LDO2, ldo2),
233         MAX77663_REG(LDO3, ldo3),
234         MAX77663_REG(LDO4, ldo4),
235         MAX77663_REG(LDO5, ldo5),
236         MAX77663_REG(LDO6, ldo6),
237         MAX77663_REG(LDO7, ldo7),
238         MAX77663_REG(LDO8, ldo8),
239 };
240
241 static struct max77663_gpio_config max77663_gpio_cfgs[] = {
242         {
243                 .gpio = MAX77663_GPIO0,
244                 .dir = GPIO_DIR_OUT,
245                 .dout = GPIO_DOUT_LOW,
246                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
247                 .alternate = GPIO_ALT_DISABLE,
248         },
249         {
250                 .gpio = MAX77663_GPIO1,
251                 .dir = GPIO_DIR_IN,
252                 .dout = GPIO_DOUT_LOW,
253                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
254                 .alternate = GPIO_ALT_DISABLE,
255         },
256         {
257                 .gpio = MAX77663_GPIO2,
258                 .dir = GPIO_DIR_OUT,
259                 .dout = GPIO_DOUT_HIGH,
260                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
261                 .alternate = GPIO_ALT_DISABLE,
262         },
263         {
264                 .gpio = MAX77663_GPIO3,
265                 .dir = GPIO_DIR_OUT,
266                 .dout = GPIO_DOUT_LOW,
267                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
268                 .alternate = GPIO_ALT_ENABLE,
269         },
270         {
271                 .gpio = MAX77663_GPIO4,
272                 .dir = GPIO_DIR_OUT,
273                 .dout = GPIO_DOUT_HIGH,
274                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
275                 .alternate = GPIO_ALT_ENABLE,
276         },
277         {
278                 .gpio = MAX77663_GPIO5,
279                 .dir = GPIO_DIR_OUT,
280                 .dout = GPIO_DOUT_LOW,
281                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
282                 .alternate = GPIO_ALT_DISABLE,
283         },
284         {
285                 .gpio = MAX77663_GPIO6,
286                 .dir = GPIO_DIR_IN,
287                 .alternate = GPIO_ALT_DISABLE,
288         },
289         {
290                 .gpio = MAX77663_GPIO7,
291                 .dir = GPIO_DIR_OUT,
292                 .dout = GPIO_DOUT_LOW,
293                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
294                 .alternate = GPIO_ALT_DISABLE,
295         },
296 };
297
298 static struct max77663_platform_data max7763_pdata = {
299         .irq_base       = MAX77663_IRQ_BASE,
300         .gpio_base      = MAX77663_GPIO_BASE,
301
302         .num_gpio_cfgs  = ARRAY_SIZE(max77663_gpio_cfgs),
303         .gpio_cfgs      = max77663_gpio_cfgs,
304
305         .regulator_pdata = max77663_reg_pdata,
306         .num_regulator_pdata = ARRAY_SIZE(max77663_reg_pdata),
307
308         .rtc_i2c_addr   = 0x68,
309
310         .use_power_off  = true,
311 };
312
313 static struct i2c_board_info __initdata max77663_regulators[] = {
314         {
315                 /* The I2C address was determined by OTP factory setting */
316                 I2C_BOARD_INFO("max77663", 0x3c),
317                 .irq            = INT_EXTERNAL_PMU,
318                 .platform_data  = &max7763_pdata,
319         },
320 };
321
322 static int __init kai_max77663_regulator_init(void)
323 {
324         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
325         u32 pmc_ctrl;
326
327         /* configure the power management controller to trigger PMU
328          * interrupts when low */
329         pmc_ctrl = readl(pmc + PMC_CTRL);
330         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
331
332         i2c_register_board_info(4, max77663_regulators,
333                                 ARRAY_SIZE(max77663_regulators));
334
335         return 0;
336 }
337
338 static struct regulator_consumer_supply fixed_reg_en_3v3_sys_a00_supply[] = {
339         REGULATOR_SUPPLY("vdd_3v3", NULL),
340         REGULATOR_SUPPLY("vdd_3v3_devices", NULL),
341         REGULATOR_SUPPLY("debug_cons", NULL),
342         REGULATOR_SUPPLY("pwrdet_pex_ctl", NULL),
343 };
344
345 static struct regulator_consumer_supply fixed_reg_en_3v3_sys_a01_supply[] = {
346         REGULATOR_SUPPLY("vdd_3v3", NULL),
347         REGULATOR_SUPPLY("vdd_3v3_devices", NULL),
348         REGULATOR_SUPPLY("debug_cons", NULL),
349         REGULATOR_SUPPLY("pwrdet_pex_ctl", NULL),
350         REGULATOR_SUPPLY("vddio_gmi", NULL),
351 };
352
353 static struct regulator_consumer_supply fixed_reg_en_avdd_hdmi_usb_a00_supply[] = {
354         REGULATOR_SUPPLY("avdd_hdmi", NULL),
355         REGULATOR_SUPPLY("avdd_usb", NULL),
356         REGULATOR_SUPPLY("vddio_gmi", NULL),
357 };
358
359 static struct regulator_consumer_supply fixed_reg_en_avdd_hdmi_usb_a01_supply[] = {
360         REGULATOR_SUPPLY("avdd_hdmi", NULL),
361         REGULATOR_SUPPLY("avdd_usb", NULL),
362 };
363
364 static struct regulator_consumer_supply fixed_reg_en_1v8_cam_supply[] = {
365         REGULATOR_SUPPLY("vdd_1v8_cam1", NULL),
366         REGULATOR_SUPPLY("vdd_1v8_cam2", NULL),
367         REGULATOR_SUPPLY("vdd_1v8_cam3", NULL),
368 };
369
370 static struct regulator_consumer_supply fixed_reg_en_vddio_vid_supply[] = {
371         REGULATOR_SUPPLY("vdd_hdmi_con", NULL),
372 };
373
374 static struct regulator_consumer_supply fixed_reg_en_3v3_modem_supply[] = {
375         REGULATOR_SUPPLY("vdd_mini_card", NULL),
376 };
377
378 static struct regulator_consumer_supply fixed_reg_en_vdd_pnl_supply[] = {
379         REGULATOR_SUPPLY("vdd_lvds", NULL),
380         REGULATOR_SUPPLY("vdd_lcd_panel", NULL),
381         REGULATOR_SUPPLY("vdd_touch", NULL),
382         REGULATOR_SUPPLY("vddio_ts", NULL),
383         REGULATOR_SUPPLY("avdd", "spi0.0"),
384 };
385
386 static struct regulator_consumer_supply fixed_reg_en_cam3_ldo_supply[] = {
387         REGULATOR_SUPPLY("vdd_cam3", NULL),
388 };
389
390 static struct regulator_consumer_supply fixed_reg_en_vdd_com_supply[] = {
391         REGULATOR_SUPPLY("vdd_com_bd", NULL),
392 };
393
394 static struct regulator_consumer_supply fixed_reg_en_vdd_sdmmc1_supply[] = {
395         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.0"),
396 };
397
398 static struct regulator_consumer_supply fixed_reg_en_3v3_fuse_supply[] = {
399         REGULATOR_SUPPLY("vpp_fuse", NULL),
400 };
401
402 /* Macro for defining fixed regulator sub device data */
403 #define FIXED_SUPPLY(_name) "fixed_reg_"#_name
404 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,   \
405         _gpio_nr, _active_high, _boot_state, _millivolts)       \
406         static struct regulator_init_data ri_data_##_var =              \
407         {                                                               \
408                 .supply_regulator = _in_supply,                         \
409                 .num_consumer_supplies =                                \
410                         ARRAY_SIZE(fixed_reg_##_name##_supply),         \
411                 .consumer_supplies = fixed_reg_##_name##_supply,        \
412                 .constraints = {                                        \
413                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
414                                         REGULATOR_MODE_STANDBY),        \
415                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
416                                         REGULATOR_CHANGE_STATUS |       \
417                                         REGULATOR_CHANGE_VOLTAGE),      \
418                         .always_on = _always_on,                        \
419                         .boot_on = _boot_on,                            \
420                 },                                                      \
421         };                                                              \
422         static struct fixed_voltage_config fixed_reg_##_var##_pdata =   \
423         {                                                               \
424                 .supply_name = FIXED_SUPPLY(_name),                     \
425                 .microvolts = _millivolts * 1000,                       \
426                 .gpio = _gpio_nr,                                       \
427                 .enable_high = _active_high,                            \
428                 .enabled_at_boot = _boot_state,                         \
429                 .init_data = &ri_data_##_var,                           \
430         };                                                              \
431         static struct platform_device fixed_reg_##_var##_dev = {        \
432                 .name = "reg-fixed-voltage",                            \
433                 .id = _id,                                              \
434                 .dev = {                                                \
435                         .platform_data = &fixed_reg_##_var##_pdata,     \
436                 },                                                      \
437         }
438
439
440 /* A00 specific */
441 FIXED_REG(1, en_3v3_sys_a00,    en_3v3_sys_a00,         NULL,
442         1,      0,      MAX77663_GPIO_BASE + MAX77663_GPIO3,    true,   1,      3300);
443 FIXED_REG(2, en_avdd_hdmi_usb_a00, en_avdd_hdmi_usb_a00, FIXED_SUPPLY(en_3v3_sys_a00),
444         1,      0,      MAX77663_GPIO_BASE + MAX77663_GPIO2,    true,   1,      3300);
445 FIXED_REG(3, en_1v8_cam_a00,    en_1v8_cam,             max77663_rails(sd2),
446         0,      0,      TEGRA_GPIO_PS0,                         true,   0,      1800);
447 FIXED_REG(4, en_vddio_vid_a00,  en_vddio_vid,           NULL,
448         0,      0,      TEGRA_GPIO_PB2,                         true,   0,      5000);
449 FIXED_REG(5, en_3v3_modem_a00,  en_3v3_modem,           NULL,
450         0,      1,      TEGRA_GPIO_PP0,                         true,   0,      3300);
451 FIXED_REG(6, en_vdd_pnl_a00,    en_vdd_pnl,             FIXED_SUPPLY(en_3v3_sys_a00),
452         0,      0,      TEGRA_GPIO_PW1,                         true,   0,      3300);
453 FIXED_REG(7, en_cam3_ldo_a00,   en_cam3_ldo,            FIXED_SUPPLY(en_3v3_sys_a00),
454         0,      0,      TEGRA_GPIO_PR7,                         true,   0,      3300);
455 FIXED_REG(8, en_vdd_com_a00,    en_vdd_com,             FIXED_SUPPLY(en_3v3_sys_a00),
456         1,      0,      TEGRA_GPIO_PD0,                         true,   0,      3300);
457 FIXED_REG(9,  en_vdd_sdmmc1_a00, en_vdd_sdmmc1,         FIXED_SUPPLY(en_3v3_sys_a00),
458         0,      0,      TEGRA_GPIO_PC6,                         true,   0,      3300);
459 FIXED_REG(10, en_3v3_fuse_a00,  en_3v3_fuse,            FIXED_SUPPLY(en_3v3_sys_a00),
460         0,      0,      TEGRA_GPIO_PC1,                         true,   0,      3300);
461
462 /* A01 specific */
463 FIXED_REG(1, en_3v3_sys_a01,    en_3v3_sys_a01,         NULL,
464         1,      0,      MAX77663_GPIO_BASE + MAX77663_GPIO3,    true,   1,      3300);
465 FIXED_REG(2, en_avdd_hdmi_usb_a01, en_avdd_hdmi_usb_a01, FIXED_SUPPLY(en_3v3_sys_a01),
466         0,      0,      MAX77663_GPIO_BASE + MAX77663_GPIO2,    true,   0,      3300);
467 FIXED_REG(3, en_1v8_cam_a01,    en_1v8_cam,             max77663_rails(sd2),
468         0,      0,      TEGRA_GPIO_PS0,                         true,   0,      1800);
469 FIXED_REG(4, en_vddio_vid_a01,  en_vddio_vid,           NULL,
470         0,      0,      TEGRA_GPIO_PB2,                         true,   0,      5000);
471 FIXED_REG(5, en_3v3_modem_a01,  en_3v3_modem,           NULL,
472         0,      1,      TEGRA_GPIO_PP0,                         true,   0,      3300);
473 FIXED_REG(6, en_vdd_pnl_a01,    en_vdd_pnl,             FIXED_SUPPLY(en_3v3_sys_a01),
474         0,      1,      TEGRA_GPIO_PW1,                         true,   0,      3300);
475 FIXED_REG(7, en_cam3_ldo_a01,   en_cam3_ldo,            FIXED_SUPPLY(en_3v3_sys_a01),
476         0,      0,      TEGRA_GPIO_PR7,                         true,   0,      3300);
477 FIXED_REG(8, en_vdd_com_a01,    en_vdd_com,             FIXED_SUPPLY(en_3v3_sys_a01),
478         1,      0,      TEGRA_GPIO_PD0,                         true,   0,      3300);
479 FIXED_REG(9,  en_vdd_sdmmc1_a01, en_vdd_sdmmc1,         FIXED_SUPPLY(en_3v3_sys_a01),
480         0,      0,      TEGRA_GPIO_PC6,                         true,   0,      3300);
481 FIXED_REG(10, en_3v3_fuse_a01,  en_3v3_fuse,            FIXED_SUPPLY(en_3v3_sys_a01),
482         0,      0,      TEGRA_GPIO_PC1,                         true,   0,      3300);
483
484 /*
485  * Creating the fixed regulator device tables
486  */
487
488 #define ADD_FIXED_REG(_name)    (&fixed_reg_##_name##_dev)
489
490 /* A00 specific */
491 #define E1565_A00_FIXED_REG \
492         ADD_FIXED_REG(en_3v3_sys_a00),          \
493         ADD_FIXED_REG(en_avdd_hdmi_usb_a00),    \
494         ADD_FIXED_REG(en_1v8_cam_a00),          \
495         ADD_FIXED_REG(en_vddio_vid_a00),        \
496         ADD_FIXED_REG(en_3v3_modem_a00),        \
497         ADD_FIXED_REG(en_vdd_pnl_a00),          \
498         ADD_FIXED_REG(en_cam3_ldo_a00),         \
499         ADD_FIXED_REG(en_vdd_com_a00),          \
500         ADD_FIXED_REG(en_vdd_sdmmc1_a00),       \
501         ADD_FIXED_REG(en_3v3_fuse_a00),         \
502
503 /* A01 specific */
504 #define E1565_A01_FIXED_REG \
505         ADD_FIXED_REG(en_3v3_sys_a01),          \
506         ADD_FIXED_REG(en_avdd_hdmi_usb_a01),    \
507         ADD_FIXED_REG(en_1v8_cam_a01),          \
508         ADD_FIXED_REG(en_vddio_vid_a01),        \
509         ADD_FIXED_REG(en_3v3_modem_a01),        \
510         ADD_FIXED_REG(en_vdd_pnl_a01),          \
511         ADD_FIXED_REG(en_cam3_ldo_a01),         \
512         ADD_FIXED_REG(en_vdd_com_a01),          \
513         ADD_FIXED_REG(en_vdd_sdmmc1_a01),       \
514         ADD_FIXED_REG(en_3v3_fuse_a01),         \
515
516 /* Gpio switch regulator platform data for Kai A00 */
517 static struct platform_device *fixed_reg_devs_a00[] = {
518         E1565_A00_FIXED_REG
519 };
520
521 /* Gpio switch regulator platform data for Kai A01 */
522 static struct platform_device *fixed_reg_devs_a01[] = {
523         E1565_A01_FIXED_REG
524 };
525
526 static int __init kai_fixed_regulator_init(void)
527 {
528         int i;
529         struct board_info board_info;
530         struct platform_device **fixed_reg_devs;
531         int nfixreg_devs;
532
533         tegra_get_board_info(&board_info);
534
535         if (board_info.fab == BOARD_FAB_A00) {
536                 fixed_reg_devs = fixed_reg_devs_a00;
537                 nfixreg_devs = ARRAY_SIZE(fixed_reg_devs_a00);
538         } else {
539                 fixed_reg_devs = fixed_reg_devs_a01;
540                 nfixreg_devs = ARRAY_SIZE(fixed_reg_devs_a01);
541         }
542
543         if (!machine_is_kai())
544                 return 0;
545
546         for (i = 0; i < nfixreg_devs; ++i) {
547                 int gpio_nr;
548                 struct fixed_voltage_config *fixed_reg_pdata =
549                         fixed_reg_devs[i]->dev.platform_data;
550                 gpio_nr = fixed_reg_pdata->gpio;
551
552         }
553
554         return platform_add_devices(fixed_reg_devs, nfixreg_devs);
555 }
556 subsys_initcall_sync(kai_fixed_regulator_init);
557
558 int __init kai_regulator_init(void)
559 {
560         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
561         u32 pmc_ctrl;
562         int ret;
563
564         /* configure the power management controller to trigger PMU
565          * interrupts when low */
566
567         pmc_ctrl = readl(pmc + PMC_CTRL);
568         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
569
570         ret = kai_max77663_regulator_init();
571         if (ret < 0)
572                 return ret;
573
574         return 0;
575 }
576
577 static void kai_board_suspend(int lp_state, enum suspend_stage stg)
578 {
579         if ((lp_state == TEGRA_SUSPEND_LP1) && (stg == TEGRA_SUSPEND_BEFORE_CPU))
580                 tegra_console_uart_suspend();
581 }
582
583 static void kai_board_resume(int lp_state, enum resume_stage stg)
584 {
585         if ((lp_state == TEGRA_SUSPEND_LP1) && (stg == TEGRA_RESUME_AFTER_CPU))
586                 tegra_console_uart_resume();
587 }
588
589 static struct tegra_suspend_platform_data kai_suspend_data = {
590         .cpu_timer      = 2000,
591         .cpu_off_timer  = 200,
592         .suspend_mode   = TEGRA_SUSPEND_LP0,
593         .core_timer     = 0x7e7e,
594         .core_off_timer = 0,
595         .corereq_high   = true,
596         .sysclkreq_high = true,
597         .cpu_lp2_min_residency = 2000,
598         .board_suspend = kai_board_suspend,
599         .board_resume = kai_board_resume,
600 #ifdef CONFIG_TEGRA_LP1_950
601         .lp1_lowvolt_support = true,
602         .i2c_base_addr = TEGRA_I2C5_BASE,
603         .pmuslave_addr = 0x78,
604         .core_reg_addr = 0x17,
605         .lp1_core_volt_low = 0x0C,
606         .lp1_core_volt_high = 0x20,
607 #endif
608 };
609
610 int __init kai_suspend_init(void)
611 {
612         tegra_init_suspend(&kai_suspend_data);
613         return 0;
614 }
615
616 static struct tegra_tsensor_pmu_data  tpdata = {
617         .poweroff_reg_addr = 0x3F,
618         .poweroff_reg_data = 0x80,
619         .reset_tegra = 1,
620         .controller_type = 0,
621         .i2c_controller_id = 4,
622         .pinmux = 0,
623         .pmu_16bit_ops = 0,
624         .pmu_i2c_addr = 0x2D,
625 };
626
627 void __init kai_tsensor_init(void)
628 {
629         tegra3_tsensor_init(&tpdata);
630 }
631
632 #ifdef CONFIG_TEGRA_EDP_LIMITS
633
634 int __init kai_edp_init(void)
635 {
636         unsigned int regulator_mA;
637
638         regulator_mA = get_maximum_cpu_current_supported();
639         if (!regulator_mA)
640                 regulator_mA = 6000; /* regular T30/s */
641         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
642
643         tegra_init_cpu_edp_limits(regulator_mA);
644         return 0;
645 }
646 #endif