arm: tegra: Board files settings for LP1 0.95V CoreV
[linux-2.6.git] / arch / arm / mach-tegra / board-kai-power.c
1 /*
2  * arch/arm/mach-tegra/board-kai-power.c
3  *
4  * Copyright (C) 2012 NVIDIA, Inc.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
18  * 02111-1307, USA
19  */
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
24 #include <linux/regulator/machine.h>
25 #include <linux/mfd/max77663-core.h>
26 #include <linux/regulator/max77663-regulator.h>
27 #include <linux/gpio.h>
28 #include <linux/io.h>
29 #include <linux/regulator/fixed.h>
30 #include <linux/power/gpio-charger.h>
31
32 #include <asm/mach-types.h>
33
34 #include <mach/iomap.h>
35 #include <mach/irqs.h>
36 #include <mach/pinmux.h>
37 #include <mach/edp.h>
38
39 #include "gpio-names.h"
40 #include "board.h"
41 #include "board-kai.h"
42 #include "pm.h"
43 #include "tegra3_tsensor.h"
44
45 #define PMC_CTRL                0x0
46 #define PMC_CTRL_INTR_LOW       (1 << 17)
47
48 static struct regulator_consumer_supply max77663_sd0_supply[] = {
49         REGULATOR_SUPPLY("vdd_cpu", NULL),
50 };
51
52 static struct regulator_consumer_supply max77663_sd1_supply[] = {
53         REGULATOR_SUPPLY("vdd_core", NULL),
54 };
55
56 static struct regulator_consumer_supply max77663_sd2_supply[] = {
57         REGULATOR_SUPPLY("vdd_gen1v8", NULL),
58         REGULATOR_SUPPLY("avdd_hdmi_pll", NULL),
59         REGULATOR_SUPPLY("avdd_usb_pll", NULL),
60         REGULATOR_SUPPLY("avdd_osc", NULL),
61         REGULATOR_SUPPLY("vddio_sys", NULL),
62         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
63         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
64         REGULATOR_SUPPLY("vddio_uart", NULL),
65         REGULATOR_SUPPLY("pwrdet_uart", NULL),
66         REGULATOR_SUPPLY("vddio_bb", NULL),
67         REGULATOR_SUPPLY("pwrdet_bb", NULL),
68         REGULATOR_SUPPLY("vddio_lcd_pmu", NULL),
69         REGULATOR_SUPPLY("pwrdet_lcd", NULL),
70         REGULATOR_SUPPLY("vddio_audio", NULL),
71         REGULATOR_SUPPLY("pwrdet_audio", NULL),
72         REGULATOR_SUPPLY("vddio_cam", NULL),
73         REGULATOR_SUPPLY("pwrdet_cam", NULL),
74         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
75         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
76         REGULATOR_SUPPLY("vddio_vi", NULL),
77         REGULATOR_SUPPLY("pwrdet_vi", NULL),
78         REGULATOR_SUPPLY("vcore_nand", NULL),
79         REGULATOR_SUPPLY("pwrdet_nand", NULL),
80 };
81
82 static struct regulator_consumer_supply max77663_sd3_supply[] = {
83         REGULATOR_SUPPLY("vdd_ddr3l_1v35", NULL),
84 };
85
86 static struct regulator_consumer_supply max77663_ldo0_supply[] = {
87         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
88 };
89
90 static struct regulator_consumer_supply max77663_ldo1_supply[] = {
91 };
92
93 static struct regulator_consumer_supply max77663_ldo2_supply[] = {
94         REGULATOR_SUPPLY("vdd_ddr_rx", NULL),
95 };
96
97 static struct regulator_consumer_supply max77663_ldo3_supply[] = {
98         REGULATOR_SUPPLY("vmmc", NULL),
99 };
100
101 static struct regulator_consumer_supply max77663_ldo4_supply[] = {
102         REGULATOR_SUPPLY("vdd_rtc", NULL),
103 };
104
105 static struct regulator_consumer_supply max77663_ldo5_supply[] = {
106         REGULATOR_SUPPLY("vdd_sensor_2v8", NULL),
107 };
108
109 static struct regulator_consumer_supply max77663_ldo6_supply[] = {
110         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
111         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
112 };
113
114 static struct regulator_consumer_supply max77663_ldo7_supply[] = {
115         REGULATOR_SUPPLY("avdd_dsi_csi", NULL),
116         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
117 };
118
119 static struct regulator_consumer_supply max77663_ldo8_supply[] = {
120         REGULATOR_SUPPLY("avdd_plla_p_c_s", NULL),
121         REGULATOR_SUPPLY("avdd_pllm", NULL),
122         REGULATOR_SUPPLY("avdd_pllu_d", NULL),
123         REGULATOR_SUPPLY("avdd_pllu_d2", NULL),
124         REGULATOR_SUPPLY("avdd_pllx", NULL),
125 };
126
127 static struct max77663_regulator_fps_cfg max77663_fps_cfgs[] = {
128         {
129                 .src = FPS_SRC_0,
130                 .en_src = FPS_EN_SRC_EN0,
131                 .time_period = FPS_TIME_PERIOD_DEF,
132         },
133         {
134                 .src = FPS_SRC_1,
135                 .en_src = FPS_EN_SRC_EN1,
136                 .time_period = FPS_TIME_PERIOD_DEF,
137         },
138         {
139                 .src = FPS_SRC_2,
140                 .en_src = FPS_EN_SRC_EN0,
141                 .time_period = FPS_TIME_PERIOD_DEF,
142         },
143 };
144
145 #define MAX77663_PDATA_INIT(_id, _min_uV, _max_uV, _supply_reg,         \
146                             _always_on, _boot_on, _apply_uV,            \
147                             _init_apply, _init_enable, _init_uV,        \
148                             _fps_src, _fps_pu_period, _fps_pd_period, _flags) \
149         static struct max77663_regulator_platform_data max77663_regulator_pdata_##_id = \
150         {                                                               \
151                 .init_data = {                                          \
152                         .constraints = {                                \
153                                 .min_uV = _min_uV,                      \
154                                 .max_uV = _max_uV,                      \
155                                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |  \
156                                                      REGULATOR_MODE_STANDBY), \
157                                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |    \
158                                                    REGULATOR_CHANGE_STATUS |  \
159                                                    REGULATOR_CHANGE_VOLTAGE), \
160                                 .always_on = _always_on,                \
161                                 .boot_on = _boot_on,                    \
162                                 .apply_uV = _apply_uV,                  \
163                         },                                              \
164                         .num_consumer_supplies =                        \
165                                 ARRAY_SIZE(max77663_##_id##_supply),    \
166                         .consumer_supplies = max77663_##_id##_supply,   \
167                         .supply_regulator = _supply_reg,                \
168                 },                                                      \
169                 .init_apply = _init_apply,                              \
170                 .init_enable = _init_enable,                            \
171                 .init_uV = _init_uV,                                    \
172                 .fps_src = _fps_src,                                    \
173                 .fps_pu_period = _fps_pu_period,                        \
174                 .fps_pd_period = _fps_pd_period,                        \
175                 .fps_cfgs = max77663_fps_cfgs,                          \
176                 .flags = _flags,                                        \
177         }
178
179 MAX77663_PDATA_INIT(sd0,  600000, 3387500, NULL, 1, 0, 0,
180                     0, 0, -1, FPS_SRC_NONE, -1, -1, EN2_CTRL_SD0);
181
182 MAX77663_PDATA_INIT(sd1,  800000, 1587500, NULL, 1, 0, 0,
183                     1, 1, -1, FPS_SRC_1, FPS_POWER_PERIOD_1, FPS_POWER_PERIOD_6, 0);
184
185 MAX77663_PDATA_INIT(sd2,  1800000, 1800000, NULL, 1, 0, 0,
186                     1, 1, -1, FPS_SRC_0, -1, -1, 0);
187
188 MAX77663_PDATA_INIT(sd3,  600000, 3387500, NULL, 1, 0, 0,
189                     1, 1, -1, FPS_SRC_0, -1, -1, 0);
190
191 MAX77663_PDATA_INIT(ldo0, 800000, 2350000, max77663_rails(sd3), 1, 0, 0,
192                     1, 1, -1, FPS_SRC_1, -1, -1, 0);
193
194 MAX77663_PDATA_INIT(ldo1, 800000, 2350000, max77663_rails(sd3), 0, 0, 0,
195                     0, 0, -1, FPS_SRC_NONE, -1, -1, 0);
196
197 MAX77663_PDATA_INIT(ldo2, 800000, 3950000, NULL, 1, 0, 0,
198                     1, 1, -1, FPS_SRC_1, -1, -1, 0);
199
200 MAX77663_PDATA_INIT(ldo3, 800000, 3950000, NULL, 1, 0, 0,
201                     1, 1, -1, FPS_SRC_1, -1, -1, 0);
202
203 MAX77663_PDATA_INIT(ldo4, 800000, 1587500, NULL, 0, 0, 0,
204                     1, 1, 1000000, FPS_SRC_0, -1, -1, LDO4_EN_TRACKING);
205
206 MAX77663_PDATA_INIT(ldo5, 800000, 2800000, NULL, 0, 0, 0,
207                     1, 1, -1, FPS_SRC_NONE, -1, -1, 0);
208
209 MAX77663_PDATA_INIT(ldo6, 800000, 3950000, NULL, 0, 0, 0,
210                     0, 0, -1, FPS_SRC_NONE, -1, -1, 0);
211
212 MAX77663_PDATA_INIT(ldo7, 800000, 3950000, max77663_rails(sd3), 0, 0, 0,
213                     0, 0, -1, FPS_SRC_NONE, -1, -1, 0);
214
215 MAX77663_PDATA_INIT(ldo8, 800000, 3950000, max77663_rails(sd3), 0, 0, 0,
216                     1, 1, -1, FPS_SRC_1, -1, -1, 0);
217
218 #define MAX77663_REG(_id, _data)                                        \
219         {                                                               \
220                 .name = "max77663-regulator",                           \
221                 .id = MAX77663_REGULATOR_ID_##_id,                      \
222                 .platform_data = &max77663_regulator_pdata_##_data,     \
223                 .pdata_size = sizeof(max77663_regulator_pdata_##_data), \
224         }
225
226 #define MAX77663_RTC()                                                  \
227         {                                                               \
228                 .name = "max77663-rtc",                                 \
229                 .id = 0,                                                \
230         }
231
232 static struct mfd_cell max77663_subdevs[] = {
233         MAX77663_REG(SD0, sd0),
234         MAX77663_REG(SD1, sd1),
235         MAX77663_REG(SD2, sd2),
236         MAX77663_REG(SD3, sd3),
237         MAX77663_REG(LDO0, ldo0),
238         MAX77663_REG(LDO1, ldo1),
239         MAX77663_REG(LDO2, ldo2),
240         MAX77663_REG(LDO3, ldo3),
241         MAX77663_REG(LDO4, ldo4),
242         MAX77663_REG(LDO5, ldo5),
243         MAX77663_REG(LDO6, ldo6),
244         MAX77663_REG(LDO7, ldo7),
245         MAX77663_REG(LDO8, ldo8),
246         MAX77663_RTC(),
247 };
248
249 static struct max77663_gpio_config max77663_gpio_cfgs[] = {
250         {
251                 .gpio = MAX77663_GPIO0,
252                 .dir = GPIO_DIR_OUT,
253                 .dout = GPIO_DOUT_LOW,
254                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
255                 .alternate = GPIO_ALT_DISABLE,
256         },
257         {
258                 .gpio = MAX77663_GPIO1,
259                 .dir = GPIO_DIR_IN,
260                 .dout = GPIO_DOUT_LOW,
261                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
262                 .alternate = GPIO_ALT_DISABLE,
263         },
264         {
265                 .gpio = MAX77663_GPIO2,
266                 .dir = GPIO_DIR_OUT,
267                 .dout = GPIO_DOUT_HIGH,
268                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
269                 .alternate = GPIO_ALT_DISABLE,
270         },
271         {
272                 .gpio = MAX77663_GPIO3,
273                 .dir = GPIO_DIR_OUT,
274                 .dout = GPIO_DOUT_LOW,
275                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
276                 .alternate = GPIO_ALT_ENABLE,
277         },
278         {
279                 .gpio = MAX77663_GPIO4,
280                 .dir = GPIO_DIR_OUT,
281                 .dout = GPIO_DOUT_HIGH,
282                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
283                 .alternate = GPIO_ALT_ENABLE,
284         },
285         {
286                 .gpio = MAX77663_GPIO5,
287                 .dir = GPIO_DIR_OUT,
288                 .dout = GPIO_DOUT_LOW,
289                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
290                 .alternate = GPIO_ALT_DISABLE,
291         },
292         {
293                 .gpio = MAX77663_GPIO6,
294                 .dir = GPIO_DIR_IN,
295                 .alternate = GPIO_ALT_DISABLE,
296         },
297         {
298                 .gpio = MAX77663_GPIO7,
299                 .dir = GPIO_DIR_OUT,
300                 .dout = GPIO_DOUT_LOW,
301                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
302                 .alternate = GPIO_ALT_DISABLE,
303         },
304 };
305
306 static struct max77663_platform_data max7763_pdata = {
307         .irq_base       = MAX77663_IRQ_BASE,
308         .gpio_base      = MAX77663_GPIO_BASE,
309
310         .num_gpio_cfgs  = ARRAY_SIZE(max77663_gpio_cfgs),
311         .gpio_cfgs      = max77663_gpio_cfgs,
312
313         .num_subdevs    = ARRAY_SIZE(max77663_subdevs),
314         .sub_devices    = max77663_subdevs,
315
316         .rtc_i2c_addr   = 0x68,
317
318         .use_power_off  = true,
319 };
320
321 static struct i2c_board_info __initdata max77663_regulators[] = {
322         {
323                 /* The I2C address was determined by OTP factory setting */
324                 I2C_BOARD_INFO("max77663", 0x3c),
325                 .irq            = INT_EXTERNAL_PMU,
326                 .platform_data  = &max7763_pdata,
327         },
328 };
329
330 static int __init kai_max77663_regulator_init(void)
331 {
332         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
333         u32 pmc_ctrl;
334
335         /* configure the power management controller to trigger PMU
336          * interrupts when low */
337         pmc_ctrl = readl(pmc + PMC_CTRL);
338         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
339
340         i2c_register_board_info(4, max77663_regulators,
341                                 ARRAY_SIZE(max77663_regulators));
342
343         return 0;
344 }
345
346 static struct regulator_consumer_supply fixed_reg_en_3v3_sys_a00_supply[] = {
347         REGULATOR_SUPPLY("vdd_3v3", NULL),
348         REGULATOR_SUPPLY("vdd_3v3_devices", NULL),
349         REGULATOR_SUPPLY("debug_cons", NULL),
350         REGULATOR_SUPPLY("pwrdet_pex_ctl", NULL),
351 };
352
353 static struct regulator_consumer_supply fixed_reg_en_3v3_sys_a01_supply[] = {
354         REGULATOR_SUPPLY("vdd_3v3", NULL),
355         REGULATOR_SUPPLY("vdd_3v3_devices", NULL),
356         REGULATOR_SUPPLY("debug_cons", NULL),
357         REGULATOR_SUPPLY("pwrdet_pex_ctl", NULL),
358         REGULATOR_SUPPLY("vddio_gmi", NULL),
359 };
360
361 static struct regulator_consumer_supply fixed_reg_en_avdd_hdmi_usb_a00_supply[] = {
362         REGULATOR_SUPPLY("avdd_hdmi", NULL),
363         REGULATOR_SUPPLY("avdd_usb", NULL),
364         REGULATOR_SUPPLY("vddio_gmi", NULL),
365 };
366
367 static struct regulator_consumer_supply fixed_reg_en_avdd_hdmi_usb_a01_supply[] = {
368         REGULATOR_SUPPLY("avdd_hdmi", NULL),
369         REGULATOR_SUPPLY("avdd_usb", NULL),
370 };
371
372 static struct regulator_consumer_supply fixed_reg_en_1v8_cam_supply[] = {
373         REGULATOR_SUPPLY("vdd_1v8_cam1", NULL),
374         REGULATOR_SUPPLY("vdd_1v8_cam2", NULL),
375         REGULATOR_SUPPLY("vdd_1v8_cam3", NULL),
376 };
377
378 static struct regulator_consumer_supply fixed_reg_en_vddio_vid_supply[] = {
379         REGULATOR_SUPPLY("vdd_hdmi_con", NULL),
380 };
381
382 static struct regulator_consumer_supply fixed_reg_en_3v3_modem_supply[] = {
383         REGULATOR_SUPPLY("vdd_mini_card", NULL),
384 };
385
386 static struct regulator_consumer_supply fixed_reg_en_vdd_pnl_supply[] = {
387         REGULATOR_SUPPLY("vdd_lvds", NULL),
388         REGULATOR_SUPPLY("vdd_lcd_panel", NULL),
389         REGULATOR_SUPPLY("vdd_touch", NULL),
390         REGULATOR_SUPPLY("vddio_ts", NULL),
391 };
392
393 static struct regulator_consumer_supply fixed_reg_en_cam3_ldo_supply[] = {
394         REGULATOR_SUPPLY("vdd_cam3", NULL),
395 };
396
397 static struct regulator_consumer_supply fixed_reg_en_vdd_com_supply[] = {
398         REGULATOR_SUPPLY("vdd_com_bd", NULL),
399 };
400
401 static struct regulator_consumer_supply fixed_reg_en_vdd_sdmmc1_supply[] = {
402         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.0"),
403 };
404
405 static struct regulator_consumer_supply fixed_reg_en_3v3_fuse_supply[] = {
406         REGULATOR_SUPPLY("vdd_fuse", NULL),
407 };
408
409 static struct regulator_consumer_supply fixed_reg_cdc_en_supply[] = {
410         REGULATOR_SUPPLY("cdc_en", NULL),
411 };
412
413 /* Macro for defining fixed regulator sub device data */
414 #define FIXED_SUPPLY(_name) "fixed_reg_"#_name
415 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,   \
416         _gpio_nr, _active_high, _boot_state, _millivolts)       \
417         static struct regulator_init_data ri_data_##_var =              \
418         {                                                               \
419                 .supply_regulator = _in_supply,                         \
420                 .num_consumer_supplies =                                \
421                         ARRAY_SIZE(fixed_reg_##_name##_supply),         \
422                 .consumer_supplies = fixed_reg_##_name##_supply,        \
423                 .constraints = {                                        \
424                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
425                                         REGULATOR_MODE_STANDBY),        \
426                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
427                                         REGULATOR_CHANGE_STATUS |       \
428                                         REGULATOR_CHANGE_VOLTAGE),      \
429                         .always_on = _always_on,                        \
430                         .boot_on = _boot_on,                            \
431                 },                                                      \
432         };                                                              \
433         static struct fixed_voltage_config fixed_reg_##_var##_pdata =   \
434         {                                                               \
435                 .supply_name = FIXED_SUPPLY(_name),                     \
436                 .microvolts = _millivolts * 1000,                       \
437                 .gpio = _gpio_nr,                                       \
438                 .enable_high = _active_high,                            \
439                 .enabled_at_boot = _boot_state,                         \
440                 .init_data = &ri_data_##_var,                           \
441         };                                                              \
442         static struct platform_device fixed_reg_##_var##_dev = {        \
443                 .name = "reg-fixed-voltage",                            \
444                 .id = _id,                                              \
445                 .dev = {                                                \
446                         .platform_data = &fixed_reg_##_var##_pdata,     \
447                 },                                                      \
448         }
449
450
451 /* A00 specific */
452 FIXED_REG(1, en_3v3_sys_a00,    en_3v3_sys_a00,         NULL,
453         1,      0,      MAX77663_GPIO_BASE + MAX77663_GPIO3,    true,   1,      3300);
454 FIXED_REG(2, en_avdd_hdmi_usb_a00, en_avdd_hdmi_usb_a00, FIXED_SUPPLY(en_3v3_sys_a00),
455         1,      0,      MAX77663_GPIO_BASE + MAX77663_GPIO2,    true,   1,      3300);
456 FIXED_REG(3, en_1v8_cam_a00,    en_1v8_cam,             max77663_rails(sd2),
457         0,      0,      TEGRA_GPIO_PS0,                         true,   0,      1800);
458 FIXED_REG(4, en_vddio_vid_a00,  en_vddio_vid,           NULL,
459         0,      0,      TEGRA_GPIO_PB2,                         true,   0,      5000);
460 FIXED_REG(5, en_3v3_modem_a00,  en_3v3_modem,           NULL,
461         0,      1,      TEGRA_GPIO_PP0,                         true,   0,      3300);
462 FIXED_REG(6, en_vdd_pnl_a00,    en_vdd_pnl,             FIXED_SUPPLY(en_3v3_sys_a00),
463         0,      0,      TEGRA_GPIO_PW1,                         true,   0,      3300);
464 FIXED_REG(7, en_cam3_ldo_a00,   en_cam3_ldo,            FIXED_SUPPLY(en_3v3_sys_a00),
465         0,      0,      TEGRA_GPIO_PR7,                         true,   0,      3300);
466 FIXED_REG(8, en_vdd_com_a00,    en_vdd_com,             FIXED_SUPPLY(en_3v3_sys_a00),
467         1,      0,      TEGRA_GPIO_PD0,                         true,   0,      3300);
468 FIXED_REG(9,  en_vdd_sdmmc1_a00, en_vdd_sdmmc1,         FIXED_SUPPLY(en_3v3_sys_a00),
469         0,      0,      TEGRA_GPIO_PC6,                         true,   0,      3300);
470 FIXED_REG(10, en_3v3_fuse_a00,  en_3v3_fuse,            FIXED_SUPPLY(en_3v3_sys_a00),
471         0,      0,      TEGRA_GPIO_PC1,                         true,   0,      3300);
472 FIXED_REG(11, cdc_en_a00,       cdc_en,                 max77663_rails(sd2),
473         0,      1,      TEGRA_GPIO_PX2,                         true,   0,      1200);
474
475 /* A01 specific */
476 FIXED_REG(1, en_3v3_sys_a01,    en_3v3_sys_a01,         NULL,
477         1,      0,      MAX77663_GPIO_BASE + MAX77663_GPIO3,    true,   1,      3300);
478 FIXED_REG(2, en_avdd_hdmi_usb_a01, en_avdd_hdmi_usb_a01, FIXED_SUPPLY(en_3v3_sys_a01),
479         0,      0,      MAX77663_GPIO_BASE + MAX77663_GPIO2,    true,   0,      3300);
480 FIXED_REG(3, en_1v8_cam_a01,    en_1v8_cam,             max77663_rails(sd2),
481         0,      0,      TEGRA_GPIO_PS0,                         true,   0,      1800);
482 FIXED_REG(4, en_vddio_vid_a01,  en_vddio_vid,           NULL,
483         0,      0,      TEGRA_GPIO_PB2,                         true,   0,      5000);
484 FIXED_REG(5, en_3v3_modem_a01,  en_3v3_modem,           NULL,
485         0,      1,      TEGRA_GPIO_PP0,                         true,   0,      3300);
486 FIXED_REG(6, en_vdd_pnl_a01,    en_vdd_pnl,             FIXED_SUPPLY(en_3v3_sys_a01),
487         0,      1,      TEGRA_GPIO_PW1,                         true,   0,      3300);
488 FIXED_REG(7, en_cam3_ldo_a01,   en_cam3_ldo,            FIXED_SUPPLY(en_3v3_sys_a01),
489         0,      0,      TEGRA_GPIO_PR7,                         true,   0,      3300);
490 FIXED_REG(8, en_vdd_com_a01,    en_vdd_com,             FIXED_SUPPLY(en_3v3_sys_a01),
491         1,      0,      TEGRA_GPIO_PD0,                         true,   0,      3300);
492 FIXED_REG(9,  en_vdd_sdmmc1_a01, en_vdd_sdmmc1,         FIXED_SUPPLY(en_3v3_sys_a01),
493         0,      0,      TEGRA_GPIO_PC6,                         true,   0,      3300);
494 FIXED_REG(10, en_3v3_fuse_a01,  en_3v3_fuse,            FIXED_SUPPLY(en_3v3_sys_a01),
495         0,      0,      TEGRA_GPIO_PC1,                         true,   0,      3300);
496 FIXED_REG(11, cdc_en_a01,       cdc_en,                 max77663_rails(sd2),
497         0,      1,      TEGRA_GPIO_PX2,                         true,   0,      1200);
498
499 /*
500  * Creating the fixed regulator device tables
501  */
502
503 #define ADD_FIXED_REG(_name)    (&fixed_reg_##_name##_dev)
504
505 /* A00 specific */
506 #define E1565_A00_FIXED_REG \
507         ADD_FIXED_REG(en_3v3_sys_a00),          \
508         ADD_FIXED_REG(en_avdd_hdmi_usb_a00),    \
509         ADD_FIXED_REG(en_1v8_cam_a00),          \
510         ADD_FIXED_REG(en_vddio_vid_a00),        \
511         ADD_FIXED_REG(en_3v3_modem_a00),        \
512         ADD_FIXED_REG(en_vdd_pnl_a00),          \
513         ADD_FIXED_REG(en_cam3_ldo_a00),         \
514         ADD_FIXED_REG(en_vdd_com_a00),          \
515         ADD_FIXED_REG(en_vdd_sdmmc1_a00),       \
516         ADD_FIXED_REG(en_3v3_fuse_a00),         \
517         ADD_FIXED_REG(cdc_en_a00),              \
518
519 /* A01 specific */
520 #define E1565_A01_FIXED_REG \
521         ADD_FIXED_REG(en_3v3_sys_a01),          \
522         ADD_FIXED_REG(en_avdd_hdmi_usb_a01),    \
523         ADD_FIXED_REG(en_1v8_cam_a01),          \
524         ADD_FIXED_REG(en_vddio_vid_a01),        \
525         ADD_FIXED_REG(en_3v3_modem_a01),        \
526         ADD_FIXED_REG(en_vdd_pnl_a01),          \
527         ADD_FIXED_REG(en_cam3_ldo_a01),         \
528         ADD_FIXED_REG(en_vdd_com_a01),          \
529         ADD_FIXED_REG(en_vdd_sdmmc1_a01),       \
530         ADD_FIXED_REG(en_3v3_fuse_a01),         \
531         ADD_FIXED_REG(cdc_en_a01),              \
532
533 /* Gpio switch regulator platform data for Kai A00 */
534 static struct platform_device *fixed_reg_devs_a00[] = {
535         E1565_A00_FIXED_REG
536 };
537
538 /* Gpio switch regulator platform data for Kai A01 */
539 static struct platform_device *fixed_reg_devs_a01[] = {
540         E1565_A01_FIXED_REG
541 };
542
543 static int __init kai_fixed_regulator_init(void)
544 {
545         int i;
546         struct board_info board_info;
547         struct platform_device **fixed_reg_devs;
548         int nfixreg_devs;
549
550         tegra_get_board_info(&board_info);
551
552         if (board_info.fab == BOARD_FAB_A00) {
553                 fixed_reg_devs = fixed_reg_devs_a00;
554                 nfixreg_devs = ARRAY_SIZE(fixed_reg_devs_a00);
555         } else {
556                 fixed_reg_devs = fixed_reg_devs_a01;
557                 nfixreg_devs = ARRAY_SIZE(fixed_reg_devs_a01);
558         }
559
560         if (!machine_is_kai())
561                 return 0;
562
563         for (i = 0; i < nfixreg_devs; ++i) {
564                 int gpio_nr;
565                 struct fixed_voltage_config *fixed_reg_pdata =
566                         fixed_reg_devs[i]->dev.platform_data;
567                 gpio_nr = fixed_reg_pdata->gpio;
568
569         }
570
571         return platform_add_devices(fixed_reg_devs, nfixreg_devs);
572 }
573 subsys_initcall_sync(kai_fixed_regulator_init);
574
575 int __init kai_regulator_init(void)
576 {
577         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
578         u32 pmc_ctrl;
579         int ret;
580
581         /* configure the power management controller to trigger PMU
582          * interrupts when low */
583
584         pmc_ctrl = readl(pmc + PMC_CTRL);
585         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
586
587         ret = kai_max77663_regulator_init();
588         if (ret < 0)
589                 return ret;
590
591         return 0;
592 }
593
594 static void kai_board_suspend(int lp_state, enum suspend_stage stg)
595 {
596         if ((lp_state == TEGRA_SUSPEND_LP1) && (stg == TEGRA_SUSPEND_BEFORE_CPU))
597                 tegra_console_uart_suspend();
598 }
599
600 static void kai_board_resume(int lp_state, enum resume_stage stg)
601 {
602         if ((lp_state == TEGRA_SUSPEND_LP1) && (stg == TEGRA_RESUME_AFTER_CPU))
603                 tegra_console_uart_resume();
604 }
605
606 static struct tegra_suspend_platform_data kai_suspend_data = {
607         .cpu_timer      = 2000,
608         .cpu_off_timer  = 200,
609         .suspend_mode   = TEGRA_SUSPEND_LP0,
610         .core_timer     = 0x7e7e,
611         .core_off_timer = 0,
612         .corereq_high   = true,
613         .sysclkreq_high = true,
614         .cpu_lp2_min_residency = 2000,
615         .board_suspend = kai_board_suspend,
616         .board_resume = kai_board_resume,
617 #ifdef CONFIG_TEGRA_LP1_950
618         .lp1_lowvolt_support = true,
619         .i2c_base_addr = TEGRA_I2C5_BASE,
620         .pmuslave_addr = 0x78,
621         .core_reg_addr = 0x17,
622         .lp1_core_volt_low = 0x0C,
623         .lp1_core_volt_high = 0x20,
624 #endif
625 };
626
627 int __init kai_suspend_init(void)
628 {
629         tegra_init_suspend(&kai_suspend_data);
630         return 0;
631 }
632
633 static struct tegra_tsensor_pmu_data  tpdata = {
634         .poweroff_reg_addr = 0x3F,
635         .poweroff_reg_data = 0x80,
636         .reset_tegra = 1,
637         .controller_type = 0,
638         .i2c_controller_id = 4,
639         .pinmux = 0,
640         .pmu_16bit_ops = 0,
641         .pmu_i2c_addr = 0x2D,
642 };
643
644 void __init kai_tsensor_init(void)
645 {
646         tegra3_tsensor_init(&tpdata);
647 }
648
649 #ifdef CONFIG_TEGRA_EDP_LIMITS
650
651 int __init kai_edp_init(void)
652 {
653         unsigned int regulator_mA;
654
655         regulator_mA = get_maximum_cpu_current_supported();
656         if (!regulator_mA)
657                 regulator_mA = 6000; /* regular T30/s */
658         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
659
660         tegra_init_cpu_edp_limits(regulator_mA);
661         return 0;
662 }
663 #endif