rtc: tps80031: register as mfd sub device
[linux-2.6.git] / arch / arm / mach-tegra / board-kai-memory.c
1 /*
2  * Copyright (C) 2011 NVIDIA, Inc.
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope that it will be useful,
9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11  * GNU General Public License for more details.
12  *
13  * You should have received a copy of the GNU General Public License
14  * along with this program; if not, write to the Free Software
15  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
16  * 02111-1307, USA
17  */
18
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21
22 #include "board.h"
23 #include "board-kai.h"
24 #include "tegra3_emc.h"
25 #include "fuse.h"
26
27
28 static const struct tegra_emc_table kai_emc_tables_h5tc4g[] = {
29         {
30                 0x32,       /* Rev 3.2 */
31                 25500,      /* SDRAM frequency */
32                 {
33                         0x00000001, /* EMC_RC */
34                         0x00000007, /* EMC_RFC */
35                         0x00000000, /* EMC_RAS */
36                         0x00000000, /* EMC_RP */
37                         0x00000002, /* EMC_R2W */
38                         0x0000000a, /* EMC_W2R */
39                         0x00000005, /* EMC_R2P */
40                         0x0000000b, /* EMC_W2P */
41                         0x00000000, /* EMC_RD_RCD */
42                         0x00000000, /* EMC_WR_RCD */
43                         0x00000003, /* EMC_RRD */
44                         0x00000001, /* EMC_REXT */
45                         0x00000000, /* EMC_WEXT */
46                         0x00000005, /* EMC_WDV */
47                         0x00000005, /* EMC_QUSE */
48                         0x00000004, /* EMC_QRST */
49                         0x00000009, /* EMC_QSAFE */
50                         0x0000000b, /* EMC_RDV */
51                         0x000000c0, /* EMC_REFRESH */
52                         0x00000000, /* EMC_BURST_REFRESH_NUM */
53                         0x00000030, /* EMC_PRE_REFRESH_REQ_CNT */
54                         0x00000002, /* EMC_PDEX2WR */
55                         0x00000002, /* EMC_PDEX2RD */
56                         0x00000001, /* EMC_PCHG2PDEN */
57                         0x00000000, /* EMC_ACT2PDEN */
58                         0x00000007, /* EMC_AR2PDEN */
59                         0x0000000f, /* EMC_RW2PDEN */
60                         0x00000008, /* EMC_TXSR */
61                         0x00000008, /* EMC_TXSRDLL */
62                         0x00000004, /* EMC_TCKE */
63                         0x00000002, /* EMC_TFAW */
64                         0x00000000, /* EMC_TRPAB */
65                         0x00000004, /* EMC_TCLKSTABLE */
66                         0x00000005, /* EMC_TCLKSTOP */
67                         0x000000c7, /* EMC_TREFBW */
68                         0x00000006, /* EMC_QUSE_EXTRA */
69                         0x00000004, /* EMC_FBIO_CFG6 */
70                         0x00000000, /* EMC_ODT_WRITE */
71                         0x00000000, /* EMC_ODT_READ */
72                         0x00004288, /* EMC_FBIO_CFG5 */
73                         0x007800a4, /* EMC_CFG_DIG_DLL */
74                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
75                         0x000fc000, /* EMC_DLL_XFORM_DQS0 */
76                         0x000fc000, /* EMC_DLL_XFORM_DQS1 */
77                         0x000fc000, /* EMC_DLL_XFORM_DQS2 */
78                         0x000fc000, /* EMC_DLL_XFORM_DQS3 */
79                         0x000fc000, /* EMC_DLL_XFORM_DQS4 */
80                         0x000fc000, /* EMC_DLL_XFORM_DQS5 */
81                         0x000fc000, /* EMC_DLL_XFORM_DQS6 */
82                         0x000fc000, /* EMC_DLL_XFORM_DQS7 */
83                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
84                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
85                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
86                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
87                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
88                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
89                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
90                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
91                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
92                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
93                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
94                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
95                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
96                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
97                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
98                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
99                         0x000fc000, /* EMC_DLL_XFORM_DQ0 */
100                         0x000fc000, /* EMC_DLL_XFORM_DQ1 */
101                         0x000fc000, /* EMC_DLL_XFORM_DQ2 */
102                         0x000fc000, /* EMC_DLL_XFORM_DQ3 */
103                         0x000002a0, /* EMC_XM2CMDPADCTRL */
104                         0x0800211c, /* EMC_XM2DQSPADCTRL2 */
105                         0x00000000, /* EMC_XM2DQPADCTRL2 */
106                         0x77fff884, /* EMC_XM2CLKPADCTRL */
107                         0x01f1f108, /* EMC_XM2COMPPADCTRL */
108                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
109                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
110                         0x08000168, /* EMC_XM2QUSEPADCTRL */
111                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
112                         0x00000802, /* EMC_CTT_TERM_CTRL */
113                         0x00000000, /* EMC_ZCAL_INTERVAL */
114                         0x00000040, /* EMC_ZCAL_WAIT_CNT */
115                         0x000c000c, /* EMC_MRS_WAIT_CNT */
116                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
117                         0x00000000, /* EMC_CTT */
118                         0x00000000, /* EMC_CTT_DURATION */
119                         0x80000287, /* EMC_DYN_SELF_REF_CONTROL */
120                         0x00020001, /* MC_EMEM_ARB_CFG */
121                         0xc0000008, /* MC_EMEM_ARB_OUTSTANDING_REQ */
122                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
123                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
124                         0x00000002, /* MC_EMEM_ARB_TIMING_RC */
125                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
126                         0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
127                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
128                         0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
129                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
130                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
131                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
132                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
133                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
134                         0x06020102, /* MC_EMEM_ARB_DA_TURNS */
135                         0x000a0502, /* MC_EMEM_ARB_DA_COVERS */
136                         0x75e30303, /* MC_EMEM_ARB_MISC0 */
137                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
138                         0xe8000000, /* EMC_FBIO_SPARE */
139                         0xff00ff00, /* EMC_CFG_RSV */
140                 },
141                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
142                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
143                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
144                 0x80001221, /* Mode Register 0 */
145                 0x80100003, /* Mode Register 1 */
146                 0x80200008, /* Mode Register 2 */
147                 0x00000001, /* EMC_CFG.DYN_SELF_REF */
148         },
149         {
150                 0x32,       /* Rev 3.2 */
151                 51000,      /* SDRAM frequency */
152                 {
153                         0x00000002, /* EMC_RC */
154                         0x0000000f, /* EMC_RFC */
155                         0x00000001, /* EMC_RAS */
156                         0x00000000, /* EMC_RP */
157                         0x00000002, /* EMC_R2W */
158                         0x0000000a, /* EMC_W2R */
159                         0x00000005, /* EMC_R2P */
160                         0x0000000b, /* EMC_W2P */
161                         0x00000000, /* EMC_RD_RCD */
162                         0x00000000, /* EMC_WR_RCD */
163                         0x00000003, /* EMC_RRD */
164                         0x00000001, /* EMC_REXT */
165                         0x00000000, /* EMC_WEXT */
166                         0x00000005, /* EMC_WDV */
167                         0x00000005, /* EMC_QUSE */
168                         0x00000004, /* EMC_QRST */
169                         0x00000009, /* EMC_QSAFE */
170                         0x0000000b, /* EMC_RDV */
171                         0x00000181, /* EMC_REFRESH */
172                         0x00000000, /* EMC_BURST_REFRESH_NUM */
173                         0x00000060, /* EMC_PRE_REFRESH_REQ_CNT */
174                         0x00000002, /* EMC_PDEX2WR */
175                         0x00000002, /* EMC_PDEX2RD */
176                         0x00000001, /* EMC_PCHG2PDEN */
177                         0x00000000, /* EMC_ACT2PDEN */
178                         0x00000007, /* EMC_AR2PDEN */
179                         0x0000000f, /* EMC_RW2PDEN */
180                         0x00000010, /* EMC_TXSR */
181                         0x00000010, /* EMC_TXSRDLL */
182                         0x00000004, /* EMC_TCKE */
183                         0x00000003, /* EMC_TFAW */
184                         0x00000000, /* EMC_TRPAB */
185                         0x00000004, /* EMC_TCLKSTABLE */
186                         0x00000005, /* EMC_TCLKSTOP */
187                         0x0000018e, /* EMC_TREFBW */
188                         0x00000006, /* EMC_QUSE_EXTRA */
189                         0x00000004, /* EMC_FBIO_CFG6 */
190                         0x00000000, /* EMC_ODT_WRITE */
191                         0x00000000, /* EMC_ODT_READ */
192                         0x00004288, /* EMC_FBIO_CFG5 */
193                         0x007800a4, /* EMC_CFG_DIG_DLL */
194                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
195                         0x000fc000, /* EMC_DLL_XFORM_DQS0 */
196                         0x000fc000, /* EMC_DLL_XFORM_DQS1 */
197                         0x000fc000, /* EMC_DLL_XFORM_DQS2 */
198                         0x000fc000, /* EMC_DLL_XFORM_DQS3 */
199                         0x000fc000, /* EMC_DLL_XFORM_DQS4 */
200                         0x000fc000, /* EMC_DLL_XFORM_DQS5 */
201                         0x000fc000, /* EMC_DLL_XFORM_DQS6 */
202                         0x000fc000, /* EMC_DLL_XFORM_DQS7 */
203                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
204                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
205                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
206                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
207                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
208                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
209                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
210                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
211                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
212                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
213                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
214                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
215                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
216                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
217                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
218                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
219                         0x000fc000, /* EMC_DLL_XFORM_DQ0 */
220                         0x000fc000, /* EMC_DLL_XFORM_DQ1 */
221                         0x000fc000, /* EMC_DLL_XFORM_DQ2 */
222                         0x000fc000, /* EMC_DLL_XFORM_DQ3 */
223                         0x000002a0, /* EMC_XM2CMDPADCTRL */
224                         0x0800211c, /* EMC_XM2DQSPADCTRL2 */
225                         0x00000000, /* EMC_XM2DQPADCTRL2 */
226                         0x77fff884, /* EMC_XM2CLKPADCTRL */
227                         0x01f1f108, /* EMC_XM2COMPPADCTRL */
228                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
229                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
230                         0x08000168, /* EMC_XM2QUSEPADCTRL */
231                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
232                         0x00000802, /* EMC_CTT_TERM_CTRL */
233                         0x00000000, /* EMC_ZCAL_INTERVAL */
234                         0x00000040, /* EMC_ZCAL_WAIT_CNT */
235                         0x000c000c, /* EMC_MRS_WAIT_CNT */
236                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
237                         0x00000000, /* EMC_CTT */
238                         0x00000000, /* EMC_CTT_DURATION */
239                         0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */
240                         0x00010001, /* MC_EMEM_ARB_CFG */
241                         0xc000000a, /* MC_EMEM_ARB_OUTSTANDING_REQ */
242                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
243                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
244                         0x00000002, /* MC_EMEM_ARB_TIMING_RC */
245                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
246                         0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
247                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
248                         0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
249                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
250                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
251                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
252                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
253                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
254                         0x06020102, /* MC_EMEM_ARB_DA_TURNS */
255                         0x000a0502, /* MC_EMEM_ARB_DA_COVERS */
256                         0x74e30303, /* MC_EMEM_ARB_MISC0 */
257                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
258                         0xe8000000, /* EMC_FBIO_SPARE */
259                         0xff00ff00, /* EMC_CFG_RSV */
260                 },
261                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
262                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
263                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
264                 0x80001221, /* Mode Register 0 */
265                 0x80100003, /* Mode Register 1 */
266                 0x80200008, /* Mode Register 2 */
267                 0x00000001, /* EMC_CFG.DYN_SELF_REF */
268         },
269         {
270                 0x32,       /* Rev 3.2 */
271                 102000,     /* SDRAM frequency */
272                 {
273                         0x00000005, /* EMC_RC */
274                         0x0000001e, /* EMC_RFC */
275                         0x00000003, /* EMC_RAS */
276                         0x00000001, /* EMC_RP */
277                         0x00000002, /* EMC_R2W */
278                         0x0000000a, /* EMC_W2R */
279                         0x00000005, /* EMC_R2P */
280                         0x0000000b, /* EMC_W2P */
281                         0x00000001, /* EMC_RD_RCD */
282                         0x00000001, /* EMC_WR_RCD */
283                         0x00000003, /* EMC_RRD */
284                         0x00000001, /* EMC_REXT */
285                         0x00000000, /* EMC_WEXT */
286                         0x00000005, /* EMC_WDV */
287                         0x00000005, /* EMC_QUSE */
288                         0x00000004, /* EMC_QRST */
289                         0x00000009, /* EMC_QSAFE */
290                         0x0000000b, /* EMC_RDV */
291                         0x00000303, /* EMC_REFRESH */
292                         0x00000000, /* EMC_BURST_REFRESH_NUM */
293                         0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */
294                         0x00000002, /* EMC_PDEX2WR */
295                         0x00000002, /* EMC_PDEX2RD */
296                         0x00000001, /* EMC_PCHG2PDEN */
297                         0x00000000, /* EMC_ACT2PDEN */
298                         0x00000007, /* EMC_AR2PDEN */
299                         0x0000000f, /* EMC_RW2PDEN */
300                         0x00000020, /* EMC_TXSR */
301                         0x00000020, /* EMC_TXSRDLL */
302                         0x00000004, /* EMC_TCKE */
303                         0x00000005, /* EMC_TFAW */
304                         0x00000000, /* EMC_TRPAB */
305                         0x00000004, /* EMC_TCLKSTABLE */
306                         0x00000005, /* EMC_TCLKSTOP */
307                         0x0000031c, /* EMC_TREFBW */
308                         0x00000006, /* EMC_QUSE_EXTRA */
309                         0x00000004, /* EMC_FBIO_CFG6 */
310                         0x00000000, /* EMC_ODT_WRITE */
311                         0x00000000, /* EMC_ODT_READ */
312                         0x00004288, /* EMC_FBIO_CFG5 */
313                         0x007800a4, /* EMC_CFG_DIG_DLL */
314                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
315                         0x000fc000, /* EMC_DLL_XFORM_DQS0 */
316                         0x000fc000, /* EMC_DLL_XFORM_DQS1 */
317                         0x000fc000, /* EMC_DLL_XFORM_DQS2 */
318                         0x000fc000, /* EMC_DLL_XFORM_DQS3 */
319                         0x000fc000, /* EMC_DLL_XFORM_DQS4 */
320                         0x000fc000, /* EMC_DLL_XFORM_DQS5 */
321                         0x000fc000, /* EMC_DLL_XFORM_DQS6 */
322                         0x000fc000, /* EMC_DLL_XFORM_DQS7 */
323                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
324                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
325                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
326                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
327                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
328                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
329                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
330                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
331                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
332                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
333                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
334                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
335                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
336                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
337                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
338                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
339                         0x000fc000, /* EMC_DLL_XFORM_DQ0 */
340                         0x000fc000, /* EMC_DLL_XFORM_DQ1 */
341                         0x000fc000, /* EMC_DLL_XFORM_DQ2 */
342                         0x000fc000, /* EMC_DLL_XFORM_DQ3 */
343                         0x000002a0, /* EMC_XM2CMDPADCTRL */
344                         0x0800211c, /* EMC_XM2DQSPADCTRL2 */
345                         0x00000000, /* EMC_XM2DQPADCTRL2 */
346                         0x77fff884, /* EMC_XM2CLKPADCTRL */
347                         0x01f1f108, /* EMC_XM2COMPPADCTRL */
348                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
349                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
350                         0x08000168, /* EMC_XM2QUSEPADCTRL */
351                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
352                         0x00000802, /* EMC_CTT_TERM_CTRL */
353                         0x00000000, /* EMC_ZCAL_INTERVAL */
354                         0x00000040, /* EMC_ZCAL_WAIT_CNT */
355                         0x000c000c, /* EMC_MRS_WAIT_CNT */
356                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
357                         0x00000000, /* EMC_CTT */
358                         0x00000000, /* EMC_CTT_DURATION */
359                         0x80000713, /* EMC_DYN_SELF_REF_CONTROL */
360                         0x00000001, /* MC_EMEM_ARB_CFG */
361                         0xc0000013, /* MC_EMEM_ARB_OUTSTANDING_REQ */
362                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
363                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
364                         0x00000003, /* MC_EMEM_ARB_TIMING_RC */
365                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
366                         0x00000002, /* MC_EMEM_ARB_TIMING_FAW */
367                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
368                         0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
369                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
370                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
371                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
372                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
373                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
374                         0x06020102, /* MC_EMEM_ARB_DA_TURNS */
375                         0x000a0503, /* MC_EMEM_ARB_DA_COVERS */
376                         0x74430504, /* MC_EMEM_ARB_MISC0 */
377                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
378                         0xe8000000, /* EMC_FBIO_SPARE */
379                         0xff00ff00, /* EMC_CFG_RSV */
380                 },
381                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
382                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
383                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
384                 0x80001221, /* Mode Register 0 */
385                 0x80100003, /* Mode Register 1 */
386                 0x80200008, /* Mode Register 2 */
387                 0x00000001, /* EMC_CFG.DYN_SELF_REF */
388         },
389         {
390                 0x32,       /* Rev 3.2 */
391                 204000,     /* SDRAM frequency */
392                 {
393                         0x0000000a, /* EMC_RC */
394                         0x0000003d, /* EMC_RFC */
395                         0x00000007, /* EMC_RAS */
396                         0x00000002, /* EMC_RP */
397                         0x00000002, /* EMC_R2W */
398                         0x0000000a, /* EMC_W2R */
399                         0x00000005, /* EMC_R2P */
400                         0x0000000b, /* EMC_W2P */
401                         0x00000002, /* EMC_RD_RCD */
402                         0x00000002, /* EMC_WR_RCD */
403                         0x00000003, /* EMC_RRD */
404                         0x00000001, /* EMC_REXT */
405                         0x00000000, /* EMC_WEXT */
406                         0x00000005, /* EMC_WDV */
407                         0x00000005, /* EMC_QUSE */
408                         0x00000004, /* EMC_QRST */
409                         0x0000000a, /* EMC_QSAFE */
410                         0x0000000b, /* EMC_RDV */
411                         0x00000607, /* EMC_REFRESH */
412                         0x00000000, /* EMC_BURST_REFRESH_NUM */
413                         0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */
414                         0x00000002, /* EMC_PDEX2WR */
415                         0x00000002, /* EMC_PDEX2RD */
416                         0x00000001, /* EMC_PCHG2PDEN */
417                         0x00000000, /* EMC_ACT2PDEN */
418                         0x00000007, /* EMC_AR2PDEN */
419                         0x0000000f, /* EMC_RW2PDEN */
420                         0x00000040, /* EMC_TXSR */
421                         0x00000040, /* EMC_TXSRDLL */
422                         0x00000004, /* EMC_TCKE */
423                         0x0000000a, /* EMC_TFAW */
424                         0x00000000, /* EMC_TRPAB */
425                         0x00000004, /* EMC_TCLKSTABLE */
426                         0x00000005, /* EMC_TCLKSTOP */
427                         0x00000638, /* EMC_TREFBW */
428                         0x00000006, /* EMC_QUSE_EXTRA */
429                         0x00000006, /* EMC_FBIO_CFG6 */
430                         0x00000000, /* EMC_ODT_WRITE */
431                         0x00000000, /* EMC_ODT_READ */
432                         0x00004288, /* EMC_FBIO_CFG5 */
433                         0x004400a4, /* EMC_CFG_DIG_DLL */
434                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
435                         0x00080000, /* EMC_DLL_XFORM_DQS0 */
436                         0x00080000, /* EMC_DLL_XFORM_DQS1 */
437                         0x00080000, /* EMC_DLL_XFORM_DQS2 */
438                         0x00080000, /* EMC_DLL_XFORM_DQS3 */
439                         0x00080000, /* EMC_DLL_XFORM_DQS4 */
440                         0x00080000, /* EMC_DLL_XFORM_DQS5 */
441                         0x00080000, /* EMC_DLL_XFORM_DQS6 */
442                         0x00080000, /* EMC_DLL_XFORM_DQS7 */
443                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
444                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
445                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
446                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
447                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
448                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
449                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
450                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
451                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
452                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
453                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
454                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
455                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
456                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
457                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
458                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
459                         0x00080000, /* EMC_DLL_XFORM_DQ0 */
460                         0x00080000, /* EMC_DLL_XFORM_DQ1 */
461                         0x00080000, /* EMC_DLL_XFORM_DQ2 */
462                         0x00080000, /* EMC_DLL_XFORM_DQ3 */
463                         0x000002a0, /* EMC_XM2CMDPADCTRL */
464                         0x0800211c, /* EMC_XM2DQSPADCTRL2 */
465                         0x00000000, /* EMC_XM2DQPADCTRL2 */
466                         0x77fff884, /* EMC_XM2CLKPADCTRL */
467                         0x01f1f108, /* EMC_XM2COMPPADCTRL */
468                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
469                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
470                         0x08000168, /* EMC_XM2QUSEPADCTRL */
471                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
472                         0x00000802, /* EMC_CTT_TERM_CTRL */
473                         0x00020000, /* EMC_ZCAL_INTERVAL */
474                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
475                         0x000c000c, /* EMC_MRS_WAIT_CNT */
476                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
477                         0x00000000, /* EMC_CTT */
478                         0x00000000, /* EMC_CTT_DURATION */
479                         0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */
480                         0x00000003, /* MC_EMEM_ARB_CFG */
481                         0xc0000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */
482                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
483                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
484                         0x00000005, /* MC_EMEM_ARB_TIMING_RC */
485                         0x00000002, /* MC_EMEM_ARB_TIMING_RAS */
486                         0x00000004, /* MC_EMEM_ARB_TIMING_FAW */
487                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
488                         0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
489                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
490                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
491                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
492                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
493                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
494                         0x06020102, /* MC_EMEM_ARB_DA_TURNS */
495                         0x000a0505, /* MC_EMEM_ARB_DA_COVERS */
496                         0x74040a06, /* MC_EMEM_ARB_MISC0 */
497                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
498                         0xe8000000, /* EMC_FBIO_SPARE */
499                         0xff00ff00, /* EMC_CFG_RSV */
500                 },
501                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
502                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
503                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
504                 0x80001221, /* Mode Register 0 */
505                 0x80100003, /* Mode Register 1 */
506                 0x80200008, /* Mode Register 2 */
507                 0x00000001, /* EMC_CFG.DYN_SELF_REF */
508         },
509         {
510                 0x32,       /* Rev 3.2 */
511                 333500,     /* SDRAM frequency */
512                 {
513                         0x0000000f, /* EMC_RC */
514                         0x00000063, /* EMC_RFC */
515                         0x0000000a, /* EMC_RAS */
516                         0x00000003, /* EMC_RP */
517                         0x00000003, /* EMC_R2W */
518                         0x00000008, /* EMC_W2R */
519                         0x00000002, /* EMC_R2P */
520                         0x00000009, /* EMC_W2P */
521                         0x00000003, /* EMC_RD_RCD */
522                         0x00000003, /* EMC_WR_RCD */
523                         0x00000002, /* EMC_RRD */
524                         0x00000001, /* EMC_REXT */
525                         0x00000000, /* EMC_WEXT */
526                         0x00000004, /* EMC_WDV */
527                         0x00000006, /* EMC_QUSE */
528                         0x00000004, /* EMC_QRST */
529                         0x0000000a, /* EMC_QSAFE */
530                         0x0000000c, /* EMC_RDV */
531                         0x000009e9, /* EMC_REFRESH */
532                         0x00000000, /* EMC_BURST_REFRESH_NUM */
533                         0x0000027a, /* EMC_PRE_REFRESH_REQ_CNT */
534                         0x00000001, /* EMC_PDEX2WR */
535                         0x00000008, /* EMC_PDEX2RD */
536                         0x00000001, /* EMC_PCHG2PDEN */
537                         0x00000000, /* EMC_ACT2PDEN */
538                         0x00000007, /* EMC_AR2PDEN */
539                         0x0000000e, /* EMC_RW2PDEN */
540                         0x00000068, /* EMC_TXSR */
541                         0x00000200, /* EMC_TXSRDLL */
542                         0x00000004, /* EMC_TCKE */
543                         0x0000000f, /* EMC_TFAW */
544                         0x00000000, /* EMC_TRPAB */
545                         0x00000004, /* EMC_TCLKSTABLE */
546                         0x00000005, /* EMC_TCLKSTOP */
547                         0x00000a2a, /* EMC_TREFBW */
548                         0x00000000, /* EMC_QUSE_EXTRA */
549                         0x00000004, /* EMC_FBIO_CFG6 */
550                         0x00000000, /* EMC_ODT_WRITE */
551                         0x00000000, /* EMC_ODT_READ */
552                         0x00007088, /* EMC_FBIO_CFG5 */
553                         0x002600a4, /* EMC_CFG_DIG_DLL */
554                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
555                         0x00034000, /* EMC_DLL_XFORM_DQS0 */
556                         0x00034000, /* EMC_DLL_XFORM_DQS1 */
557                         0x00034000, /* EMC_DLL_XFORM_DQS2 */
558                         0x00034000, /* EMC_DLL_XFORM_DQS3 */
559                         0x00034000, /* EMC_DLL_XFORM_DQS4 */
560                         0x00034000, /* EMC_DLL_XFORM_DQS5 */
561                         0x00034000, /* EMC_DLL_XFORM_DQS6 */
562                         0x00034000, /* EMC_DLL_XFORM_DQS7 */
563                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
564                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
565                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
566                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
567                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
568                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
569                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
570                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
571                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
572                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
573                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
574                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
575                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
576                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
577                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
578                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
579                         0x00034000, /* EMC_DLL_XFORM_DQ0 */
580                         0x00034000, /* EMC_DLL_XFORM_DQ1 */
581                         0x00034000, /* EMC_DLL_XFORM_DQ2 */
582                         0x00034000, /* EMC_DLL_XFORM_DQ3 */
583                         0x000002a0, /* EMC_XM2CMDPADCTRL */
584                         0x0800013d, /* EMC_XM2DQSPADCTRL2 */
585                         0x00000000, /* EMC_XM2DQPADCTRL2 */
586                         0x77fff884, /* EMC_XM2CLKPADCTRL */
587                         0x01f1f508, /* EMC_XM2COMPPADCTRL */
588                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
589                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
590                         0x080001e8, /* EMC_XM2QUSEPADCTRL */
591                         0x08000021, /* EMC_XM2DQSPADCTRL3 */
592                         0x00000802, /* EMC_CTT_TERM_CTRL */
593                         0x00020000, /* EMC_ZCAL_INTERVAL */
594                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
595                         0x015c000c, /* EMC_MRS_WAIT_CNT */
596                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
597                         0x00000000, /* EMC_CTT */
598                         0x00000000, /* EMC_CTT_DURATION */
599                         0x800014d4, /* EMC_DYN_SELF_REF_CONTROL */
600                         0x00000005, /* MC_EMEM_ARB_CFG */
601                         0x8000003d, /* MC_EMEM_ARB_OUTSTANDING_REQ */
602                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
603                         0x00000002, /* MC_EMEM_ARB_TIMING_RP */
604                         0x00000008, /* MC_EMEM_ARB_TIMING_RC */
605                         0x00000004, /* MC_EMEM_ARB_TIMING_RAS */
606                         0x00000007, /* MC_EMEM_ARB_TIMING_FAW */
607                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
608                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
609                         0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */
610                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
611                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
612                         0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
613                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
614                         0x06030202, /* MC_EMEM_ARB_DA_TURNS */
615                         0x000b0608, /* MC_EMEM_ARB_DA_COVERS */
616                         0x70850f09, /* MC_EMEM_ARB_MISC0 */
617                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
618                         0xe8000000, /* EMC_FBIO_SPARE */
619                         0xff00ff89, /* EMC_CFG_RSV */
620                 },
621                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
622                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
623                 0x00000000, /* EMC_CFG.PERIODIC_QRST */
624                 0x80000321, /* Mode Register 0 */
625                 0x80100002, /* Mode Register 1 */
626                 0x80200000, /* Mode Register 2 */
627                 0x00000000, /* EMC_CFG.DYN_SELF_REF */
628         },
629         {
630                 0x32,       /* Rev 3.2 */
631                 667000,     /* SDRAM frequency */
632                 {
633                         0x00000020, /* EMC_RC */
634                         0x000000c7, /* EMC_RFC */
635                         0x00000017, /* EMC_RAS */
636                         0x00000007, /* EMC_RP */
637                         0x00000005, /* EMC_R2W */
638                         0x0000000c, /* EMC_W2R */
639                         0x00000003, /* EMC_R2P */
640                         0x00000011, /* EMC_W2P */
641                         0x00000007, /* EMC_RD_RCD */
642                         0x00000007, /* EMC_WR_RCD */
643                         0x00000002, /* EMC_RRD */
644                         0x00000001, /* EMC_REXT */
645                         0x00000000, /* EMC_WEXT */
646                         0x00000007, /* EMC_WDV */
647                         0x0000000a, /* EMC_QUSE */
648                         0x00000009, /* EMC_QRST */
649                         0x0000000d, /* EMC_QSAFE */
650                         0x00000012, /* EMC_RDV */
651                         0x00001412, /* EMC_REFRESH */
652                         0x00000000, /* EMC_BURST_REFRESH_NUM */
653                         0x00000504, /* EMC_PRE_REFRESH_REQ_CNT */
654                         0x00000002, /* EMC_PDEX2WR */
655                         0x0000000e, /* EMC_PDEX2RD */
656                         0x00000001, /* EMC_PCHG2PDEN */
657                         0x00000000, /* EMC_ACT2PDEN */
658                         0x0000000c, /* EMC_AR2PDEN */
659                         0x00000016, /* EMC_RW2PDEN */
660                         0x000000cf, /* EMC_TXSR */
661                         0x00000200, /* EMC_TXSRDLL */
662                         0x00000005, /* EMC_TCKE */
663                         0x0000001f, /* EMC_TFAW */
664                         0x00000000, /* EMC_TRPAB */
665                         0x00000006, /* EMC_TCLKSTABLE */
666                         0x00000007, /* EMC_TCLKSTOP */
667                         0x00001453, /* EMC_TREFBW */
668                         0x0000000b, /* EMC_QUSE_EXTRA */
669                         0x00000006, /* EMC_FBIO_CFG6 */
670                         0x00000000, /* EMC_ODT_WRITE */
671                         0x00000000, /* EMC_ODT_READ */
672                         0x00005088, /* EMC_FBIO_CFG5 */
673                         0xf00b0191, /* EMC_CFG_DIG_DLL */
674                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
675                         0x0000000a, /* EMC_DLL_XFORM_DQS0 */
676                         0x0000000a, /* EMC_DLL_XFORM_DQS1 */
677                         0x00000008, /* EMC_DLL_XFORM_DQS2 */
678                         0x0000000a, /* EMC_DLL_XFORM_DQS3 */
679                         0x0000000a, /* EMC_DLL_XFORM_DQS4 */
680                         0x0000000a, /* EMC_DLL_XFORM_DQS5 */
681                         0x00000008, /* EMC_DLL_XFORM_DQS6 */
682                         0x0000000a, /* EMC_DLL_XFORM_DQS7 */
683                         0x00018000, /* EMC_DLL_XFORM_QUSE0 */
684                         0x00018000, /* EMC_DLL_XFORM_QUSE1 */
685                         0x00018000, /* EMC_DLL_XFORM_QUSE2 */
686                         0x00018000, /* EMC_DLL_XFORM_QUSE3 */
687                         0x00018000, /* EMC_DLL_XFORM_QUSE4 */
688                         0x00018000, /* EMC_DLL_XFORM_QUSE5 */
689                         0x00018000, /* EMC_DLL_XFORM_QUSE6 */
690                         0x00018000, /* EMC_DLL_XFORM_QUSE7 */
691                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
692                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
693                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
694                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
695                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
696                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
697                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
698                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
699                         0x0000000c, /* EMC_DLL_XFORM_DQ0 */
700                         0x0000000c, /* EMC_DLL_XFORM_DQ1 */
701                         0x0000000c, /* EMC_DLL_XFORM_DQ2 */
702                         0x0000000c, /* EMC_DLL_XFORM_DQ3 */
703                         0x000002a0, /* EMC_XM2CMDPADCTRL */
704                         0x0600013d, /* EMC_XM2DQSPADCTRL2 */
705                         0x22220000, /* EMC_XM2DQPADCTRL2 */
706                         0x77fff884, /* EMC_XM2CLKPADCTRL */
707                         0x01f1f501, /* EMC_XM2COMPPADCTRL */
708                         0x07077404, /* EMC_XM2VTTGENPADCTRL */
709                         0x54000000, /* EMC_XM2VTTGENPADCTRL2 */
710                         0x080001e8, /* EMC_XM2QUSEPADCTRL */
711                         0x06000021, /* EMC_XM2DQSPADCTRL3 */
712                         0x00000802, /* EMC_CTT_TERM_CTRL */
713                         0x00020000, /* EMC_ZCAL_INTERVAL */
714                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
715                         0x00f8000c, /* EMC_MRS_WAIT_CNT */
716                         0xa0f10202, /* EMC_AUTO_CAL_CONFIG */
717                         0x00000000, /* EMC_CTT */
718                         0x00000000, /* EMC_CTT_DURATION */
719                         0x800028a5, /* EMC_DYN_SELF_REF_CONTROL */
720                         0x0000000a, /* MC_EMEM_ARB_CFG */
721                         0x80000079, /* MC_EMEM_ARB_OUTSTANDING_REQ */
722                         0x00000003, /* MC_EMEM_ARB_TIMING_RCD */
723                         0x00000004, /* MC_EMEM_ARB_TIMING_RP */
724                         0x00000010, /* MC_EMEM_ARB_TIMING_RC */
725                         0x0000000b, /* MC_EMEM_ARB_TIMING_RAS */
726                         0x0000000f, /* MC_EMEM_ARB_TIMING_FAW */
727                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
728                         0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
729                         0x0000000b, /* MC_EMEM_ARB_TIMING_WAP2PRE */
730                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
731                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
732                         0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
733                         0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
734                         0x08040202, /* MC_EMEM_ARB_DA_TURNS */
735                         0x00130b10, /* MC_EMEM_ARB_DA_COVERS */
736                         0x70ea1f11, /* MC_EMEM_ARB_MISC0 */
737                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
738                         0xe8000000, /* EMC_FBIO_SPARE */
739                         0xff00ff49, /* EMC_CFG_RSV */
740                 },
741                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
742                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
743                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
744                 0x80000b71, /* Mode Register 0 */
745                 0x80100002, /* Mode Register 1 */
746                 0x80200018, /* Mode Register 2 */
747                 0x00000000, /* EMC_CFG.DYN_SELF_REF */
748         },
749 };
750
751 int kai_emc_init(void)
752 {
753         tegra_init_emc(kai_emc_tables_h5tc4g,
754                        ARRAY_SIZE(kai_emc_tables_h5tc4g));
755
756         return 0;
757 }