ARM: tegra: clock: Auto-detect PLLP rate in uart init
[linux-2.6.git] / arch / arm / mach-tegra / board-enterprise.c
1 /*
2  * arch/arm/mach-tegra/board-enterprise.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/ctype.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/serial_8250.h>
28 #include <linux/i2c.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/delay.h>
31 #include <linux/i2c-tegra.h>
32 #include <linux/gpio.h>
33 #include <linux/input.h>
34 #include <linux/platform_data/tegra_usb.h>
35 #include <linux/spi/spi.h>
36 #include <linux/tegra_uart.h>
37 #include <linux/fsl_devices.h>
38 #include <linux/i2c/atmel_mxt_ts.h>
39
40 #include <linux/nfc/pn544.h>
41 #include <sound/max98088.h>
42
43 #include <mach/clk.h>
44 #include <mach/iomap.h>
45 #include <mach/irqs.h>
46 #include <mach/pinmux.h>
47 #include <mach/iomap.h>
48 #include <mach/io.h>
49 #include <asm/mach-types.h>
50 #include <asm/mach/arch.h>
51 #include <mach/usb_phy.h>
52 #include <mach/i2s.h>
53 #include <mach/tegra_max98088_pdata.h>
54 #include <mach/thermal.h>
55
56 #include "board.h"
57 #include "clock.h"
58 #include "board-enterprise.h"
59 #include "devices.h"
60 #include "gpio-names.h"
61 #include "fuse.h"
62 #include "pm.h"
63
64 /* All units are in millicelsius */
65 static struct tegra_thermal_data thermal_data = {
66         .temp_throttle = 85000,
67         .temp_shutdown = 90000,
68         .temp_offset = TDIODE_OFFSET, /* temps based on tdiode */
69 #ifdef CONFIG_TEGRA_EDP_LIMITS
70         .edp_offset = TDIODE_OFFSET,  /* edp based on tdiode */
71         .hysteresis_edp = 3000,
72 #endif
73 #ifdef CONFIG_TEGRA_THERMAL_SYSFS
74         .tc1 = 0,
75         .tc2 = 1,
76         .passive_delay = 2000,
77 #else
78         .hysteresis_throttle = 1000,
79 #endif
80 };
81
82 /* !!!TODO: Change for enterprise (Taken from Cardhu) */
83 static struct tegra_utmip_config utmi_phy_config[] = {
84         [0] = {
85                         .hssync_start_delay = 0,
86                         .idle_wait_delay = 17,
87                         .elastic_limit = 16,
88                         .term_range_adj = 6,
89                         .xcvr_setup = 15,
90                         .xcvr_setup_offset = 0,
91                         .xcvr_use_fuses = 1,
92                         .xcvr_lsfslew = 2,
93                         .xcvr_lsrslew = 2,
94         },
95         [1] = {
96                         .hssync_start_delay = 0,
97                         .idle_wait_delay = 17,
98                         .elastic_limit = 16,
99                         .term_range_adj = 6,
100                         .xcvr_setup = 15,
101                         .xcvr_setup_offset = 0,
102                         .xcvr_use_fuses = 1,
103                         .xcvr_lsfslew = 2,
104                         .xcvr_lsrslew = 2,
105         },
106         [2] = {
107                         .hssync_start_delay = 0,
108                         .idle_wait_delay = 17,
109                         .elastic_limit = 16,
110                         .term_range_adj = 6,
111                         .xcvr_setup = 8,
112                         .xcvr_setup_offset = 0,
113                         .xcvr_use_fuses = 1,
114                         .xcvr_lsfslew = 2,
115                         .xcvr_lsrslew = 2,
116         },
117 };
118
119 #ifdef CONFIG_BCM4329_RFKILL
120 static struct resource enterprise_bcm4329_rfkill_resources[] = {
121         {
122                 .name   = "bcm4329_nshutdown_gpio",
123                 .start  = TEGRA_GPIO_PE6,
124                 .end    = TEGRA_GPIO_PE6,
125                 .flags  = IORESOURCE_IO,
126         },
127 };
128
129 static struct platform_device enterprise_bcm4329_rfkill_device = {
130         .name = "bcm4329_rfkill",
131         .id             = -1,
132         .num_resources  = ARRAY_SIZE(enterprise_bcm4329_rfkill_resources),
133         .resource       = enterprise_bcm4329_rfkill_resources,
134 };
135
136 static noinline void __init enterprise_bt_rfkill(void)
137 {
138         platform_device_register(&enterprise_bcm4329_rfkill_device);
139
140         return;
141 }
142 #else
143 static inline void enterprise_bt_rfkill(void) { }
144 #endif
145
146 static void __init enterprise_setup_bluesleep(void)
147 {
148         struct platform_device *pdev = NULL;
149         struct resource *res;
150
151         pdev = platform_device_alloc("bluesleep", 0);
152         if (!pdev) {
153                 pr_err("unable to allocate platform device for bluesleep");
154                 return;
155         }
156
157         res = kzalloc(sizeof(struct resource) * 3, GFP_KERNEL);
158         if (!res) {
159                 pr_err("unable to allocate resource for bluesleep\n");
160                 goto err_free_dev;
161         }
162
163         res[0].name   = "gpio_host_wake";
164         res[0].start  = TEGRA_GPIO_PS2;
165         res[0].end    = TEGRA_GPIO_PS2;
166         res[0].flags  = IORESOURCE_IO;
167
168         res[1].name   = "gpio_ext_wake";
169         res[1].start  = TEGRA_GPIO_PE7;
170         res[1].end    = TEGRA_GPIO_PE7;
171         res[1].flags  = IORESOURCE_IO;
172
173         res[2].name   = "host_wake";
174         res[2].start  = gpio_to_irq(TEGRA_GPIO_PS2);
175         res[2].end    = gpio_to_irq(TEGRA_GPIO_PS2);
176         res[2].flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE ;
177
178         if (platform_device_add_resources(pdev, res, 3)) {
179                 pr_err("unable to add resources to bluesleep device\n");
180                 goto err_free_res;
181         }
182
183         if (platform_device_add(pdev)) {
184                 pr_err("unable to add bluesleep device\n");
185                 goto err_free_res;
186         }
187         tegra_gpio_enable(TEGRA_GPIO_PS2);
188         tegra_gpio_enable(TEGRA_GPIO_PE7);
189
190         return;
191
192 err_free_res:
193         kfree(res);
194 err_free_dev:
195         platform_device_put(pdev);
196         return;
197 }
198
199 static __initdata struct tegra_clk_init_table enterprise_clk_init_table[] = {
200         /* name         parent          rate            enabled */
201         { "pll_m",      NULL,           0,              false},
202         { "hda",        "pll_p",        108000000,      false},
203         { "hda2codec_2x","pll_p",       48000000,       false},
204         { "pwm",        "clk_32k",      32768,          false},
205         { "blink",      "clk_32k",      32768,          true},
206         { "pll_a",      NULL,           564480000,      false},
207         { "pll_a_out0", NULL,           11289600,       false},
208         { "i2s0",       "pll_a_out0",   0,              false},
209         { "i2s1",       "pll_a_out0",   0,              false},
210         { "i2s2",       "pll_a_out0",   0,              false},
211         { "i2s3",       "pll_a_out0",   0,              false},
212         { "spdif_out",  "pll_a_out0",   0,              false},
213         { "d_audio",    "pll_a_out0",   0,              false},
214         { "dam0",       "pll_a_out0",   0,              false},
215         { "dam1",       "pll_a_out0",   0,              false},
216         { "dam2",       "pll_a_out0",   0,              false},
217         { "audio0",     "i2s0_sync",    0,              false},
218         { "audio1",     "i2s1_sync",    0,              false},
219         { "audio2",     "i2s2_sync",    0,              false},
220         { "audio3",     "i2s3_sync",    0,              false},
221         { NULL,         NULL,           0,              0},
222 };
223
224 static struct tegra_i2c_platform_data enterprise_i2c1_platform_data = {
225         .adapter_nr     = 0,
226         .bus_count      = 1,
227         .bus_clk_rate   = { 100000, 0 },
228         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
229         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
230         .arb_recovery = arb_lost_recovery,
231 };
232
233 static struct tegra_i2c_platform_data enterprise_i2c2_platform_data = {
234         .adapter_nr     = 1,
235         .bus_count      = 1,
236         .bus_clk_rate   = { 100000, 0 },
237         .is_clkon_always = true,
238         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
239         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
240         .arb_recovery = arb_lost_recovery,
241 };
242
243 static struct tegra_i2c_platform_data enterprise_i2c3_platform_data = {
244         .adapter_nr     = 2,
245         .bus_count      = 1,
246         .bus_clk_rate   = { 271000, 0 },
247         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
248         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
249         .arb_recovery = arb_lost_recovery,
250 };
251
252 static struct tegra_i2c_platform_data enterprise_i2c4_platform_data = {
253         .adapter_nr     = 3,
254         .bus_count      = 1,
255         .bus_clk_rate   = { 100000, 0 },
256         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
257         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
258         .arb_recovery = arb_lost_recovery,
259 };
260
261 static struct tegra_i2c_platform_data enterprise_i2c5_platform_data = {
262         .adapter_nr     = 4,
263         .bus_count      = 1,
264         .bus_clk_rate   = { 100000, 0 },
265         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
266         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
267         .arb_recovery = arb_lost_recovery,
268 };
269
270 /* Equalizer filter coefs generated from the MAXIM MAX98088
271  * evkit software tool */
272 static struct max98088_eq_cfg max98088_eq_cfg[] = {
273         {
274                 .name = "FLAT",
275                 .rate = 44100,
276                 .band1 = {0x2000, 0xC002, 0x4000, 0x00E9, 0x0000},
277                 .band2 = {0x2000, 0xC00F, 0x4000, 0x02BC, 0x0000},
278                 .band3 = {0x2000, 0xC0A7, 0x4000, 0x0916, 0x0000},
279                 .band4 = {0x2000, 0xC5C2, 0x4000, 0x1A87, 0x0000},
280                 .band5 = {0x2000, 0xF6B0, 0x4000, 0x3F51, 0x0000},
281         },
282         {
283                 .name = "LOWPASS1K",
284                 .rate = 44100,
285                 .band1 = {0x205D, 0xC001, 0x3FEF, 0x002E, 0x02E0},
286                 .band2 = {0x5B9A, 0xC093, 0x3AB2, 0x088B, 0x1981},
287                 .band3 = {0x0D22, 0xC170, 0x26EA, 0x0D79, 0x32CF},
288                 .band4 = {0x0894, 0xC612, 0x01B3, 0x1B34, 0x3FFA},
289                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
290         },
291         { /* BASS=-12dB, TREBLE=+9dB, Fc=5KHz */
292                 .name = "HIBOOST",
293                 .rate = 44100,
294                 .band1 = {0x0815, 0xC001, 0x3AA4, 0x0003, 0x19A2},
295                 .band2 = {0x0815, 0xC103, 0x092F, 0x0B55, 0x3F56},
296                 .band3 = {0x0E0A, 0xC306, 0x1E5C, 0x136E, 0x3856},
297                 .band4 = {0x2459, 0xF665, 0x0CAA, 0x3F46, 0x3EBB},
298                 .band5 = {0x5BBB, 0x3FFF, 0xCEB0, 0x0000, 0x28CA},
299         },
300         { /* BASS=12dB, TREBLE=+12dB */
301                 .name = "LOUD12DB",
302                 .rate = 44100,
303                 .band1 = {0x7FC1, 0xC001, 0x3EE8, 0x0020, 0x0BC7},
304                 .band2 = {0x51E9, 0xC016, 0x3C7C, 0x033F, 0x14E9},
305                 .band3 = {0x1745, 0xC12C, 0x1680, 0x0C2F, 0x3BE9},
306                 .band4 = {0x4536, 0xD7E2, 0x0ED4, 0x31DD, 0x3E42},
307                 .band5 = {0x7FEF, 0x3FFF, 0x0BAB, 0x0000, 0x3EED},
308         },
309         {
310                 .name = "FLAT",
311                 .rate = 16000,
312                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
313                 .band2 = {0x2000, 0xC033, 0x4000, 0x0505, 0x0000},
314                 .band3 = {0x2000, 0xC268, 0x4000, 0x115F, 0x0000},
315                 .band4 = {0x2000, 0xDA62, 0x4000, 0x33C6, 0x0000},
316                 .band5 = {0x2000, 0x4000, 0x4000, 0x0000, 0x0000},
317         },
318         {
319                 .name = "LOWPASS1K",
320                 .rate = 16000,
321                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
322                 .band2 = {0x5BE8, 0xC3E0, 0x3307, 0x15ED, 0x26A0},
323                 .band3 = {0x0F71, 0xD15A, 0x08B3, 0x2BD0, 0x3F67},
324                 .band4 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
325                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
326         },
327         { /* BASS=-12dB, TREBLE=+9dB, Fc=2KHz */
328                 .name = "HIBOOST",
329                 .rate = 16000,
330                 .band1 = {0x0815, 0xC001, 0x3BD2, 0x0009, 0x16BF},
331                 .band2 = {0x080E, 0xC17E, 0xF653, 0x0DBD, 0x3F43},
332                 .band3 = {0x0F80, 0xDF45, 0xEE33, 0x36FE, 0x3D79},
333                 .band4 = {0x590B, 0x3FF0, 0xE882, 0x02BD, 0x3B87},
334                 .band5 = {0x4C87, 0xF3D0, 0x063F, 0x3ED4, 0x3FB1},
335         },
336         { /* BASS=12dB, TREBLE=+12dB */
337                 .name = "LOUD12DB",
338                 .rate = 16000,
339                 .band1 = {0x7FC1, 0xC001, 0x3D07, 0x0058, 0x1344},
340                 .band2 = {0x2DA6, 0xC013, 0x3CF1, 0x02FF, 0x138B},
341                 .band3 = {0x18F1, 0xC08E, 0x244D, 0x0863, 0x34B5},
342                 .band4 = {0x2BE0, 0xF385, 0x04FD, 0x3EC5, 0x3FCE},
343                 .band5 = {0x7FEF, 0x4000, 0x0BAB, 0x0000, 0x3EED},
344         },
345 };
346
347
348 static struct max98088_pdata enterprise_max98088_pdata = {
349         /* equalizer configuration */
350         .eq_cfg = max98088_eq_cfg,
351         .eq_cfgcnt = ARRAY_SIZE(max98088_eq_cfg),
352
353         /* debounce time */
354         .debounce_time_ms = 200,
355
356         /* microphone configuration */
357         .digmic_left_mode = 1,
358         .digmic_right_mode = 1,
359
360         /* receiver output configuration */
361         .receiver_mode = 0,     /* 0 = amplifier, 1 = line output */
362 };
363
364 static struct pn544_i2c_platform_data nfc_pdata = {
365                 .irq_gpio = TEGRA_GPIO_PS4,
366                 .ven_gpio = TEGRA_GPIO_PM6,
367                 .firm_gpio = 0,
368 };
369
370
371 static struct i2c_board_info __initdata max98088_board_info = {
372         I2C_BOARD_INFO("max98088", 0x10),
373         .platform_data = &enterprise_max98088_pdata,
374         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_HP_DET),
375 };
376
377 static struct i2c_board_info __initdata nfc_board_info = {
378         I2C_BOARD_INFO("pn544", 0x28),
379         .platform_data = &nfc_pdata,
380         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PS4),
381 };
382
383 static void enterprise_i2c_init(void)
384 {
385         tegra_i2c_device1.dev.platform_data = &enterprise_i2c1_platform_data;
386         tegra_i2c_device2.dev.platform_data = &enterprise_i2c2_platform_data;
387         tegra_i2c_device3.dev.platform_data = &enterprise_i2c3_platform_data;
388         tegra_i2c_device4.dev.platform_data = &enterprise_i2c4_platform_data;
389         tegra_i2c_device5.dev.platform_data = &enterprise_i2c5_platform_data;
390
391         platform_device_register(&tegra_i2c_device5);
392         platform_device_register(&tegra_i2c_device4);
393         platform_device_register(&tegra_i2c_device3);
394         platform_device_register(&tegra_i2c_device2);
395         platform_device_register(&tegra_i2c_device1);
396
397         i2c_register_board_info(0, &max98088_board_info, 1);
398         i2c_register_board_info(0, &nfc_board_info, 1);
399 }
400
401 static struct platform_device *enterprise_uart_devices[] __initdata = {
402         &tegra_uarta_device,
403         &tegra_uartb_device,
404         &tegra_uartc_device,
405         &tegra_uartd_device,
406         &tegra_uarte_device,
407 };
408
409 static struct uart_clk_parent uart_parent_clk[] = {
410         [0] = {.name = "clk_m"},
411         [1] = {.name = "pll_p"},
412 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
413         [2] = {.name = "pll_m"},
414 #endif
415 };
416 static struct tegra_uart_platform_data enterprise_uart_pdata;
417 static struct tegra_uart_platform_data enterprise_loopback_uart_pdata;
418
419 static void __init uart_debug_init(void)
420 {
421         unsigned long rate;
422         struct clk *c;
423
424         tegra_init_debug_uart_rate();
425
426         /* UARTD is the debug port. */
427         pr_info("Selecting UARTD as the debug console\n");
428         enterprise_uart_devices[3] = &debug_uartd_device;
429         debug_uart_port_base = ((struct plat_serial8250_port *)(
430                         debug_uartd_device.dev.platform_data))->mapbase;
431         debug_uart_clk = clk_get_sys("serial8250.0", "uartd");
432
433         /* Clock enable for the debug channel */
434         if (!IS_ERR_OR_NULL(debug_uart_clk)) {
435                 rate = ((struct plat_serial8250_port *)(
436                         debug_uartd_device.dev.platform_data))->uartclk;
437                 pr_info("The debug console clock name is %s\n",
438                                                 debug_uart_clk->name);
439                 c = tegra_get_clock_by_name("pll_p");
440                 if (IS_ERR_OR_NULL(c))
441                         pr_err("Not getting the parent clock pll_p\n");
442                 else
443                         clk_set_parent(debug_uart_clk, c);
444
445                 clk_enable(debug_uart_clk);
446                 clk_set_rate(debug_uart_clk, rate);
447         } else {
448                 pr_err("Not getting the clock %s for debug console\n",
449                                 debug_uart_clk->name);
450         }
451 }
452
453 static void __init enterprise_uart_init(void)
454 {
455         int i;
456         struct clk *c;
457
458         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
459                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
460                 if (IS_ERR_OR_NULL(c)) {
461                         pr_err("Not able to get the clock for %s\n",
462                                                 uart_parent_clk[i].name);
463                         continue;
464                 }
465                 uart_parent_clk[i].parent_clk = c;
466                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
467         }
468         enterprise_uart_pdata.parent_clk_list = uart_parent_clk;
469         enterprise_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
470         enterprise_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
471         enterprise_loopback_uart_pdata.parent_clk_count =
472                                                 ARRAY_SIZE(uart_parent_clk);
473         enterprise_loopback_uart_pdata.is_loopback = true;
474         tegra_uarta_device.dev.platform_data = &enterprise_uart_pdata;
475         tegra_uartb_device.dev.platform_data = &enterprise_uart_pdata;
476         tegra_uartc_device.dev.platform_data = &enterprise_uart_pdata;
477         tegra_uartd_device.dev.platform_data = &enterprise_uart_pdata;
478         /* UARTE is used for loopback test purpose */
479         tegra_uarte_device.dev.platform_data = &enterprise_loopback_uart_pdata;
480
481         /* Register low speed only if it is selected */
482         if (!is_tegra_debug_uartport_hs())
483                 uart_debug_init();
484
485         platform_add_devices(enterprise_uart_devices,
486                                 ARRAY_SIZE(enterprise_uart_devices));
487 }
488
489
490
491 static struct resource tegra_rtc_resources[] = {
492         [0] = {
493                 .start = TEGRA_RTC_BASE,
494                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
495                 .flags = IORESOURCE_MEM,
496         },
497         [1] = {
498                 .start = INT_RTC,
499                 .end = INT_RTC,
500                 .flags = IORESOURCE_IRQ,
501         },
502 };
503
504 static struct platform_device tegra_rtc_device = {
505         .name = "tegra_rtc",
506         .id   = -1,
507         .resource = tegra_rtc_resources,
508         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
509 };
510
511 static struct platform_device tegra_camera = {
512         .name = "tegra_camera",
513         .id = -1,
514 };
515
516 static struct tegra_max98088_platform_data enterprise_audio_pdata = {
517         .gpio_spkr_en           = -1,
518         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
519         .gpio_hp_mute           = -1,
520         .gpio_int_mic_en        = -1,
521         .gpio_ext_mic_en        = -1,
522         .audio_port_id          = {
523                 [HIFI_CODEC] = 0,
524                 [BASEBAND] = 2,
525                 [BT_SCO] = 3,
526         },
527         .baseband_param         = {
528                 .rate = 8000,
529                 .channels = 1,
530         },
531 };
532
533 static struct platform_device enterprise_audio_device = {
534         .name   = "tegra-snd-max98088",
535         .id     = 0,
536         .dev    = {
537                 .platform_data  = &enterprise_audio_pdata,
538         },
539 };
540
541 static struct platform_device *enterprise_devices[] __initdata = {
542         &tegra_pmu_device,
543         &tegra_rtc_device,
544         &tegra_udc_device,
545 #if defined(CONFIG_TEGRA_IOVMM_SMMU) || defined(CONFIG_TEGRA_IOMMU_SMMU)
546         &tegra_smmu_device,
547 #endif
548         &tegra_wdt_device,
549 #if defined(CONFIG_TEGRA_AVP)
550         &tegra_avp_device,
551 #endif
552         &tegra_camera,
553         &tegra_spi_device4,
554         &tegra_hda_device,
555 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
556         &tegra_se_device,
557 #endif
558 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
559         &tegra_aes_device,
560 #endif
561 };
562
563 #define MXT_CONFIG_CRC 0x62F903
564 /*
565  * Config converted from memory-mapped cfg-file with
566  * following version information:
567  *
568  *
569  *
570  *      FAMILY_ID=128
571  *      VARIANT=1
572  *      VERSION=32
573  *      BUILD=170
574  *      VENDOR_ID=255
575  *      PRODUCT_ID=TBD
576  *      CHECKSUM=0xC189B6
577  *
578  *
579  */
580
581 static const u8 config[] = {
582         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
583         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x05, 0x01, 0x00,
584         0x00, 0x1E, 0x0A, 0x8B, 0x00, 0x00, 0x13, 0x0B,
585         0x00, 0x10, 0x32, 0x03, 0x03, 0x00, 0x03, 0x01,
586         0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xBF, 0x03, 0x1B,
587         0x02, 0x00, 0x00, 0x37, 0x37, 0x00, 0x00, 0x00,
588         0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
589         0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
590         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
591         0x00, 0x00, 0x00, 0xA9, 0x7F, 0x9A, 0x0E, 0x00,
592         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
593         0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00,
594         0x00, 0x00, 0x03, 0x23, 0x00, 0x00, 0x00, 0x0A,
595         0x0F, 0x14, 0x19, 0x03, 0x00, 0x00, 0x00, 0x00,
596         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
597         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
598         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
599         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
600         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
601         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
602         0x00, 0x00, 0x00, 0x01, 0x00, 0x03, 0x08, 0x10,
603         0x00
604 };
605
606 static struct mxt_platform_data atmel_mxt_info = {
607         .x_line         = 19,
608         .y_line         = 11,
609         .x_size         = 960,
610         .y_size         = 540,
611         .blen           = 0x10,
612         .threshold      = 0x32,
613         .voltage        = 3300000,              /* 3.3V */
614         .orient         = 3,
615         .config         = config,
616         .config_length  = 168,
617         .config_crc     = MXT_CONFIG_CRC,
618         .irqflags       = IRQF_TRIGGER_FALLING,
619 /*      .read_chg       = &read_chg, */
620         .read_chg       = NULL,
621 };
622
623 static struct i2c_board_info __initdata atmel_i2c_info[] = {
624         {
625                 I2C_BOARD_INFO("atmel_mxt_ts", MXT224_I2C_ADDR1),
626                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PH6),
627                 .platform_data = &atmel_mxt_info,
628         }
629 };
630
631 static int __init enterprise_touch_init(void)
632 {
633         tegra_gpio_enable(TEGRA_GPIO_PH6);
634         tegra_gpio_enable(TEGRA_GPIO_PF5);
635
636         gpio_request(TEGRA_GPIO_PH6, "atmel-irq");
637         gpio_direction_input(TEGRA_GPIO_PH6);
638
639         gpio_request(TEGRA_GPIO_PF5, "atmel-reset");
640         gpio_direction_output(TEGRA_GPIO_PF5, 0);
641         msleep(1);
642         gpio_set_value(TEGRA_GPIO_PF5, 1);
643         msleep(100);
644
645         i2c_register_board_info(1, atmel_i2c_info, 1);
646
647         return 0;
648 }
649
650 static struct usb_phy_plat_data tegra_usb_phy_pdata[] = {
651         [0] = {
652                         .instance = 0,
653                         .vbus_gpio = -1,
654                         .vbus_reg_supply = "usb_vbus",
655                         .vbus_irq = ENT_TPS80031_IRQ_BASE +
656                                                         TPS80031_INT_VBUS_DET,
657         },
658         [1] = {
659                         .instance = 1,
660                         .vbus_gpio = -1,
661         },
662         [2] = {
663                         .instance = 2,
664                         .vbus_gpio = -1,
665         },
666 };
667
668 static struct tegra_ehci_platform_data tegra_ehci_pdata[] = {
669         [0] = {
670                         .phy_config = &utmi_phy_config[0],
671                         .operating_mode = TEGRA_USB_HOST,
672                         .power_down_on_bus_suspend = 1,
673                         .default_enable = false,
674         },
675         [1] = {
676                         .phy_config = &utmi_phy_config[1],
677                         .operating_mode = TEGRA_USB_HOST,
678                         .power_down_on_bus_suspend = 1,
679                         .default_enable = false,
680         },
681         [2] = {
682                         .phy_config = &utmi_phy_config[2],
683                         .operating_mode = TEGRA_USB_HOST,
684                         .power_down_on_bus_suspend = 1,
685                         .default_enable = false,
686         },
687 };
688
689 static struct tegra_otg_platform_data tegra_otg_pdata = {
690         .ehci_device = &tegra_ehci1_device,
691         .ehci_pdata = &tegra_ehci_pdata[0],
692 };
693
694 static void enterprise_usb_init(void)
695 {
696         struct  fsl_usb2_platform_data *udc_pdata;
697
698         tegra_usb_phy_init(tegra_usb_phy_pdata, ARRAY_SIZE(tegra_usb_phy_pdata));
699
700         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
701         platform_device_register(&tegra_otg_device);
702
703         udc_pdata = tegra_udc_device.dev.platform_data;
704 }
705
706 static struct platform_device *enterprise_audio_devices[] __initdata = {
707         &tegra_ahub_device,
708         &tegra_dam_device0,
709         &tegra_dam_device1,
710         &tegra_dam_device2,
711         &tegra_i2s_device2,
712         &tegra_i2s_device3,
713         &tegra_spdif_device,
714         &spdif_dit_device,
715         &bluetooth_dit_device,
716         &baseband_dit_device,
717         &tegra_pcm_device,
718         &enterprise_audio_device,
719 };
720
721 static void enterprise_audio_init(void)
722 {
723         struct board_info board_info;
724
725         tegra_get_board_info(&board_info);
726         if (board_info.board_id == BOARD_E1197) {
727                 platform_device_register(&tegra_i2s_device1);
728                 enterprise_audio_pdata.audio_port_id[HIFI_CODEC] = 1;
729         } else
730                 platform_device_register(&tegra_i2s_device0);
731
732         platform_add_devices(enterprise_audio_devices,
733                         ARRAY_SIZE(enterprise_audio_devices));
734 }
735
736 static void enterprise_gps_init(void)
737 {
738         tegra_gpio_enable(TEGRA_GPIO_PE4);
739         tegra_gpio_enable(TEGRA_GPIO_PE5);
740 }
741
742 static void enterprise_baseband_init(void)
743 {
744         int modem_id = tegra_get_modem_id();
745
746         switch (modem_id) {
747         case 1: /* PH450 ULPI */
748                 enterprise_modem_init();
749                 break;
750         case 2: /* 6260 HSIC */
751                 break;
752         }
753 }
754
755 static void enterprise_nfc_init(void)
756 {
757         tegra_gpio_enable(TEGRA_GPIO_PS4);
758         tegra_gpio_enable(TEGRA_GPIO_PM6);
759 }
760
761 static void __init tegra_enterprise_init(void)
762 {
763         tegra_thermal_init(&thermal_data);
764         tegra_clk_init_from_table(enterprise_clk_init_table);
765         enterprise_pinmux_init();
766         enterprise_i2c_init();
767         enterprise_uart_init();
768         enterprise_usb_init();
769         enterprise_tsensor_init();
770         platform_add_devices(enterprise_devices, ARRAY_SIZE(enterprise_devices));
771         enterprise_regulator_init();
772         enterprise_sdhci_init();
773 #ifdef CONFIG_TEGRA_EDP_LIMITS
774         enterprise_edp_init();
775 #endif
776         enterprise_kbc_init();
777         enterprise_touch_init();
778         enterprise_audio_init();
779         enterprise_gps_init();
780         enterprise_baseband_init();
781         enterprise_panel_init();
782         enterprise_bt_rfkill();
783         enterprise_setup_bluesleep();
784         enterprise_emc_init();
785         enterprise_sensors_init();
786         enterprise_suspend_init();
787         enterprise_bpc_mgmt_init();
788         tegra_release_bootloader_fb();
789         enterprise_nfc_init();
790 }
791
792 static void __init tegra_enterprise_reserve(void)
793 {
794 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
795         tegra_reserve(0, SZ_4M, SZ_8M);
796 #else
797         tegra_reserve(SZ_128M, SZ_4M, SZ_8M);
798 #endif
799 }
800
801 MACHINE_START(TEGRA_ENTERPRISE, "tegra_enterprise")
802         .boot_params    = 0x80000100,
803         .map_io         = tegra_map_common_io,
804         .reserve        = tegra_enterprise_reserve,
805         .init_early     = tegra_init_early,
806         .init_irq       = tegra_init_irq,
807         .timer          = &tegra_timer,
808         .init_machine   = tegra_enterprise_init,
809 MACHINE_END