arm: tegra: sd: enable sd dpd
[linux-2.6.git] / arch / arm / mach-tegra / board-enterprise-memory.c
1 /*
2  * Copyright (C) 2011 NVIDIA, Inc.
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope that it will be useful,
9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11  * GNU General Public License for more details.
12  *
13  * You should have received a copy of the GNU General Public License
14  * along with this program; if not, write to the Free Software
15  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
16  * 02111-1307, USA
17  */
18
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21
22 #include "board-enterprise.h"
23 #include "tegra3_emc.h"
24 #include "board.h"
25
26
27 static const struct tegra_emc_table enterprise_emc_tables_kmmll0_a02[] = {
28         {
29                 0x32,       /* Rev 3.2 */
30                 12750,      /* SDRAM frequency */
31                 {
32                         0x00000000, /* EMC_RC */
33                         0x00000001, /* EMC_RFC */
34                         0x00000002, /* EMC_RAS */
35                         0x00000002, /* EMC_RP */
36                         0x00000004, /* EMC_R2W */
37                         0x00000004, /* EMC_W2R */
38                         0x00000001, /* EMC_R2P */
39                         0x00000005, /* EMC_W2P */
40                         0x00000002, /* EMC_RD_RCD */
41                         0x00000002, /* EMC_WR_RCD */
42                         0x00000001, /* EMC_RRD */
43                         0x00000001, /* EMC_REXT */
44                         0x00000000, /* EMC_WEXT */
45                         0x00000001, /* EMC_WDV */
46                         0x00000003, /* EMC_QUSE */
47                         0x00000001, /* EMC_QRST */
48                         0x00000009, /* EMC_QSAFE */
49                         0x0000000a, /* EMC_RDV */
50                         0x0000002f, /* EMC_REFRESH */
51                         0x00000000, /* EMC_BURST_REFRESH_NUM */
52                         0x0000000b, /* EMC_PRE_REFRESH_REQ_CNT */
53                         0x00000001, /* EMC_PDEX2WR */
54                         0x00000001, /* EMC_PDEX2RD */
55                         0x00000002, /* EMC_PCHG2PDEN */
56                         0x00000000, /* EMC_ACT2PDEN */
57                         0x00000001, /* EMC_AR2PDEN */
58                         0x00000007, /* EMC_RW2PDEN */
59                         0x00000002, /* EMC_TXSR */
60                         0x00000002, /* EMC_TXSRDLL */
61                         0x00000003, /* EMC_TCKE */
62                         0x00000008, /* EMC_TFAW */
63                         0x00000004, /* EMC_TRPAB */
64                         0x00000001, /* EMC_TCLKSTABLE */
65                         0x00000002, /* EMC_TCLKSTOP */
66                         0x00000036, /* EMC_TREFBW */
67                         0x00000004, /* EMC_QUSE_EXTRA */
68                         0x00000004, /* EMC_FBIO_CFG6 */
69                         0x00000000, /* EMC_ODT_WRITE */
70                         0x00000000, /* EMC_ODT_READ */
71                         0x00004282, /* EMC_FBIO_CFG5 */
72                         0x007800a4, /* EMC_CFG_DIG_DLL */
73                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
74                         0x000fc000, /* EMC_DLL_XFORM_DQS0 */
75                         0x000fc000, /* EMC_DLL_XFORM_DQS1 */
76                         0x000fc000, /* EMC_DLL_XFORM_DQS2 */
77                         0x000fc000, /* EMC_DLL_XFORM_DQS3 */
78                         0x000fc000, /* EMC_DLL_XFORM_DQS4 */
79                         0x000fc000, /* EMC_DLL_XFORM_DQS5 */
80                         0x000fc000, /* EMC_DLL_XFORM_DQS6 */
81                         0x000fc000, /* EMC_DLL_XFORM_DQS7 */
82                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
83                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
84                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
85                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
86                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
87                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
88                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
89                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
90                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
91                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
92                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
93                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
94                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
95                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
96                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
97                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
98                         0x000fc000, /* EMC_DLL_XFORM_DQ0 */
99                         0x000fc000, /* EMC_DLL_XFORM_DQ1 */
100                         0x000fc000, /* EMC_DLL_XFORM_DQ2 */
101                         0x000fc000, /* EMC_DLL_XFORM_DQ3 */
102                         0x00100220, /* EMC_XM2CMDPADCTRL */
103                         0x0800201c, /* EMC_XM2DQSPADCTRL2 */
104                         0x00000000, /* EMC_XM2DQPADCTRL2 */
105                         0x77ffc004, /* EMC_XM2CLKPADCTRL */
106                         0x01f1f008, /* EMC_XM2COMPPADCTRL */
107                         0x00000000, /* EMC_XM2VTTGENPADCTRL */
108                         0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
109                         0x08000068, /* EMC_XM2QUSEPADCTRL */
110                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
111                         0x00000802, /* EMC_CTT_TERM_CTRL */
112                         0x00064000, /* EMC_ZCAL_INTERVAL */
113                         0x00000009, /* EMC_ZCAL_WAIT_CNT */
114                         0x00090009, /* EMC_MRS_WAIT_CNT */
115                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
116                         0x00000000, /* EMC_CTT */
117                         0x00000000, /* EMC_CTT_DURATION */
118                         0x80000164, /* EMC_DYN_SELF_REF_CONTROL */
119                         0x00050001, /* MC_EMEM_ARB_CFG */
120                         0xc0000008, /* MC_EMEM_ARB_OUTSTANDING_REQ */
121                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
122                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
123                         0x00000002, /* MC_EMEM_ARB_TIMING_RC */
124                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
125                         0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
126                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
127                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
128                         0x00000004, /* MC_EMEM_ARB_TIMING_WAP2PRE */
129                         0x00000001, /* MC_EMEM_ARB_TIMING_R2R */
130                         0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
131                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
132                         0x00000002, /* MC_EMEM_ARB_TIMING_W2R */
133                         0x02020001, /* MC_EMEM_ARB_DA_TURNS */
134                         0x00060402, /* MC_EMEM_ARB_DA_COVERS */
135                         0x77230303, /* MC_EMEM_ARB_MISC0 */
136                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
137                         0x50000000, /* EMC_FBIO_SPARE */
138                         0xff00ff00, /* EMC_CFG_RSV */
139                 },
140                 0x00000009, /* EMC_ZCAL_WAIT_CNT after clock change */
141                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
142                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
143                 0x00000000, /* Mode Register 0 */
144                 0x00010022, /* Mode Register 1 */
145                 0x00020001, /* Mode Register 2 */
146                 0x00000001, /* EMC_CFG.DYN_SELF_REF */
147         },
148         {
149                 0x32,       /* Rev 3.2 */
150                 25500,      /* SDRAM frequency */
151                 {
152                         0x00000001, /* EMC_RC */
153                         0x00000003, /* EMC_RFC */
154                         0x00000002, /* EMC_RAS */
155                         0x00000002, /* EMC_RP */
156                         0x00000004, /* EMC_R2W */
157                         0x00000004, /* EMC_W2R */
158                         0x00000001, /* EMC_R2P */
159                         0x00000005, /* EMC_W2P */
160                         0x00000002, /* EMC_RD_RCD */
161                         0x00000002, /* EMC_WR_RCD */
162                         0x00000001, /* EMC_RRD */
163                         0x00000001, /* EMC_REXT */
164                         0x00000000, /* EMC_WEXT */
165                         0x00000001, /* EMC_WDV */
166                         0x00000003, /* EMC_QUSE */
167                         0x00000001, /* EMC_QRST */
168                         0x00000009, /* EMC_QSAFE */
169                         0x0000000a, /* EMC_RDV */
170                         0x0000005e, /* EMC_REFRESH */
171                         0x00000000, /* EMC_BURST_REFRESH_NUM */
172                         0x00000017, /* EMC_PRE_REFRESH_REQ_CNT */
173                         0x00000001, /* EMC_PDEX2WR */
174                         0x00000001, /* EMC_PDEX2RD */
175                         0x00000002, /* EMC_PCHG2PDEN */
176                         0x00000000, /* EMC_ACT2PDEN */
177                         0x00000001, /* EMC_AR2PDEN */
178                         0x00000007, /* EMC_RW2PDEN */
179                         0x00000004, /* EMC_TXSR */
180                         0x00000004, /* EMC_TXSRDLL */
181                         0x00000003, /* EMC_TCKE */
182                         0x00000008, /* EMC_TFAW */
183                         0x00000004, /* EMC_TRPAB */
184                         0x00000004, /* EMC_TCLKSTABLE */
185                         0x00000002, /* EMC_TCLKSTOP */
186                         0x00000068, /* EMC_TREFBW */
187                         0x00000004, /* EMC_QUSE_EXTRA */
188                         0x00000004, /* EMC_FBIO_CFG6 */
189                         0x00000000, /* EMC_ODT_WRITE */
190                         0x00000000, /* EMC_ODT_READ */
191                         0x00004282, /* EMC_FBIO_CFG5 */
192                         0x007800a4, /* EMC_CFG_DIG_DLL */
193                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
194                         0x00090000, /* EMC_DLL_XFORM_DQS0 */
195                         0x00090000, /* EMC_DLL_XFORM_DQS1 */
196                         0x00090000, /* EMC_DLL_XFORM_DQS2 */
197                         0x00090000, /* EMC_DLL_XFORM_DQS3 */
198                         0x00000010, /* EMC_DLL_XFORM_DQS4 */
199                         0x00000010, /* EMC_DLL_XFORM_DQS5 */
200                         0x00000010, /* EMC_DLL_XFORM_DQS6 */
201                         0x00000010, /* EMC_DLL_XFORM_DQS7 */
202                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
203                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
204                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
205                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
206                         0x00000008, /* EMC_DLL_XFORM_QUSE4 */
207                         0x00000008, /* EMC_DLL_XFORM_QUSE5 */
208                         0x00000008, /* EMC_DLL_XFORM_QUSE6 */
209                         0x00000008, /* EMC_DLL_XFORM_QUSE7 */
210                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
211                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
212                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
213                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
214                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
215                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
216                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
217                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
218                         0x00088000, /* EMC_DLL_XFORM_DQ0 */
219                         0x00088000, /* EMC_DLL_XFORM_DQ1 */
220                         0x00088000, /* EMC_DLL_XFORM_DQ2 */
221                         0x00088000, /* EMC_DLL_XFORM_DQ3 */
222                         0x00100220, /* EMC_XM2CMDPADCTRL */
223                         0x0800201c, /* EMC_XM2DQSPADCTRL2 */
224                         0x00000000, /* EMC_XM2DQPADCTRL2 */
225                         0x77ffc004, /* EMC_XM2CLKPADCTRL */
226                         0x01f1f008, /* EMC_XM2COMPPADCTRL */
227                         0x00000000, /* EMC_XM2VTTGENPADCTRL */
228                         0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
229                         0x08000068, /* EMC_XM2QUSEPADCTRL */
230                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
231                         0x00000802, /* EMC_CTT_TERM_CTRL */
232                         0x00064000, /* EMC_ZCAL_INTERVAL */
233                         0x0000000a, /* EMC_ZCAL_WAIT_CNT */
234                         0x00090009, /* EMC_MRS_WAIT_CNT */
235                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
236                         0x00000000, /* EMC_CTT */
237                         0x00000000, /* EMC_CTT_DURATION */
238                         0x800001c2, /* EMC_DYN_SELF_REF_CONTROL */
239                         0x00020001, /* MC_EMEM_ARB_CFG */
240                         0xc0000008, /* MC_EMEM_ARB_OUTSTANDING_REQ */
241                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
242                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
243                         0x00000002, /* MC_EMEM_ARB_TIMING_RC */
244                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
245                         0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
246                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
247                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
248                         0x00000004, /* MC_EMEM_ARB_TIMING_WAP2PRE */
249                         0x00000001, /* MC_EMEM_ARB_TIMING_R2R */
250                         0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
251                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
252                         0x00000002, /* MC_EMEM_ARB_TIMING_W2R */
253                         0x02020001, /* MC_EMEM_ARB_DA_TURNS */
254                         0x00060402, /* MC_EMEM_ARB_DA_COVERS */
255                         0x74030303, /* MC_EMEM_ARB_MISC0 */
256                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
257                         0x50000000, /* EMC_FBIO_SPARE */
258                         0xff00ff00, /* EMC_CFG_RSV */
259                 },
260                 0x00000009, /* EMC_ZCAL_WAIT_CNT after clock change */
261                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
262                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
263                 0x00000000, /* Mode Register 0 */
264                 0x00010022, /* Mode Register 1 */
265                 0x00020001, /* Mode Register 2 */
266                 0x00000001, /* EMC_CFG.DYN_SELF_REF */
267         },
268         {
269                 0x32,       /* Rev 3.2 */
270                 51000,      /* SDRAM frequency */
271                 {
272                         0x00000003, /* EMC_RC */
273                         0x00000006, /* EMC_RFC */
274                         0x00000002, /* EMC_RAS */
275                         0x00000002, /* EMC_RP */
276                         0x00000004, /* EMC_R2W */
277                         0x00000004, /* EMC_W2R */
278                         0x00000001, /* EMC_R2P */
279                         0x00000005, /* EMC_W2P */
280                         0x00000002, /* EMC_RD_RCD */
281                         0x00000002, /* EMC_WR_RCD */
282                         0x00000001, /* EMC_RRD */
283                         0x00000001, /* EMC_REXT */
284                         0x00000000, /* EMC_WEXT */
285                         0x00000001, /* EMC_WDV */
286                         0x00000003, /* EMC_QUSE */
287                         0x00000001, /* EMC_QRST */
288                         0x00000009, /* EMC_QSAFE */
289                         0x0000000a, /* EMC_RDV */
290                         0x000000c0, /* EMC_REFRESH */
291                         0x00000000, /* EMC_BURST_REFRESH_NUM */
292                         0x00000030, /* EMC_PRE_REFRESH_REQ_CNT */
293                         0x00000001, /* EMC_PDEX2WR */
294                         0x00000001, /* EMC_PDEX2RD */
295                         0x00000002, /* EMC_PCHG2PDEN */
296                         0x00000000, /* EMC_ACT2PDEN */
297                         0x00000001, /* EMC_AR2PDEN */
298                         0x00000007, /* EMC_RW2PDEN */
299                         0x00000008, /* EMC_TXSR */
300                         0x00000008, /* EMC_TXSRDLL */
301                         0x00000003, /* EMC_TCKE */
302                         0x00000008, /* EMC_TFAW */
303                         0x00000004, /* EMC_TRPAB */
304                         0x00000004, /* EMC_TCLKSTABLE */
305                         0x00000002, /* EMC_TCLKSTOP */
306                         0x000000d5, /* EMC_TREFBW */
307                         0x00000004, /* EMC_QUSE_EXTRA */
308                         0x00000004, /* EMC_FBIO_CFG6 */
309                         0x00000000, /* EMC_ODT_WRITE */
310                         0x00000000, /* EMC_ODT_READ */
311                         0x00004282, /* EMC_FBIO_CFG5 */
312                         0x007800a4, /* EMC_CFG_DIG_DLL */
313                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
314                         0x00090000, /* EMC_DLL_XFORM_DQS0 */
315                         0x00090000, /* EMC_DLL_XFORM_DQS1 */
316                         0x00090000, /* EMC_DLL_XFORM_DQS2 */
317                         0x00090000, /* EMC_DLL_XFORM_DQS3 */
318                         0x00000010, /* EMC_DLL_XFORM_DQS4 */
319                         0x00000010, /* EMC_DLL_XFORM_DQS5 */
320                         0x00000010, /* EMC_DLL_XFORM_DQS6 */
321                         0x00000010, /* EMC_DLL_XFORM_DQS7 */
322                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
323                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
324                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
325                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
326                         0x00000018, /* EMC_DLL_XFORM_QUSE4 */
327                         0x00000018, /* EMC_DLL_XFORM_QUSE5 */
328                         0x00000018, /* EMC_DLL_XFORM_QUSE6 */
329                         0x00000018, /* EMC_DLL_XFORM_QUSE7 */
330                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
331                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
332                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
333                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
334                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
335                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
336                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
337                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
338                         0x00088000, /* EMC_DLL_XFORM_DQ0 */
339                         0x00088000, /* EMC_DLL_XFORM_DQ1 */
340                         0x00088000, /* EMC_DLL_XFORM_DQ2 */
341                         0x00088000, /* EMC_DLL_XFORM_DQ3 */
342                         0x00100220, /* EMC_XM2CMDPADCTRL */
343                         0x0800201c, /* EMC_XM2DQSPADCTRL2 */
344                         0x00000000, /* EMC_XM2DQPADCTRL2 */
345                         0x77ffc004, /* EMC_XM2CLKPADCTRL */
346                         0x01f1f008, /* EMC_XM2COMPPADCTRL */
347                         0x00000000, /* EMC_XM2VTTGENPADCTRL */
348                         0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
349                         0x08000068, /* EMC_XM2QUSEPADCTRL */
350                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
351                         0x00000802, /* EMC_CTT_TERM_CTRL */
352                         0x00064000, /* EMC_ZCAL_INTERVAL */
353                         0x00000013, /* EMC_ZCAL_WAIT_CNT */
354                         0x00090009, /* EMC_MRS_WAIT_CNT */
355                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
356                         0x00000000, /* EMC_CTT */
357                         0x00000000, /* EMC_CTT_DURATION */
358                         0x80000287, /* EMC_DYN_SELF_REF_CONTROL */
359                         0x00010001, /* MC_EMEM_ARB_CFG */
360                         0xc000000a, /* MC_EMEM_ARB_OUTSTANDING_REQ */
361                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
362                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
363                         0x00000002, /* MC_EMEM_ARB_TIMING_RC */
364                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
365                         0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
366                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
367                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
368                         0x00000004, /* MC_EMEM_ARB_TIMING_WAP2PRE */
369                         0x00000001, /* MC_EMEM_ARB_TIMING_R2R */
370                         0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
371                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
372                         0x00000002, /* MC_EMEM_ARB_TIMING_W2R */
373                         0x02020001, /* MC_EMEM_ARB_DA_TURNS */
374                         0x00060402, /* MC_EMEM_ARB_DA_COVERS */
375                         0x72c30303, /* MC_EMEM_ARB_MISC0 */
376                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
377                         0x50000000, /* EMC_FBIO_SPARE */
378                         0xff00ff00, /* EMC_CFG_RSV */
379                 },
380                 0x00000009, /* EMC_ZCAL_WAIT_CNT after clock change */
381                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
382                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
383                 0x00000000, /* Mode Register 0 */
384                 0x00010022, /* Mode Register 1 */
385                 0x00020001, /* Mode Register 2 */
386                 0x00000001, /* EMC_CFG.DYN_SELF_REF */
387         },
388         {
389                 0x32,       /* Rev 3.2 */
390                 102000,     /* SDRAM frequency */
391                 {
392                         0x00000006, /* EMC_RC */
393                         0x0000000d, /* EMC_RFC */
394                         0x00000004, /* EMC_RAS */
395                         0x00000002, /* EMC_RP */
396                         0x00000004, /* EMC_R2W */
397                         0x00000004, /* EMC_W2R */
398                         0x00000001, /* EMC_R2P */
399                         0x00000005, /* EMC_W2P */
400                         0x00000002, /* EMC_RD_RCD */
401                         0x00000002, /* EMC_WR_RCD */
402                         0x00000001, /* EMC_RRD */
403                         0x00000001, /* EMC_REXT */
404                         0x00000000, /* EMC_WEXT */
405                         0x00000001, /* EMC_WDV */
406                         0x00000003, /* EMC_QUSE */
407                         0x00000001, /* EMC_QRST */
408                         0x00000009, /* EMC_QSAFE */
409                         0x0000000a, /* EMC_RDV */
410                         0x00000181, /* EMC_REFRESH */
411                         0x00000000, /* EMC_BURST_REFRESH_NUM */
412                         0x00000060, /* EMC_PRE_REFRESH_REQ_CNT */
413                         0x00000001, /* EMC_PDEX2WR */
414                         0x00000001, /* EMC_PDEX2RD */
415                         0x00000002, /* EMC_PCHG2PDEN */
416                         0x00000000, /* EMC_ACT2PDEN */
417                         0x00000001, /* EMC_AR2PDEN */
418                         0x00000007, /* EMC_RW2PDEN */
419                         0x0000000f, /* EMC_TXSR */
420                         0x0000000f, /* EMC_TXSRDLL */
421                         0x00000003, /* EMC_TCKE */
422                         0x00000008, /* EMC_TFAW */
423                         0x00000004, /* EMC_TRPAB */
424                         0x00000004, /* EMC_TCLKSTABLE */
425                         0x00000002, /* EMC_TCLKSTOP */
426                         0x000001a9, /* EMC_TREFBW */
427                         0x00000004, /* EMC_QUSE_EXTRA */
428                         0x00000006, /* EMC_FBIO_CFG6 */
429                         0x00000000, /* EMC_ODT_WRITE */
430                         0x00000000, /* EMC_ODT_READ */
431                         0x00004282, /* EMC_FBIO_CFG5 */
432                         0x007800a4, /* EMC_CFG_DIG_DLL */
433                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
434                         0x00090000, /* EMC_DLL_XFORM_DQS0 */
435                         0x00090000, /* EMC_DLL_XFORM_DQS1 */
436                         0x00090000, /* EMC_DLL_XFORM_DQS2 */
437                         0x00090000, /* EMC_DLL_XFORM_DQS3 */
438                         0x00000010, /* EMC_DLL_XFORM_DQS4 */
439                         0x00000010, /* EMC_DLL_XFORM_DQS5 */
440                         0x00000010, /* EMC_DLL_XFORM_DQS6 */
441                         0x00000010, /* EMC_DLL_XFORM_DQS7 */
442                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
443                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
444                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
445                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
446                         0x00000008, /* EMC_DLL_XFORM_QUSE4 */
447                         0x00000008, /* EMC_DLL_XFORM_QUSE5 */
448                         0x00000008, /* EMC_DLL_XFORM_QUSE6 */
449                         0x00000008, /* EMC_DLL_XFORM_QUSE7 */
450                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
451                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
452                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
453                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
454                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
455                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
456                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
457                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
458                         0x00088000, /* EMC_DLL_XFORM_DQ0 */
459                         0x00088000, /* EMC_DLL_XFORM_DQ1 */
460                         0x00088000, /* EMC_DLL_XFORM_DQ2 */
461                         0x00088000, /* EMC_DLL_XFORM_DQ3 */
462                         0x00100220, /* EMC_XM2CMDPADCTRL */
463                         0x0800201c, /* EMC_XM2DQSPADCTRL2 */
464                         0x00000000, /* EMC_XM2DQPADCTRL2 */
465                         0x77ffc004, /* EMC_XM2CLKPADCTRL */
466                         0x01f1f008, /* EMC_XM2COMPPADCTRL */
467                         0x00000000, /* EMC_XM2VTTGENPADCTRL */
468                         0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
469                         0x08000068, /* EMC_XM2QUSEPADCTRL */
470                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
471                         0x00000802, /* EMC_CTT_TERM_CTRL */
472                         0x00064000, /* EMC_ZCAL_INTERVAL */
473                         0x00000025, /* EMC_ZCAL_WAIT_CNT */
474                         0x00090009, /* EMC_MRS_WAIT_CNT */
475                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
476                         0x00000000, /* EMC_CTT */
477                         0x00000000, /* EMC_CTT_DURATION */
478                         0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */
479                         0x00000001, /* MC_EMEM_ARB_CFG */
480                         0xc0000013, /* MC_EMEM_ARB_OUTSTANDING_REQ */
481                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
482                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
483                         0x00000003, /* MC_EMEM_ARB_TIMING_RC */
484                         0x00000001, /* MC_EMEM_ARB_TIMING_RAS */
485                         0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
486                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
487                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
488                         0x00000004, /* MC_EMEM_ARB_TIMING_WAP2PRE */
489                         0x00000001, /* MC_EMEM_ARB_TIMING_R2R */
490                         0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
491                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
492                         0x00000002, /* MC_EMEM_ARB_TIMING_W2R */
493                         0x02020001, /* MC_EMEM_ARB_DA_TURNS */
494                         0x00060403, /* MC_EMEM_ARB_DA_COVERS */
495                         0x72430504, /* MC_EMEM_ARB_MISC0 */
496                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
497                         0x50000000, /* EMC_FBIO_SPARE */
498                         0xff00ff00, /* EMC_CFG_RSV */
499                 },
500                 0x0000000a, /* EMC_ZCAL_WAIT_CNT after clock change */
501                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
502                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
503                 0x00000000, /* Mode Register 0 */
504                 0x00010022, /* Mode Register 1 */
505                 0x00020001, /* Mode Register 2 */
506                 0x00000001, /* EMC_CFG.DYN_SELF_REF */
507         },
508         {
509                 0x32,       /* Rev 3.2 */
510                 204000,     /* SDRAM frequency */
511                 {
512                         0x0000000c, /* EMC_RC */
513                         0x0000001a, /* EMC_RFC */
514                         0x00000008, /* EMC_RAS */
515                         0x00000003, /* EMC_RP */
516                         0x00000005, /* EMC_R2W */
517                         0x00000004, /* EMC_W2R */
518                         0x00000001, /* EMC_R2P */
519                         0x00000006, /* EMC_W2P */
520                         0x00000003, /* EMC_RD_RCD */
521                         0x00000003, /* EMC_WR_RCD */
522                         0x00000002, /* EMC_RRD */
523                         0x00000002, /* EMC_REXT */
524                         0x00000000, /* EMC_WEXT */
525                         0x00000001, /* EMC_WDV */
526                         0x00000003, /* EMC_QUSE */
527                         0x00000001, /* EMC_QRST */
528                         0x0000000b, /* EMC_QSAFE */
529                         0x0000000a, /* EMC_RDV */
530                         0x00000303, /* EMC_REFRESH */
531                         0x00000000, /* EMC_BURST_REFRESH_NUM */
532                         0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */
533                         0x00000001, /* EMC_PDEX2WR */
534                         0x00000001, /* EMC_PDEX2RD */
535                         0x00000003, /* EMC_PCHG2PDEN */
536                         0x00000000, /* EMC_ACT2PDEN */
537                         0x00000001, /* EMC_AR2PDEN */
538                         0x00000007, /* EMC_RW2PDEN */
539                         0x0000001d, /* EMC_TXSR */
540                         0x0000001d, /* EMC_TXSRDLL */
541                         0x00000004, /* EMC_TCKE */
542                         0x0000000b, /* EMC_TFAW */
543                         0x00000005, /* EMC_TRPAB */
544                         0x00000004, /* EMC_TCLKSTABLE */
545                         0x00000002, /* EMC_TCLKSTOP */
546                         0x00000351, /* EMC_TREFBW */
547                         0x00000004, /* EMC_QUSE_EXTRA */
548                         0x00000006, /* EMC_FBIO_CFG6 */
549                         0x00000000, /* EMC_ODT_WRITE */
550                         0x00000000, /* EMC_ODT_READ */
551                         0x00004282, /* EMC_FBIO_CFG5 */
552                         0x004400a4, /* EMC_CFG_DIG_DLL */
553                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
554                         0x0007c000, /* EMC_DLL_XFORM_DQS0 */
555                         0x0007c000, /* EMC_DLL_XFORM_DQS1 */
556                         0x0007c000, /* EMC_DLL_XFORM_DQS2 */
557                         0x0007c000, /* EMC_DLL_XFORM_DQS3 */
558                         0x00000010, /* EMC_DLL_XFORM_DQS4 */
559                         0x00000010, /* EMC_DLL_XFORM_DQS5 */
560                         0x00000010, /* EMC_DLL_XFORM_DQS6 */
561                         0x00000010, /* EMC_DLL_XFORM_DQS7 */
562                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
563                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
564                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
565                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
566                         0x00000018, /* EMC_DLL_XFORM_QUSE4 */
567                         0x00000018, /* EMC_DLL_XFORM_QUSE5 */
568                         0x00000018, /* EMC_DLL_XFORM_QUSE6 */
569                         0x00000018, /* EMC_DLL_XFORM_QUSE7 */
570                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
571                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
572                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
573                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
574                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
575                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
576                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
577                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
578                         0x00088000, /* EMC_DLL_XFORM_DQ0 */
579                         0x00088000, /* EMC_DLL_XFORM_DQ1 */
580                         0x00088000, /* EMC_DLL_XFORM_DQ2 */
581                         0x00088000, /* EMC_DLL_XFORM_DQ3 */
582                         0x000f0220, /* EMC_XM2CMDPADCTRL */
583                         0x0800201c, /* EMC_XM2DQSPADCTRL2 */
584                         0x00000000, /* EMC_XM2DQPADCTRL2 */
585                         0x77ffc004, /* EMC_XM2CLKPADCTRL */
586                         0x01f1f008, /* EMC_XM2COMPPADCTRL */
587                         0x00000000, /* EMC_XM2VTTGENPADCTRL */
588                         0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
589                         0x08000068, /* EMC_XM2QUSEPADCTRL */
590                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
591                         0x00000802, /* EMC_CTT_TERM_CTRL */
592                         0x00064000, /* EMC_ZCAL_INTERVAL */
593                         0x0000004a, /* EMC_ZCAL_WAIT_CNT */
594                         0x00090009, /* EMC_MRS_WAIT_CNT */
595                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
596                         0x00000000, /* EMC_CTT */
597                         0x00000000, /* EMC_CTT_DURATION */
598                         0x80000713, /* EMC_DYN_SELF_REF_CONTROL */
599                         0x00000003, /* MC_EMEM_ARB_CFG */
600                         0xc0000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */
601                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
602                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
603                         0x00000006, /* MC_EMEM_ARB_TIMING_RC */
604                         0x00000003, /* MC_EMEM_ARB_TIMING_RAS */
605                         0x00000005, /* MC_EMEM_ARB_TIMING_FAW */
606                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
607                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
608                         0x00000004, /* MC_EMEM_ARB_TIMING_WAP2PRE */
609                         0x00000001, /* MC_EMEM_ARB_TIMING_R2R */
610                         0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
611                         0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
612                         0x00000002, /* MC_EMEM_ARB_TIMING_W2R */
613                         0x02030001, /* MC_EMEM_ARB_DA_TURNS */
614                         0x00070506, /* MC_EMEM_ARB_DA_COVERS */
615                         0x71e40a07, /* MC_EMEM_ARB_MISC0 */
616                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
617                         0x50000000, /* EMC_FBIO_SPARE */
618                         0xff00ff00, /* EMC_CFG_RSV */
619                 },
620                 0x00000013, /* EMC_ZCAL_WAIT_CNT after clock change */
621                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
622                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
623                 0x00000000, /* Mode Register 0 */
624                 0x00010042, /* Mode Register 1 */
625                 0x00020001, /* Mode Register 2 */
626                 0x00000001, /* EMC_CFG.DYN_SELF_REF */
627         },
628         {
629                 0x32,       /* Rev 3.2 */
630                 400000,     /* SDRAM frequency */
631                 {
632                         0x00000017, /* EMC_RC */
633                         0x00000033, /* EMC_RFC */
634                         0x00000010, /* EMC_RAS */
635                         0x00000007, /* EMC_RP */
636                         0x00000007, /* EMC_R2W */
637                         0x00000007, /* EMC_W2R */
638                         0x00000002, /* EMC_R2P */
639                         0x0000000a, /* EMC_W2P */
640                         0x00000007, /* EMC_RD_RCD */
641                         0x00000007, /* EMC_WR_RCD */
642                         0x00000003, /* EMC_RRD */
643                         0x00000002, /* EMC_REXT */
644                         0x00000000, /* EMC_WEXT */
645                         0x00000003, /* EMC_WDV */
646                         0x00000007, /* EMC_QUSE */
647                         0x00000004, /* EMC_QRST */
648                         0x0000000b, /* EMC_QSAFE */
649                         0x0000000e, /* EMC_RDV */
650                         0x000005e9, /* EMC_REFRESH */
651                         0x00000000, /* EMC_BURST_REFRESH_NUM */
652                         0x0000017a, /* EMC_PRE_REFRESH_REQ_CNT */
653                         0x00000002, /* EMC_PDEX2WR */
654                         0x00000002, /* EMC_PDEX2RD */
655                         0x00000007, /* EMC_PCHG2PDEN */
656                         0x00000000, /* EMC_ACT2PDEN */
657                         0x00000001, /* EMC_AR2PDEN */
658                         0x0000000c, /* EMC_RW2PDEN */
659                         0x00000038, /* EMC_TXSR */
660                         0x00000038, /* EMC_TXSRDLL */
661                         0x00000006, /* EMC_TCKE */
662                         0x00000014, /* EMC_TFAW */
663                         0x00000009, /* EMC_TRPAB */
664                         0x00000004, /* EMC_TCLKSTABLE */
665                         0x00000002, /* EMC_TCLKSTOP */
666                         0x00000680, /* EMC_TREFBW */
667                         0x00000000, /* EMC_QUSE_EXTRA */
668                         0x00000006, /* EMC_FBIO_CFG6 */
669                         0x00000000, /* EMC_ODT_WRITE */
670                         0x00000000, /* EMC_ODT_READ */
671                         0x00006282, /* EMC_FBIO_CFG5 */
672                         0x001d0084, /* EMC_CFG_DIG_DLL */
673                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
674                         0x00024000, /* EMC_DLL_XFORM_DQS0 */
675                         0x00024000, /* EMC_DLL_XFORM_DQS1 */
676                         0x00024000, /* EMC_DLL_XFORM_DQS2 */
677                         0x00024000, /* EMC_DLL_XFORM_DQS3 */
678                         0x00000010, /* EMC_DLL_XFORM_DQS4 */
679                         0x00000010, /* EMC_DLL_XFORM_DQS5 */
680                         0x00000010, /* EMC_DLL_XFORM_DQS6 */
681                         0x00000010, /* EMC_DLL_XFORM_DQS7 */
682                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
683                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
684                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
685                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
686                         0x00000008, /* EMC_DLL_XFORM_QUSE4 */
687                         0x00000008, /* EMC_DLL_XFORM_QUSE5 */
688                         0x00000008, /* EMC_DLL_XFORM_QUSE6 */
689                         0x00000008, /* EMC_DLL_XFORM_QUSE7 */
690                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
691                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
692                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
693                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
694                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
695                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
696                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
697                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
698                         0x00048000, /* EMC_DLL_XFORM_DQ0 */
699                         0x00048000, /* EMC_DLL_XFORM_DQ1 */
700                         0x00048000, /* EMC_DLL_XFORM_DQ2 */
701                         0x00048000, /* EMC_DLL_XFORM_DQ3 */
702                         0x00060220, /* EMC_XM2CMDPADCTRL */
703                         0x0800003d, /* EMC_XM2DQSPADCTRL2 */
704                         0x00000000, /* EMC_XM2DQPADCTRL2 */
705                         0x77ffc004, /* EMC_XM2CLKPADCTRL */
706                         0x01f1f408, /* EMC_XM2COMPPADCTRL */
707                         0x00000000, /* EMC_XM2VTTGENPADCTRL */
708                         0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
709                         0x08000068, /* EMC_XM2QUSEPADCTRL */
710                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
711                         0x00000802, /* EMC_CTT_TERM_CTRL */
712                         0x00064000, /* EMC_ZCAL_INTERVAL */
713                         0x00000090, /* EMC_ZCAL_WAIT_CNT */
714                         0x000c000c, /* EMC_MRS_WAIT_CNT */
715                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
716                         0x00000000, /* EMC_CTT */
717                         0x00000000, /* EMC_CTT_DURATION */
718                         0x80000ce6, /* EMC_DYN_SELF_REF_CONTROL */
719                         0x00000006, /* MC_EMEM_ARB_CFG */
720                         0xc0000048, /* MC_EMEM_ARB_OUTSTANDING_REQ */
721                         0x00000002, /* MC_EMEM_ARB_TIMING_RCD */
722                         0x00000003, /* MC_EMEM_ARB_TIMING_RP */
723                         0x0000000c, /* MC_EMEM_ARB_TIMING_RC */
724                         0x00000007, /* MC_EMEM_ARB_TIMING_RAS */
725                         0x00000009, /* MC_EMEM_ARB_TIMING_FAW */
726                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
727                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
728                         0x00000006, /* MC_EMEM_ARB_TIMING_WAP2PRE */
729                         0x00000001, /* MC_EMEM_ARB_TIMING_R2R */
730                         0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
731                         0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
732                         0x00000004, /* MC_EMEM_ARB_TIMING_W2R */
733                         0x04040001, /* MC_EMEM_ARB_DA_TURNS */
734                         0x000d090c, /* MC_EMEM_ARB_DA_COVERS */
735                         0x71c6120d, /* MC_EMEM_ARB_MISC0 */
736                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
737                         0x10000000, /* EMC_FBIO_SPARE */
738                         0xff00ff00, /* EMC_CFG_RSV */
739                 },
740                 0x00000024, /* EMC_ZCAL_WAIT_CNT after clock change */
741                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
742                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
743                 0x00000000, /* Mode Register 0 */
744                 0x00010082, /* Mode Register 1 */
745                 0x00020004, /* Mode Register 2 */
746                 0x00000000, /* EMC_CFG.DYN_SELF_REF */
747         },
748 };
749
750 static const struct tegra_emc_table enterprise_emc_tables_kmkts0_a03[] = {
751         {
752                 0x32,       /* Rev 3.2 */
753                 12750,      /* SDRAM frequency */
754                 {
755                         0x00000000, /* EMC_RC */
756                         0x00000001, /* EMC_RFC */
757                         0x00000002, /* EMC_RAS */
758                         0x00000002, /* EMC_RP */
759                         0x00000004, /* EMC_R2W */
760                         0x00000004, /* EMC_W2R */
761                         0x00000001, /* EMC_R2P */
762                         0x00000005, /* EMC_W2P */
763                         0x00000002, /* EMC_RD_RCD */
764                         0x00000002, /* EMC_WR_RCD */
765                         0x00000001, /* EMC_RRD */
766                         0x00000001, /* EMC_REXT */
767                         0x00000000, /* EMC_WEXT */
768                         0x00000001, /* EMC_WDV */
769                         0x00000003, /* EMC_QUSE */
770                         0x00000001, /* EMC_QRST */
771                         0x0000000b, /* EMC_QSAFE */
772                         0x0000000a, /* EMC_RDV */
773                         0x0000002f, /* EMC_REFRESH */
774                         0x00000000, /* EMC_BURST_REFRESH_NUM */
775                         0x0000000b, /* EMC_PRE_REFRESH_REQ_CNT */
776                         0x00000001, /* EMC_PDEX2WR */
777                         0x00000001, /* EMC_PDEX2RD */
778                         0x00000002, /* EMC_PCHG2PDEN */
779                         0x00000000, /* EMC_ACT2PDEN */
780                         0x00000001, /* EMC_AR2PDEN */
781                         0x00000007, /* EMC_RW2PDEN */
782                         0x00000002, /* EMC_TXSR */
783                         0x00000002, /* EMC_TXSRDLL */
784                         0x00000003, /* EMC_TCKE */
785                         0x00000008, /* EMC_TFAW */
786                         0x00000004, /* EMC_TRPAB */
787                         0x00000001, /* EMC_TCLKSTABLE */
788                         0x00000002, /* EMC_TCLKSTOP */
789                         0x00000036, /* EMC_TREFBW */
790                         0x00000004, /* EMC_QUSE_EXTRA */
791                         0x00000006, /* EMC_FBIO_CFG6 */
792                         0x00000000, /* EMC_ODT_WRITE */
793                         0x00000000, /* EMC_ODT_READ */
794                         0x00004282, /* EMC_FBIO_CFG5 */
795                         0x007800a4, /* EMC_CFG_DIG_DLL */
796                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
797                         0x000fc000, /* EMC_DLL_XFORM_DQS0 */
798                         0x000fc000, /* EMC_DLL_XFORM_DQS1 */
799                         0x000fc000, /* EMC_DLL_XFORM_DQS2 */
800                         0x000fc000, /* EMC_DLL_XFORM_DQS3 */
801                         0x000fc000, /* EMC_DLL_XFORM_DQS4 */
802                         0x000fc000, /* EMC_DLL_XFORM_DQS5 */
803                         0x000fc000, /* EMC_DLL_XFORM_DQS6 */
804                         0x000fc000, /* EMC_DLL_XFORM_DQS7 */
805                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
806                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
807                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
808                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
809                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
810                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
811                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
812                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
813                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
814                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
815                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
816                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
817                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
818                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
819                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
820                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
821                         0x000fc000, /* EMC_DLL_XFORM_DQ0 */
822                         0x000fc000, /* EMC_DLL_XFORM_DQ1 */
823                         0x000fc000, /* EMC_DLL_XFORM_DQ2 */
824                         0x000fc000, /* EMC_DLL_XFORM_DQ3 */
825                         0x00100220, /* EMC_XM2CMDPADCTRL */
826                         0x0800201c, /* EMC_XM2DQSPADCTRL2 */
827                         0x00000000, /* EMC_XM2DQPADCTRL2 */
828                         0x77ffc004, /* EMC_XM2CLKPADCTRL */
829                         0x01f1f008, /* EMC_XM2COMPPADCTRL */
830                         0x00000000, /* EMC_XM2VTTGENPADCTRL */
831                         0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
832                         0x08000068, /* EMC_XM2QUSEPADCTRL */
833                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
834                         0x00000802, /* EMC_CTT_TERM_CTRL */
835                         0x00064000, /* EMC_ZCAL_INTERVAL */
836                         0x00000009, /* EMC_ZCAL_WAIT_CNT */
837                         0x00090009, /* EMC_MRS_WAIT_CNT */
838                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
839                         0x00000000, /* EMC_CTT */
840                         0x00000000, /* EMC_CTT_DURATION */
841                         0x80000164, /* EMC_DYN_SELF_REF_CONTROL */
842                         0x00050001, /* MC_EMEM_ARB_CFG */
843                         0xc0000008, /* MC_EMEM_ARB_OUTSTANDING_REQ */
844                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
845                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
846                         0x00000002, /* MC_EMEM_ARB_TIMING_RC */
847                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
848                         0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
849                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
850                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
851                         0x00000004, /* MC_EMEM_ARB_TIMING_WAP2PRE */
852                         0x00000001, /* MC_EMEM_ARB_TIMING_R2R */
853                         0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
854                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
855                         0x00000002, /* MC_EMEM_ARB_TIMING_W2R */
856                         0x02020001, /* MC_EMEM_ARB_DA_TURNS */
857                         0x00060402, /* MC_EMEM_ARB_DA_COVERS */
858                         0x77230303, /* MC_EMEM_ARB_MISC0 */
859                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
860                         0xe0000000, /* EMC_FBIO_SPARE */
861                         0xff00ff00, /* EMC_CFG_RSV */
862                 },
863                 0x00000009, /* EMC_ZCAL_WAIT_CNT after clock change */
864                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
865                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
866                 0x00000000, /* Mode Register 0 */
867                 0x00010022, /* Mode Register 1 */
868                 0x00020001, /* Mode Register 2 */
869                 0x00000001, /* EMC_CFG.DYN_SELF_REF */
870         },
871         {
872                 0x32,       /* Rev 3.2 */
873                 25500,      /* SDRAM frequency */
874                 {
875                         0x00000001, /* EMC_RC */
876                         0x00000003, /* EMC_RFC */
877                         0x00000002, /* EMC_RAS */
878                         0x00000002, /* EMC_RP */
879                         0x00000004, /* EMC_R2W */
880                         0x00000004, /* EMC_W2R */
881                         0x00000001, /* EMC_R2P */
882                         0x00000005, /* EMC_W2P */
883                         0x00000002, /* EMC_RD_RCD */
884                         0x00000002, /* EMC_WR_RCD */
885                         0x00000001, /* EMC_RRD */
886                         0x00000001, /* EMC_REXT */
887                         0x00000000, /* EMC_WEXT */
888                         0x00000001, /* EMC_WDV */
889                         0x00000003, /* EMC_QUSE */
890                         0x00000001, /* EMC_QRST */
891                         0x0000000b, /* EMC_QSAFE */
892                         0x0000000a, /* EMC_RDV */
893                         0x00000060, /* EMC_REFRESH */
894                         0x00000000, /* EMC_BURST_REFRESH_NUM */
895                         0x00000018, /* EMC_PRE_REFRESH_REQ_CNT */
896                         0x00000001, /* EMC_PDEX2WR */
897                         0x00000001, /* EMC_PDEX2RD */
898                         0x00000002, /* EMC_PCHG2PDEN */
899                         0x00000000, /* EMC_ACT2PDEN */
900                         0x00000001, /* EMC_AR2PDEN */
901                         0x00000007, /* EMC_RW2PDEN */
902                         0x00000004, /* EMC_TXSR */
903                         0x00000004, /* EMC_TXSRDLL */
904                         0x00000003, /* EMC_TCKE */
905                         0x00000008, /* EMC_TFAW */
906                         0x00000004, /* EMC_TRPAB */
907                         0x00000001, /* EMC_TCLKSTABLE */
908                         0x00000002, /* EMC_TCLKSTOP */
909                         0x0000006b, /* EMC_TREFBW */
910                         0x00000004, /* EMC_QUSE_EXTRA */
911                         0x00000006, /* EMC_FBIO_CFG6 */
912                         0x00000000, /* EMC_ODT_WRITE */
913                         0x00000000, /* EMC_ODT_READ */
914                         0x00004282, /* EMC_FBIO_CFG5 */
915                         0x007800a4, /* EMC_CFG_DIG_DLL */
916                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
917                         0x000fc000, /* EMC_DLL_XFORM_DQS0 */
918                         0x000fc000, /* EMC_DLL_XFORM_DQS1 */
919                         0x000fc000, /* EMC_DLL_XFORM_DQS2 */
920                         0x000fc000, /* EMC_DLL_XFORM_DQS3 */
921                         0x000fc000, /* EMC_DLL_XFORM_DQS4 */
922                         0x000fc000, /* EMC_DLL_XFORM_DQS5 */
923                         0x000fc000, /* EMC_DLL_XFORM_DQS6 */
924                         0x000fc000, /* EMC_DLL_XFORM_DQS7 */
925                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
926                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
927                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
928                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
929                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
930                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
931                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
932                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
933                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
934                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
935                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
936                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
937                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
938                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
939                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
940                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
941                         0x000fc000, /* EMC_DLL_XFORM_DQ0 */
942                         0x000fc000, /* EMC_DLL_XFORM_DQ1 */
943                         0x000fc000, /* EMC_DLL_XFORM_DQ2 */
944                         0x000fc000, /* EMC_DLL_XFORM_DQ3 */
945                         0x00100220, /* EMC_XM2CMDPADCTRL */
946                         0x0800201c, /* EMC_XM2DQSPADCTRL2 */
947                         0x00000000, /* EMC_XM2DQPADCTRL2 */
948                         0x77ffc004, /* EMC_XM2CLKPADCTRL */
949                         0x01f1f008, /* EMC_XM2COMPPADCTRL */
950                         0x00000000, /* EMC_XM2VTTGENPADCTRL */
951                         0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
952                         0x08000068, /* EMC_XM2QUSEPADCTRL */
953                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
954                         0x00000802, /* EMC_CTT_TERM_CTRL */
955                         0x00064000, /* EMC_ZCAL_INTERVAL */
956                         0x0000000a, /* EMC_ZCAL_WAIT_CNT */
957                         0x00090009, /* EMC_MRS_WAIT_CNT */
958                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
959                         0x00000000, /* EMC_CTT */
960                         0x00000000, /* EMC_CTT_DURATION */
961                         0x800001c5, /* EMC_DYN_SELF_REF_CONTROL */
962                         0x00020001, /* MC_EMEM_ARB_CFG */
963                         0xc0000008, /* MC_EMEM_ARB_OUTSTANDING_REQ */
964                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
965                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
966                         0x00000002, /* MC_EMEM_ARB_TIMING_RC */
967                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
968                         0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
969                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
970                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
971                         0x00000004, /* MC_EMEM_ARB_TIMING_WAP2PRE */
972                         0x00000001, /* MC_EMEM_ARB_TIMING_R2R */
973                         0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
974                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
975                         0x00000002, /* MC_EMEM_ARB_TIMING_W2R */
976                         0x02020001, /* MC_EMEM_ARB_DA_TURNS */
977                         0x00060402, /* MC_EMEM_ARB_DA_COVERS */
978                         0x73e30303, /* MC_EMEM_ARB_MISC0 */
979                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
980                         0xe0000000, /* EMC_FBIO_SPARE */
981                         0xff00ff00, /* EMC_CFG_RSV */
982                 },
983                 0x00000009, /* EMC_ZCAL_WAIT_CNT after clock change */
984                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
985                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
986                 0x00000000, /* Mode Register 0 */
987                 0x00010022, /* Mode Register 1 */
988                 0x00020001, /* Mode Register 2 */
989                 0x00000001, /* EMC_CFG.DYN_SELF_REF */
990         },
991         {
992                 0x32,       /* Rev 3.2 */
993                 51000,      /* SDRAM frequency */
994                 {
995                         0x00000003, /* EMC_RC */
996                         0x00000006, /* EMC_RFC */
997                         0x00000002, /* EMC_RAS */
998                         0x00000002, /* EMC_RP */
999                         0x00000004, /* EMC_R2W */
1000                         0x00000004, /* EMC_W2R */
1001                         0x00000001, /* EMC_R2P */
1002                         0x00000005, /* EMC_W2P */
1003                         0x00000002, /* EMC_RD_RCD */
1004                         0x00000002, /* EMC_WR_RCD */
1005                         0x00000001, /* EMC_RRD */
1006                         0x00000001, /* EMC_REXT */
1007                         0x00000000, /* EMC_WEXT */
1008                         0x00000001, /* EMC_WDV */
1009                         0x00000003, /* EMC_QUSE */
1010                         0x00000001, /* EMC_QRST */
1011                         0x0000000b, /* EMC_QSAFE */
1012                         0x0000000a, /* EMC_RDV */
1013                         0x000000c0, /* EMC_REFRESH */
1014                         0x00000000, /* EMC_BURST_REFRESH_NUM */
1015                         0x00000030, /* EMC_PRE_REFRESH_REQ_CNT */
1016                         0x00000001, /* EMC_PDEX2WR */
1017                         0x00000001, /* EMC_PDEX2RD */
1018                         0x00000002, /* EMC_PCHG2PDEN */
1019                         0x00000000, /* EMC_ACT2PDEN */
1020                         0x00000001, /* EMC_AR2PDEN */
1021                         0x00000007, /* EMC_RW2PDEN */
1022                         0x00000008, /* EMC_TXSR */
1023                         0x00000008, /* EMC_TXSRDLL */
1024                         0x00000003, /* EMC_TCKE */
1025                         0x00000008, /* EMC_TFAW */
1026                         0x00000004, /* EMC_TRPAB */
1027                         0x00000001, /* EMC_TCLKSTABLE */
1028                         0x00000002, /* EMC_TCLKSTOP */
1029                         0x000000d5, /* EMC_TREFBW */
1030                         0x00000004, /* EMC_QUSE_EXTRA */
1031                         0x00000006, /* EMC_FBIO_CFG6 */
1032                         0x00000000, /* EMC_ODT_WRITE */
1033                         0x00000000, /* EMC_ODT_READ */
1034                         0x00004282, /* EMC_FBIO_CFG5 */
1035                         0x007800a4, /* EMC_CFG_DIG_DLL */
1036                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1037                         0x000fc000, /* EMC_DLL_XFORM_DQS0 */
1038                         0x000fc000, /* EMC_DLL_XFORM_DQS1 */
1039                         0x000fc000, /* EMC_DLL_XFORM_DQS2 */
1040                         0x000fc000, /* EMC_DLL_XFORM_DQS3 */
1041                         0x000fc000, /* EMC_DLL_XFORM_DQS4 */
1042                         0x000fc000, /* EMC_DLL_XFORM_DQS5 */
1043                         0x000fc000, /* EMC_DLL_XFORM_DQS6 */
1044                         0x000fc000, /* EMC_DLL_XFORM_DQS7 */
1045                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1046                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1047                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1048                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1049                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
1050                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
1051                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
1052                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
1053                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1054                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1055                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1056                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1057                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1058                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1059                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1060                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1061                         0x000fc000, /* EMC_DLL_XFORM_DQ0 */
1062                         0x000fc000, /* EMC_DLL_XFORM_DQ1 */
1063                         0x000fc000, /* EMC_DLL_XFORM_DQ2 */
1064                         0x000fc000, /* EMC_DLL_XFORM_DQ3 */
1065                         0x00100220, /* EMC_XM2CMDPADCTRL */
1066                         0x0800201c, /* EMC_XM2DQSPADCTRL2 */
1067                         0x00000000, /* EMC_XM2DQPADCTRL2 */
1068                         0x77ffc004, /* EMC_XM2CLKPADCTRL */
1069                         0x01f1f008, /* EMC_XM2COMPPADCTRL */
1070                         0x00000000, /* EMC_XM2VTTGENPADCTRL */
1071                         0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
1072                         0x08000068, /* EMC_XM2QUSEPADCTRL */
1073                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
1074                         0x00000802, /* EMC_CTT_TERM_CTRL */
1075                         0x00064000, /* EMC_ZCAL_INTERVAL */
1076                         0x00000013, /* EMC_ZCAL_WAIT_CNT */
1077                         0x00090009, /* EMC_MRS_WAIT_CNT */
1078                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
1079                         0x00000000, /* EMC_CTT */
1080                         0x00000000, /* EMC_CTT_DURATION */
1081                         0x80000287, /* EMC_DYN_SELF_REF_CONTROL */
1082                         0x00010001, /* MC_EMEM_ARB_CFG */
1083                         0xc000000a, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1084                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
1085                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
1086                         0x00000002, /* MC_EMEM_ARB_TIMING_RC */
1087                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
1088                         0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
1089                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
1090                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1091                         0x00000004, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1092                         0x00000001, /* MC_EMEM_ARB_TIMING_R2R */
1093                         0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
1094                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
1095                         0x00000002, /* MC_EMEM_ARB_TIMING_W2R */
1096                         0x02020001, /* MC_EMEM_ARB_DA_TURNS */
1097                         0x00060402, /* MC_EMEM_ARB_DA_COVERS */
1098                         0x72c30303, /* MC_EMEM_ARB_MISC0 */
1099                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1100                         0xe0000000, /* EMC_FBIO_SPARE */
1101                         0xff00ff00, /* EMC_CFG_RSV */
1102                 },
1103                 0x00000009, /* EMC_ZCAL_WAIT_CNT after clock change */
1104                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1105                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
1106                 0x00000000, /* Mode Register 0 */
1107                 0x00010022, /* Mode Register 1 */
1108                 0x00020001, /* Mode Register 2 */
1109                 0x00000001, /* EMC_CFG.DYN_SELF_REF */
1110         },
1111         {
1112                 0x32,       /* Rev 3.2 */
1113                 102000,     /* SDRAM frequency */
1114                 {
1115                         0x00000006, /* EMC_RC */
1116                         0x0000000d, /* EMC_RFC */
1117                         0x00000004, /* EMC_RAS */
1118                         0x00000002, /* EMC_RP */
1119                         0x00000004, /* EMC_R2W */
1120                         0x00000004, /* EMC_W2R */
1121                         0x00000002, /* EMC_R2P */
1122                         0x00000005, /* EMC_W2P */
1123                         0x00000002, /* EMC_RD_RCD */
1124                         0x00000002, /* EMC_WR_RCD */
1125                         0x00000001, /* EMC_RRD */
1126                         0x00000001, /* EMC_REXT */
1127                         0x00000000, /* EMC_WEXT */
1128                         0x00000001, /* EMC_WDV */
1129                         0x00000003, /* EMC_QUSE */
1130                         0x00000001, /* EMC_QRST */
1131                         0x0000000b, /* EMC_QSAFE */
1132                         0x0000000a, /* EMC_RDV */
1133                         0x00000181, /* EMC_REFRESH */
1134                         0x00000000, /* EMC_BURST_REFRESH_NUM */
1135                         0x00000060, /* EMC_PRE_REFRESH_REQ_CNT */
1136                         0x00000001, /* EMC_PDEX2WR */
1137                         0x00000001, /* EMC_PDEX2RD */
1138                         0x00000002, /* EMC_PCHG2PDEN */
1139                         0x00000000, /* EMC_ACT2PDEN */
1140                         0x00000001, /* EMC_AR2PDEN */
1141                         0x00000007, /* EMC_RW2PDEN */
1142                         0x0000000f, /* EMC_TXSR */
1143                         0x0000000f, /* EMC_TXSRDLL */
1144                         0x00000003, /* EMC_TCKE */
1145                         0x00000008, /* EMC_TFAW */
1146                         0x00000004, /* EMC_TRPAB */
1147                         0x00000001, /* EMC_TCLKSTABLE */
1148                         0x00000002, /* EMC_TCLKSTOP */
1149                         0x000001a9, /* EMC_TREFBW */
1150                         0x00000004, /* EMC_QUSE_EXTRA */
1151                         0x00000006, /* EMC_FBIO_CFG6 */
1152                         0x00000000, /* EMC_ODT_WRITE */
1153                         0x00000000, /* EMC_ODT_READ */
1154                         0x00004282, /* EMC_FBIO_CFG5 */
1155                         0x007800a4, /* EMC_CFG_DIG_DLL */
1156                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1157                         0x000fc000, /* EMC_DLL_XFORM_DQS0 */
1158                         0x000fc000, /* EMC_DLL_XFORM_DQS1 */
1159                         0x000fc000, /* EMC_DLL_XFORM_DQS2 */
1160                         0x000fc000, /* EMC_DLL_XFORM_DQS3 */
1161                         0x000fc000, /* EMC_DLL_XFORM_DQS4 */
1162                         0x000fc000, /* EMC_DLL_XFORM_DQS5 */
1163                         0x000fc000, /* EMC_DLL_XFORM_DQS6 */
1164                         0x000fc000, /* EMC_DLL_XFORM_DQS7 */
1165                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1166                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1167                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1168                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1169                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
1170                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
1171                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
1172                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
1173                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1174                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1175                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1176                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1177                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1178                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1179                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1180                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1181                         0x000fc000, /* EMC_DLL_XFORM_DQ0 */
1182                         0x000fc000, /* EMC_DLL_XFORM_DQ1 */
1183                         0x000fc000, /* EMC_DLL_XFORM_DQ2 */
1184                         0x000fc000, /* EMC_DLL_XFORM_DQ3 */
1185                         0x00100220, /* EMC_XM2CMDPADCTRL */
1186                         0x0800201c, /* EMC_XM2DQSPADCTRL2 */
1187                         0x00000000, /* EMC_XM2DQPADCTRL2 */
1188                         0x77ffc004, /* EMC_XM2CLKPADCTRL */
1189                         0x01f1f008, /* EMC_XM2COMPPADCTRL */
1190                         0x00000000, /* EMC_XM2VTTGENPADCTRL */
1191                         0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
1192                         0x08000068, /* EMC_XM2QUSEPADCTRL */
1193                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
1194                         0x00000802, /* EMC_CTT_TERM_CTRL */
1195                         0x00000000, /* EMC_ZCAL_INTERVAL */
1196                         0x0000000a, /* EMC_ZCAL_WAIT_CNT */
1197                         0x00090009, /* EMC_MRS_WAIT_CNT */
1198                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
1199                         0x00000000, /* EMC_CTT */
1200                         0x00000000, /* EMC_CTT_DURATION */
1201                         0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */
1202                         0x00000001, /* MC_EMEM_ARB_CFG */
1203                         0xc0000013, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1204                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
1205                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
1206                         0x00000003, /* MC_EMEM_ARB_TIMING_RC */
1207                         0x00000001, /* MC_EMEM_ARB_TIMING_RAS */
1208                         0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
1209                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
1210                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1211                         0x00000004, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1212                         0x00000001, /* MC_EMEM_ARB_TIMING_R2R */
1213                         0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
1214                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
1215                         0x00000002, /* MC_EMEM_ARB_TIMING_W2R */
1216                         0x02020001, /* MC_EMEM_ARB_DA_TURNS */
1217                         0x00060403, /* MC_EMEM_ARB_DA_COVERS */
1218                         0x72430504, /* MC_EMEM_ARB_MISC0 */
1219                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1220                         0xe0000000, /* EMC_FBIO_SPARE */
1221                         0xff00ff00, /* EMC_CFG_RSV */
1222                 },
1223                 0x0000000a, /* EMC_ZCAL_WAIT_CNT after clock change */
1224                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1225                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
1226                 0x00000000, /* Mode Register 0 */
1227                 0x00010022, /* Mode Register 1 */
1228                 0x00020001, /* Mode Register 2 */
1229                 0x00000001, /* EMC_CFG.DYN_SELF_REF */
1230         },
1231         {
1232                 0x32,       /* Rev 3.2 */
1233                 204000,     /* SDRAM frequency */
1234                 {
1235                         0x0000000c, /* EMC_RC */
1236                         0x0000001a, /* EMC_RFC */
1237                         0x00000008, /* EMC_RAS */
1238                         0x00000003, /* EMC_RP */
1239                         0x00000005, /* EMC_R2W */
1240                         0x00000004, /* EMC_W2R */
1241                         0x00000002, /* EMC_R2P */
1242                         0x00000006, /* EMC_W2P */
1243                         0x00000003, /* EMC_RD_RCD */
1244                         0x00000003, /* EMC_WR_RCD */
1245                         0x00000002, /* EMC_RRD */
1246                         0x00000002, /* EMC_REXT */
1247                         0x00000000, /* EMC_WEXT */
1248                         0x00000001, /* EMC_WDV */
1249                         0x00000003, /* EMC_QUSE */
1250                         0x00000001, /* EMC_QRST */
1251                         0x0000000c, /* EMC_QSAFE */
1252                         0x0000000b, /* EMC_RDV */
1253                         0x00000303, /* EMC_REFRESH */
1254                         0x00000000, /* EMC_BURST_REFRESH_NUM */
1255                         0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */
1256                         0x00000001, /* EMC_PDEX2WR */
1257                         0x00000001, /* EMC_PDEX2RD */
1258                         0x00000003, /* EMC_PCHG2PDEN */
1259                         0x00000000, /* EMC_ACT2PDEN */
1260                         0x00000001, /* EMC_AR2PDEN */
1261                         0x00000007, /* EMC_RW2PDEN */
1262                         0x0000001d, /* EMC_TXSR */
1263                         0x0000001d, /* EMC_TXSRDLL */
1264                         0x00000004, /* EMC_TCKE */
1265                         0x0000000b, /* EMC_TFAW */
1266                         0x00000005, /* EMC_TRPAB */
1267                         0x00000001, /* EMC_TCLKSTABLE */
1268                         0x00000002, /* EMC_TCLKSTOP */
1269                         0x00000351, /* EMC_TREFBW */
1270                         0x00000004, /* EMC_QUSE_EXTRA */
1271                         0x00000006, /* EMC_FBIO_CFG6 */
1272                         0x00000000, /* EMC_ODT_WRITE */
1273                         0x00000000, /* EMC_ODT_READ */
1274                         0x00004282, /* EMC_FBIO_CFG5 */
1275                         0x004400a4, /* EMC_CFG_DIG_DLL */
1276                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1277                         0x0007c000, /* EMC_DLL_XFORM_DQS0 */
1278                         0x0007c000, /* EMC_DLL_XFORM_DQS1 */
1279                         0x0007c000, /* EMC_DLL_XFORM_DQS2 */
1280                         0x0007c000, /* EMC_DLL_XFORM_DQS3 */
1281                         0x00072000, /* EMC_DLL_XFORM_DQS4 */
1282                         0x00072000, /* EMC_DLL_XFORM_DQS5 */
1283                         0x00072000, /* EMC_DLL_XFORM_DQS6 */
1284                         0x00072000, /* EMC_DLL_XFORM_DQS7 */
1285                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1286                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1287                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1288                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1289                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
1290                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
1291                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
1292                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
1293                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1294                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1295                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1296                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1297                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1298                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1299                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1300                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1301                         0x00088000, /* EMC_DLL_XFORM_DQ0 */
1302                         0x00088000, /* EMC_DLL_XFORM_DQ1 */
1303                         0x00088000, /* EMC_DLL_XFORM_DQ2 */
1304                         0x00088000, /* EMC_DLL_XFORM_DQ3 */
1305                         0x000e0220, /* EMC_XM2CMDPADCTRL */
1306                         0x0800201c, /* EMC_XM2DQSPADCTRL2 */
1307                         0x00000000, /* EMC_XM2DQPADCTRL2 */
1308                         0x77ffc004, /* EMC_XM2CLKPADCTRL */
1309                         0x01f1f008, /* EMC_XM2COMPPADCTRL */
1310                         0x00000000, /* EMC_XM2VTTGENPADCTRL */
1311                         0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
1312                         0x08000068, /* EMC_XM2QUSEPADCTRL */
1313                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
1314                         0x00000802, /* EMC_CTT_TERM_CTRL */
1315                         0x00000000, /* EMC_ZCAL_INTERVAL */
1316                         0x00000013, /* EMC_ZCAL_WAIT_CNT */
1317                         0x00090009, /* EMC_MRS_WAIT_CNT */
1318                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
1319                         0x00000000, /* EMC_CTT */
1320                         0x00000000, /* EMC_CTT_DURATION */
1321                         0x80000713, /* EMC_DYN_SELF_REF_CONTROL */
1322                         0x00000003, /* MC_EMEM_ARB_CFG */
1323                         0xc0000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1324                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
1325                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
1326                         0x00000006, /* MC_EMEM_ARB_TIMING_RC */
1327                         0x00000003, /* MC_EMEM_ARB_TIMING_RAS */
1328                         0x00000005, /* MC_EMEM_ARB_TIMING_FAW */
1329                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
1330                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1331                         0x00000004, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1332                         0x00000001, /* MC_EMEM_ARB_TIMING_R2R */
1333                         0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
1334                         0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
1335                         0x00000002, /* MC_EMEM_ARB_TIMING_W2R */
1336                         0x02030001, /* MC_EMEM_ARB_DA_TURNS */
1337                         0x00070506, /* MC_EMEM_ARB_DA_COVERS */
1338                         0x71e40a07, /* MC_EMEM_ARB_MISC0 */
1339                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1340                         0xe0000000, /* EMC_FBIO_SPARE */
1341                         0xff00ff00, /* EMC_CFG_RSV */
1342                 },
1343                 0x00000013, /* EMC_ZCAL_WAIT_CNT after clock change */
1344                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1345                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
1346                 0x00000000, /* Mode Register 0 */
1347                 0x00010042, /* Mode Register 1 */
1348                 0x00020001, /* Mode Register 2 */
1349                 0x00000001, /* EMC_CFG.DYN_SELF_REF */
1350         },
1351         {
1352                 0x32,       /* Rev 3.2 */
1353                 533000,     /* SDRAM frequency */
1354                 {
1355                         0x0000001f, /* EMC_RC */
1356                         0x00000045, /* EMC_RFC */
1357                         0x00000016, /* EMC_RAS */
1358                         0x00000009, /* EMC_RP */
1359                         0x00000008, /* EMC_R2W */
1360                         0x00000009, /* EMC_W2R */
1361                         0x00000004, /* EMC_R2P */
1362                         0x0000000d, /* EMC_W2P */
1363                         0x00000009, /* EMC_RD_RCD */
1364                         0x00000009, /* EMC_WR_RCD */
1365                         0x00000005, /* EMC_RRD */
1366                         0x00000003, /* EMC_REXT */
1367                         0x00000000, /* EMC_WEXT */
1368                         0x00000004, /* EMC_WDV */
1369                         0x00000009, /* EMC_QUSE */
1370                         0x00000006, /* EMC_QRST */
1371                         0x0000000d, /* EMC_QSAFE */
1372                         0x00000010, /* EMC_RDV */
1373                         0x000007e1, /* EMC_REFRESH */
1374                         0x00000000, /* EMC_BURST_REFRESH_NUM */
1375                         0x000001f8, /* EMC_PRE_REFRESH_REQ_CNT */
1376                         0x00000003, /* EMC_PDEX2WR */
1377                         0x00000003, /* EMC_PDEX2RD */
1378                         0x00000009, /* EMC_PCHG2PDEN */
1379                         0x00000000, /* EMC_ACT2PDEN */
1380                         0x00000001, /* EMC_AR2PDEN */
1381                         0x0000000f, /* EMC_RW2PDEN */
1382                         0x0000004b, /* EMC_TXSR */
1383                         0x0000004b, /* EMC_TXSRDLL */
1384                         0x00000008, /* EMC_TCKE */
1385                         0x0000001b, /* EMC_TFAW */
1386                         0x0000000c, /* EMC_TRPAB */
1387                         0x00000001, /* EMC_TCLKSTABLE */
1388                         0x00000002, /* EMC_TCLKSTOP */
1389                         0x000008ab, /* EMC_TREFBW */
1390                         0x00000000, /* EMC_QUSE_EXTRA */
1391                         0x00000006, /* EMC_FBIO_CFG6 */
1392                         0x00000000, /* EMC_ODT_WRITE */
1393                         0x00000000, /* EMC_ODT_READ */
1394                         0x00006282, /* EMC_FBIO_CFG5 */
1395                         0xf0120091, /* EMC_CFG_DIG_DLL */
1396                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1397                         0x00000008, /* EMC_DLL_XFORM_DQS0 */
1398                         0x00000008, /* EMC_DLL_XFORM_DQS1 */
1399                         0x00000008, /* EMC_DLL_XFORM_DQS2 */
1400                         0x00000008, /* EMC_DLL_XFORM_DQS3 */
1401                         0x00000008, /* EMC_DLL_XFORM_DQS4 */
1402                         0x00000008, /* EMC_DLL_XFORM_DQS5 */
1403                         0x00000008, /* EMC_DLL_XFORM_DQS6 */
1404                         0x00000008, /* EMC_DLL_XFORM_DQS7 */
1405                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1406                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1407                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1408                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1409                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
1410                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
1411                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
1412                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
1413                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1414                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1415                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1416                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1417                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1418                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1419                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1420                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1421                         0x0000000c, /* EMC_DLL_XFORM_DQ0 */
1422                         0x0000000c, /* EMC_DLL_XFORM_DQ1 */
1423                         0x0000000c, /* EMC_DLL_XFORM_DQ2 */
1424                         0x0000000c, /* EMC_DLL_XFORM_DQ3 */
1425                         0x000a0220, /* EMC_XM2CMDPADCTRL */
1426                         0x0800003d, /* EMC_XM2DQSPADCTRL2 */
1427                         0x00000000, /* EMC_XM2DQPADCTRL2 */
1428                         0x77ffc004, /* EMC_XM2CLKPADCTRL */
1429                         0x01f1f408, /* EMC_XM2COMPPADCTRL */
1430                         0x00000000, /* EMC_XM2VTTGENPADCTRL */
1431                         0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
1432                         0x08000068, /* EMC_XM2QUSEPADCTRL */
1433                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
1434                         0x00000802, /* EMC_CTT_TERM_CTRL */
1435                         0x00064000, /* EMC_ZCAL_INTERVAL */
1436                         0x000000c0, /* EMC_ZCAL_WAIT_CNT */
1437                         0x000e000e, /* EMC_MRS_WAIT_CNT */
1438                         0xa0f10202, /* EMC_AUTO_CAL_CONFIG */
1439                         0x00000000, /* EMC_CTT */
1440                         0x00000000, /* EMC_CTT_DURATION */
1441                         0x800010dc, /* EMC_DYN_SELF_REF_CONTROL */
1442                         0x00000008, /* MC_EMEM_ARB_CFG */
1443                         0x80000060, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1444                         0x00000003, /* MC_EMEM_ARB_TIMING_RCD */
1445                         0x00000004, /* MC_EMEM_ARB_TIMING_RP */
1446                         0x00000010, /* MC_EMEM_ARB_TIMING_RC */
1447                         0x0000000a, /* MC_EMEM_ARB_TIMING_RAS */
1448                         0x0000000d, /* MC_EMEM_ARB_TIMING_FAW */
1449                         0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
1450                         0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1451                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1452                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
1453                         0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
1454                         0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
1455                         0x00000005, /* MC_EMEM_ARB_TIMING_W2R */
1456                         0x05040002, /* MC_EMEM_ARB_DA_TURNS */
1457                         0x00110c10, /* MC_EMEM_ARB_DA_COVERS */
1458                         0x70281811, /* MC_EMEM_ARB_MISC0 */
1459                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1460                         0xe0000000, /* EMC_FBIO_SPARE */
1461                         0xff00ff88, /* EMC_CFG_RSV */
1462                 },
1463                 0x00000030, /* EMC_ZCAL_WAIT_CNT after clock change */
1464                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1465                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
1466                 0x00000000, /* Mode Register 0 */
1467                 0x000100c2, /* Mode Register 1 */
1468                 0x00020006, /* Mode Register 2 */
1469                 0x00000000, /* EMC_CFG.DYN_SELF_REF */
1470         },
1471 };
1472
1473 int enterprise_emc_init(void)
1474 {
1475         struct board_info board_info;
1476
1477         tegra_get_board_info(&board_info);
1478
1479         if (board_info.fab <= BOARD_FAB_A02)
1480                 tegra_init_emc(enterprise_emc_tables_kmmll0_a02,
1481                                ARRAY_SIZE(enterprise_emc_tables_kmmll0_a02));
1482         else
1483                 tegra_init_emc(enterprise_emc_tables_kmkts0_a03,
1484                                ARRAY_SIZE(enterprise_emc_tables_kmkts0_a03));
1485
1486
1487         return 0;
1488 }