ARM: tegra: thermal: Cleaned up thermal framework
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA Corporation.  All rights reserved.
5  * Copyright (c) 2011-2012, NVIDIA Corporation.
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15  * more details.
16  *
17  * You should have received a copy of the GNU General Public License along
18  * with this program; if not, write to the Free Software Foundation, Inc.,
19  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
20  */
21
22 #include <linux/kernel.h>
23 #include <linux/init.h>
24 #include <linux/slab.h>
25 #include <linux/ctype.h>
26 #include <linux/platform_device.h>
27 #include <linux/clk.h>
28 #include <linux/serial_8250.h>
29 #include <linux/i2c.h>
30 #include <linux/i2c/panjit_ts.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/delay.h>
33 #include <linux/i2c-tegra.h>
34 #include <linux/gpio.h>
35 #include <linux/input.h>
36 #include <linux/platform_data/tegra_usb.h>
37 #include <linux/spi/spi.h>
38 #include <linux/i2c/atmel_mxt_ts.h>
39 #include <linux/tegra_uart.h>
40 #include <linux/memblock.h>
41 #include <linux/spi-tegra.h>
42 #include <linux/nfc/pn544.h>
43 #include <linux/rfkill-gpio.h>
44
45
46 #include <sound/wm8903.h>
47 #include <sound/max98095.h>
48 #include <media/tegra_dtv.h>
49
50 #include <asm/hardware/gic.h>
51
52 #include <mach/clk.h>
53 #include <mach/iomap.h>
54 #include <mach/irqs.h>
55 #include <mach/pinmux.h>
56 #include <mach/iomap.h>
57 #include <mach/io_dpd.h>
58 #include <mach/io.h>
59 #include <mach/i2s.h>
60 #include <mach/tegra_asoc_pdata.h>
61 #include <mach/tegra_wm8903_pdata.h>
62 #include <mach/usb_phy.h>
63 #include <mach/thermal.h>
64 #include <mach/pci.h>
65 #include <mach/gpio-tegra.h>
66 #include <mach/tegra_fiq_debugger.h>
67 #include <linux/thermal.h>
68
69 #include <asm/hardware/gic.h>
70 #include <asm/mach-types.h>
71 #include <asm/mach/arch.h>
72
73 #include "board.h"
74 #include "clock.h"
75 #include "board-cardhu.h"
76 #include "board-touch.h"
77 #include "devices.h"
78 #include "gpio-names.h"
79 #include "fuse.h"
80 #include "pm.h"
81 #include "baseband-xmm-power.h"
82 #include "wdt-recovery.h"
83 #include "common.h"
84
85 static struct balanced_throttle throttle_list[] = {
86         {
87                 .tegra_cdev = {
88                         .id = CDEV_BTHROT_ID_TJ,
89                 },
90                 .throt_tab_size = 10,
91                 .throt_tab = {
92                         {      0, 1000 },
93                         { 640000, 1000 },
94                         { 640000, 1000 },
95                         { 640000, 1000 },
96                         { 640000, 1000 },
97                         { 640000, 1000 },
98                         { 760000, 1000 },
99                         { 760000, 1050 },
100                         {1000000, 1050 },
101                         {1000000, 1100 },
102                 },
103         },
104 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
105         {
106                 .tegra_cdev = {
107                         .id = CDEV_BTHROT_ID_SKIN,
108                 },
109                 .throt_tab_size = 6,
110                 .throt_tab = {
111                         { 640000, 1200 },
112                         { 640000, 1200 },
113                         { 760000, 1200 },
114                         { 760000, 1200 },
115                         {1000000, 1200 },
116                         {1000000, 1200 },
117                 },
118         },
119 #endif
120 };
121
122 /* All units are in millicelsius */
123 static struct tegra_thermal_data thermal_data = {
124         .throttle_edp_device_id = THERMAL_DEVICE_ID_NCT_EXT,
125 #ifdef CONFIG_TEGRA_EDP_LIMITS
126         .edp_offset = TDIODE_OFFSET,  /* edp based on tdiode */
127         .hysteresis_edp = 3000,
128 #endif
129         .temp_throttle = 85000,
130         .binds = {
131                 /* Thermal Throttling */
132                 {
133                         .tdev_id = THERMAL_DEVICE_ID_NCT_EXT,
134                         .cdev_id = CDEV_BTHROT_ID_TJ,
135                         .type = THERMAL_TRIP_PASSIVE,
136                         .passive = {
137                                 .trip_temp = 85000,
138                                 .tc1 = 0,
139                                 .tc2 = 1,
140                                 .passive_delay = 2000,
141                         }
142                 },
143 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
144                 /* Skin Thermal Throttling */
145                 {
146                         .tdev_id = THERMAL_DEVICE_ID_SKIN,
147                         .cdev_id = CDEV_BTHROT_ID_SKIN,
148                         .type = THERMAL_TRIP_PASSIVE,
149                         .passive = {
150                                 .trip_temp = 43000,
151                                 .tc1 = 10,
152                                 .tc2 = 1,
153                                 .passive_delay = 15000,
154                         }
155                 },
156 #endif
157                 {
158                         .tdev_id = THERMAL_DEVICE_ID_NULL,
159                 },
160         },
161 };
162
163 static struct tegra_skin_data skin_data = {
164 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
165         .skin_device_id = THERMAL_DEVICE_ID_THERM_EST_SKIN,
166         .temp_throttle_skin = 43000,
167         .skin_temp_offset = 9793,
168         .skin_period = 1100,
169         .skin_devs_size = 2,
170         .skin_devs = {
171                 {
172                         THERMAL_DEVICE_ID_NCT_EXT,
173                         {
174                                 2, 1, 1, 1,
175                                 1, 1, 1, 1,
176                                 1, 1, 1, 0,
177                                 1, 1, 0, 0,
178                                 0, 0, -1, -7
179                         }
180                 },
181                 {
182                         THERMAL_DEVICE_ID_NCT_INT,
183                         {
184                                 -11, -7, -5, -3,
185                                 -3, -2, -1, 0,
186                                 0, 0, 1, 1,
187                                 1, 2, 2, 3,
188                                 4, 6, 11, 18
189                         }
190                 },
191         },
192 #else
193         .skin_device_id = THERMAL_DEVICE_ID_NULL,
194 #endif
195 };
196
197
198 static struct rfkill_gpio_platform_data cardhu_bt_rfkill_pdata[] = {
199         {
200                 .name           = "bt_rfkill",
201                 .shutdown_gpio  = TEGRA_GPIO_PU0,
202                 .reset_gpio     = TEGRA_GPIO_INVALID,
203                 .type           = RFKILL_TYPE_BLUETOOTH,
204         },
205 };
206
207 static struct platform_device cardhu_bt_rfkill_device = {
208         .name = "rfkill_gpio",
209         .id             = -1,
210         .dev = {
211                 .platform_data = &cardhu_bt_rfkill_pdata,
212         },
213 };
214
215 static struct resource cardhu_bluesleep_resources[] = {
216         [0] = {
217                 .name = "gpio_host_wake",
218                         .start  = TEGRA_GPIO_PU6,
219                         .end    = TEGRA_GPIO_PU6,
220                         .flags  = IORESOURCE_IO,
221         },
222         [1] = {
223                 .name = "gpio_ext_wake",
224                         .start  = TEGRA_GPIO_PU1,
225                         .end    = TEGRA_GPIO_PU1,
226                         .flags  = IORESOURCE_IO,
227         },
228         [2] = {
229                 .name = "host_wake",
230                         .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
231         },
232 };
233
234 static struct platform_device cardhu_bluesleep_device = {
235         .name           = "bluesleep",
236         .id             = -1,
237         .num_resources  = ARRAY_SIZE(cardhu_bluesleep_resources),
238         .resource       = cardhu_bluesleep_resources,
239 };
240
241 static noinline void __init cardhu_setup_bluesleep(void)
242 {
243         cardhu_bluesleep_resources[2].start =
244                 cardhu_bluesleep_resources[2].end =
245                         gpio_to_irq(TEGRA_GPIO_PU6);
246         platform_device_register(&cardhu_bluesleep_device);
247         return;
248 }
249
250 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
251         /* name         parent          rate            enabled */
252         { "pll_m",      NULL,           0,              false},
253         { "hda",        "pll_p",        108000000,      false},
254         { "hda2codec_2x","pll_p",       48000000,       false},
255         { "pwm",        "pll_p",        3187500,        false},
256         { "blink",      "clk_32k",      32768,          true},
257         { "i2s0",       "pll_a_out0",   0,              false},
258         { "i2s1",       "pll_a_out0",   0,              false},
259         { "i2s3",       "pll_a_out0",   0,              false},
260         { "spdif_out",  "pll_a_out0",   0,              false},
261         { "d_audio",    "clk_m",        12000000,       false},
262         { "dam0",       "clk_m",        12000000,       false},
263         { "dam1",       "clk_m",        12000000,       false},
264         { "dam2",       "clk_m",        12000000,       false},
265         { "audio1",     "i2s1_sync",    0,              false},
266         { "audio3",     "i2s3_sync",    0,              false},
267         { "vi_sensor",  "pll_p",        150000000,      false},
268         { "i2c1",       "pll_p",        3200000,        false},
269         { "i2c2",       "pll_p",        3200000,        false},
270         { "i2c3",       "pll_p",        3200000,        false},
271         { "i2c4",       "pll_p",        3200000,        false},
272         { "i2c5",       "pll_p",        3200000,        false},
273         { "vi",         "pll_p",        0,              false},
274         { NULL,         NULL,           0,              0},
275 };
276
277 static struct pn544_i2c_platform_data nfc_pdata = {
278         .irq_gpio = TEGRA_GPIO_PX0,
279         .ven_gpio = TEGRA_GPIO_PP3,
280         .firm_gpio = TEGRA_GPIO_PO7,
281         };
282
283 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
284         {
285                 I2C_BOARD_INFO("pn544", 0x28),
286                 .platform_data = &nfc_pdata,
287         },
288 };
289 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
290         .adapter_nr     = 0,
291         .bus_count      = 1,
292         .bus_clk_rate   = { 100000, 0 },
293         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
294         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
295         .arb_recovery = arb_lost_recovery,
296 };
297
298 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
299         .adapter_nr     = 1,
300         .bus_count      = 1,
301         .bus_clk_rate   = { 400000, 0 },
302         .is_clkon_always = true,
303         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
304         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
305         .arb_recovery = arb_lost_recovery,
306 };
307
308 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
309         .adapter_nr     = 2,
310         .bus_count      = 1,
311         .bus_clk_rate   = { 100000, 0 },
312         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
313         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
314         .arb_recovery = arb_lost_recovery,
315 };
316
317 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
318         .adapter_nr     = 3,
319         .bus_count      = 1,
320         .bus_clk_rate   = { 10000, 0 },
321         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
322         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
323         .arb_recovery = arb_lost_recovery,
324 };
325
326 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
327         .adapter_nr     = 4,
328         .bus_count      = 1,
329         .bus_clk_rate   = { 400000, 0 },
330         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
331         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
332         .arb_recovery = arb_lost_recovery,
333 };
334
335
336 #if 0
337 struct tegra_wired_jack_conf audio_wr_jack_conf = {
338         .hp_det_n = TEGRA_GPIO_PW2,
339         .en_mic_ext = TEGRA_GPIO_PX1,
340         .en_mic_int = TEGRA_GPIO_PX0,
341 };
342 #endif
343
344 static struct wm8903_platform_data cardhu_wm8903_pdata = {
345         .irq_active_low = 0,
346         .micdet_cfg = 0,
347         .micdet_delay = 100,
348         .gpio_base = CARDHU_GPIO_WM8903(0),
349         .gpio_cfg = {
350                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
351                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
352                         WM8903_GP2_DIR,
353                 WM8903_GPIO_CONFIG_ZERO,
354                 0,
355                 0,
356         },
357 };
358
359 /* Equalizer filter coefs generated from the MAXIM MAX98095
360  * evkit software tool */
361 static struct max98095_eq_cfg max98095_eq_cfg[] = {
362         {
363                 .name = "FLAT",
364                 .rate = 44100,
365                 .band1 = {0x2000, 0xC002, 0x4000, 0x00E9, 0x0000},
366                 .band2 = {0x2000, 0xC00F, 0x4000, 0x02BC, 0x0000},
367                 .band3 = {0x2000, 0xC0A7, 0x4000, 0x0916, 0x0000},
368                 .band4 = {0x2000, 0xC5C2, 0x4000, 0x1A87, 0x0000},
369                 .band5 = {0x2000, 0xF6B0, 0x4000, 0x3F51, 0x0000},
370         },
371         {
372                 .name = "LOWPASS1K",
373                 .rate = 44100,
374                 .band1 = {0x205D, 0xC001, 0x3FEF, 0x002E, 0x02E0},
375                 .band2 = {0x5B9A, 0xC093, 0x3AB2, 0x088B, 0x1981},
376                 .band3 = {0x0D22, 0xC170, 0x26EA, 0x0D79, 0x32CF},
377                 .band4 = {0x0894, 0xC612, 0x01B3, 0x1B34, 0x3FFA},
378                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
379         },
380         { /* BASS=-12dB, TREBLE=+9dB, Fc=5KHz */
381                 .name = "HIBOOST",
382                 .rate = 44100,
383                 .band1 = {0x0815, 0xC001, 0x3AA4, 0x0003, 0x19A2},
384                 .band2 = {0x0815, 0xC103, 0x092F, 0x0B55, 0x3F56},
385                 .band3 = {0x0E0A, 0xC306, 0x1E5C, 0x136E, 0x3856},
386                 .band4 = {0x2459, 0xF665, 0x0CAA, 0x3F46, 0x3EBB},
387                 .band5 = {0x5BBB, 0x3FFF, 0xCEB0, 0x0000, 0x28CA},
388         },
389         { /* BASS=12dB, TREBLE=+12dB */
390                 .name = "LOUD12DB",
391                 .rate = 44100,
392                 .band1 = {0x7FC1, 0xC001, 0x3EE8, 0x0020, 0x0BC7},
393                 .band2 = {0x51E9, 0xC016, 0x3C7C, 0x033F, 0x14E9},
394                 .band3 = {0x1745, 0xC12C, 0x1680, 0x0C2F, 0x3BE9},
395                 .band4 = {0x4536, 0xD7E2, 0x0ED4, 0x31DD, 0x3E42},
396                 .band5 = {0x7FEF, 0x3FFF, 0x0BAB, 0x0000, 0x3EED},
397         },
398         {
399                 .name = "FLAT",
400                 .rate = 16000,
401                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
402                 .band2 = {0x2000, 0xC033, 0x4000, 0x0505, 0x0000},
403                 .band3 = {0x2000, 0xC268, 0x4000, 0x115F, 0x0000},
404                 .band4 = {0x2000, 0xDA62, 0x4000, 0x33C6, 0x0000},
405                 .band5 = {0x2000, 0x4000, 0x4000, 0x0000, 0x0000},
406         },
407         {
408                 .name = "LOWPASS1K",
409                 .rate = 16000,
410                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
411                 .band2 = {0x5BE8, 0xC3E0, 0x3307, 0x15ED, 0x26A0},
412                 .band3 = {0x0F71, 0xD15A, 0x08B3, 0x2BD0, 0x3F67},
413                 .band4 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
414                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
415         },
416         { /* BASS=-12dB, TREBLE=+9dB, Fc=2KHz */
417                 .name = "HIBOOST",
418                 .rate = 16000,
419                 .band1 = {0x0815, 0xC001, 0x3BD2, 0x0009, 0x16BF},
420                 .band2 = {0x080E, 0xC17E, 0xF653, 0x0DBD, 0x3F43},
421                 .band3 = {0x0F80, 0xDF45, 0xEE33, 0x36FE, 0x3D79},
422                 .band4 = {0x590B, 0x3FF0, 0xE882, 0x02BD, 0x3B87},
423                 .band5 = {0x4C87, 0xF3D0, 0x063F, 0x3ED4, 0x3FB1},
424         },
425         { /* BASS=12dB, TREBLE=+12dB */
426                 .name = "LOUD12DB",
427                 .rate = 16000,
428                 .band1 = {0x7FC1, 0xC001, 0x3D07, 0x0058, 0x1344},
429                 .band2 = {0x2DA6, 0xC013, 0x3CF1, 0x02FF, 0x138B},
430                 .band3 = {0x18F1, 0xC08E, 0x244D, 0x0863, 0x34B5},
431                 .band4 = {0x2BE0, 0xF385, 0x04FD, 0x3EC5, 0x3FCE},
432                 .band5 = {0x7FEF, 0x4000, 0x0BAB, 0x0000, 0x3EED},
433         },
434 };
435
436 static struct max98095_pdata cardhu_max98095_pdata = {
437         /* equalizer configuration */
438         .eq_cfg = max98095_eq_cfg,
439         .eq_cfgcnt = ARRAY_SIZE(max98095_eq_cfg),
440
441         /* Biquad filter response configuration */
442         .bq_cfg = NULL,
443         .bq_cfgcnt = 0,
444
445         /* microphone configuration */
446         .digmic_left_mode = 1,
447         .digmic_right_mode = 1,
448 };
449
450 static struct i2c_board_info __initdata cardhu_codec_wm8903_info = {
451         I2C_BOARD_INFO("wm8903", 0x1a),
452         .platform_data = &cardhu_wm8903_pdata,
453 };
454
455 static struct i2c_board_info __initdata cardhu_codec_aic326x_info = {
456         I2C_BOARD_INFO("aic3262-codec", 0x18),
457 };
458
459 static struct i2c_board_info __initdata cardhu_codec_max98095_info = {
460         I2C_BOARD_INFO("max98095", 0x10),
461         .platform_data = &cardhu_max98095_pdata,
462 };
463
464 static void cardhu_i2c_init(void)
465 {
466         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
467         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
468         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
469         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
470         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
471
472         platform_device_register(&tegra_i2c_device5);
473         platform_device_register(&tegra_i2c_device4);
474         platform_device_register(&tegra_i2c_device3);
475         platform_device_register(&tegra_i2c_device2);
476         platform_device_register(&tegra_i2c_device1);
477
478         cardhu_codec_wm8903_info.irq = cardhu_codec_max98095_info.irq =
479                 cardhu_codec_aic326x_info.irq = gpio_to_irq(TEGRA_GPIO_CDC_IRQ);
480         i2c_register_board_info(4, &cardhu_codec_wm8903_info, 1);
481         i2c_register_board_info(4, &cardhu_codec_max98095_info, 1);
482         i2c_register_board_info(4, &cardhu_codec_aic326x_info, 1);
483
484         cardhu_i2c_bus3_board_info[0].irq = gpio_to_irq(TEGRA_GPIO_PX0);
485         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
486 }
487
488 static struct platform_device *cardhu_uart_devices[] __initdata = {
489         &tegra_uarta_device,
490         &tegra_uartb_device,
491         &tegra_uartc_device,
492         &tegra_uartd_device,
493         &tegra_uarte_device,
494 };
495 static struct uart_clk_parent uart_parent_clk[] = {
496         [0] = {.name = "clk_m"},
497         [1] = {.name = "pll_p"},
498 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
499         [2] = {.name = "pll_m"},
500 #endif
501 };
502
503 static struct tegra_uart_platform_data cardhu_uart_pdata;
504 static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
505
506 static void __init uart_debug_init(void)
507 {
508         struct board_info board_info;
509         int debug_port_id;
510
511         tegra_get_board_info(&board_info);
512
513         debug_port_id = get_tegra_uart_debug_port_id();
514         if (debug_port_id < 0) {
515                 debug_port_id = 0;
516                         /* UARTB is debug port
517                          *       for SLT - E1186/E1187/PM269
518                          *       for E1256/E1257
519                          */
520                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
521                         ((board_info.board_id == BOARD_E1186) ||
522                         (board_info.board_id == BOARD_E1187) ||
523                         (board_info.board_id == BOARD_PM269))) ||
524                         (board_info.board_id == BOARD_E1256) ||
525                         (board_info.board_id == BOARD_E1257))
526                                 debug_port_id = 1;
527         }
528
529 #ifdef CONFIG_TEGRA_IRDA
530         if ((board_info.board_id == BOARD_E1186) ||
531                 (board_info.board_id == BOARD_E1198)) {
532                 if (debug_port_id == 1) {
533                         cardhu_irda_pdata.is_irda = false;
534                         pr_err("UARTB is not available for IrDA\n");
535                 }
536         }
537 #endif
538
539         switch (debug_port_id) {
540         case 0:
541                 /* UARTA is the debug port. */
542                 pr_info("Selecting UARTA as the debug console\n");
543                 cardhu_uart_devices[0] = &debug_uarta_device;
544                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
545                 debug_uart_port_base = ((struct plat_serial8250_port *)(
546                         debug_uarta_device.dev.platform_data))->mapbase;
547                 break;
548
549         case 1:
550                 /* UARTB is the debug port. */
551                 pr_info("Selecting UARTB as the debug console\n");
552                 cardhu_uart_devices[1] = &debug_uartb_device;
553                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
554                 debug_uart_port_base = ((struct plat_serial8250_port *)(
555                         debug_uartb_device.dev.platform_data))->mapbase;
556                 break;
557
558         case 2:
559                 /* UARTC is the debug port. */
560                 pr_info("Selecting UARTC as the debug console\n");
561                 cardhu_uart_devices[2] = &debug_uartc_device;
562                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
563                 debug_uart_port_base = ((struct plat_serial8250_port *)(
564                         debug_uartc_device.dev.platform_data))->mapbase;
565                 break;
566
567         case 3:
568                 /* UARTD is the debug port. */
569                 pr_info("Selecting UARTD as the debug console\n");
570                 cardhu_uart_devices[3] = &debug_uartd_device;
571                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
572                 debug_uart_port_base = ((struct plat_serial8250_port *)(
573                         debug_uartd_device.dev.platform_data))->mapbase;
574                 break;
575
576         case 4:
577                 /* UARTE is the debug port. */
578                 pr_info("Selecting UARTE as the debug console\n");
579                 cardhu_uart_devices[4] = &debug_uarte_device;
580                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
581                 debug_uart_port_base = ((struct plat_serial8250_port *)(
582                         debug_uarte_device.dev.platform_data))->mapbase;
583                 break;
584
585         default:
586                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
587                 cardhu_uart_devices[0] = &debug_uarta_device;
588                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
589                 debug_uart_port_base = ((struct plat_serial8250_port *)(
590                         debug_uarta_device.dev.platform_data))->mapbase;
591                 break;
592         }
593         return;
594 }
595
596 static void __init cardhu_uart_init(void)
597 {
598         struct clk *c;
599         int i;
600         struct board_info board_info;
601
602         tegra_get_board_info(&board_info);
603
604         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
605                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
606                 if (IS_ERR_OR_NULL(c)) {
607                         pr_err("Not able to get the clock for %s\n",
608                                                 uart_parent_clk[i].name);
609                         continue;
610                 }
611                 uart_parent_clk[i].parent_clk = c;
612                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
613         }
614         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
615         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
616         cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
617         cardhu_loopback_uart_pdata.parent_clk_count =
618                                                 ARRAY_SIZE(uart_parent_clk);
619         cardhu_loopback_uart_pdata.is_loopback = true;
620         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
621         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
622         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
623         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
624         /* UARTE is used for loopback test purpose */
625         tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
626
627         /* Register low speed only if it is selected */
628         if (!is_tegra_debug_uartport_hs()) {
629                 uart_debug_init();
630                 /* Clock enable for the debug channel */
631                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
632                         pr_info("The debug console clock name is %s\n",
633                                                 debug_uart_clk->name);
634                         c = tegra_get_clock_by_name("pll_p");
635                         if (IS_ERR_OR_NULL(c))
636                                 pr_err("Not getting the parent clock pll_p\n");
637                         else
638                                 clk_set_parent(debug_uart_clk, c);
639
640                         clk_enable(debug_uart_clk);
641                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
642                 } else {
643                         pr_err("Not getting the clock %s for debug console\n",
644                                         debug_uart_clk->name);
645                 }
646         }
647
648 #ifdef CONFIG_TEGRA_IRDA
649         if (((board_info.board_id == BOARD_E1186) ||
650                 (board_info.board_id == BOARD_E1198)) &&
651                         cardhu_irda_pdata.is_irda) {
652                 cardhu_irda_pdata.parent_clk_list = uart_parent_clk;
653                 cardhu_irda_pdata.parent_clk_count =
654                                         ARRAY_SIZE(uart_parent_clk);
655
656                 tegra_uartb_device.dev.platform_data = &cardhu_irda_pdata;
657         }
658 #endif
659
660         platform_add_devices(cardhu_uart_devices,
661                                 ARRAY_SIZE(cardhu_uart_devices));
662 }
663
664 static struct platform_device tegra_camera = {
665         .name = "tegra_camera",
666         .id = -1,
667 };
668
669 static struct platform_device *cardhu_spi_devices[] __initdata = {
670         &tegra_spi_device4,
671 };
672
673 static struct platform_device *touch_spi_device[] __initdata = {
674         &tegra_spi_device1,
675 };
676
677 struct spi_clk_parent spi_parent_clk[] = {
678         [0] = {.name = "pll_p"},
679 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
680         [1] = {.name = "pll_m"},
681         [2] = {.name = "clk_m"},
682 #else
683         [1] = {.name = "clk_m"},
684 #endif
685 };
686
687 static struct tegra_spi_platform_data cardhu_spi_pdata = {
688         .is_dma_based           = true,
689         .max_dma_buffer         = (16 * 1024),
690         .is_clkon_always        = false,
691         .max_rate               = 100000000,
692 };
693
694 static void __init cardhu_spi_init(void)
695 {
696         int i;
697         struct clk *c;
698         struct board_info board_info, display_board_info;
699
700         tegra_get_board_info(&board_info);
701         tegra_get_display_board_info(&display_board_info);
702
703         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
704                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
705                 if (IS_ERR_OR_NULL(c)) {
706                         pr_err("Not able to get the clock for %s\n",
707                                                 spi_parent_clk[i].name);
708                         continue;
709                 }
710                 spi_parent_clk[i].parent_clk = c;
711                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
712         }
713         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
714         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
715         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
716         platform_add_devices(cardhu_spi_devices,
717                                 ARRAY_SIZE(cardhu_spi_devices));
718
719         if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
720                 platform_add_devices(touch_spi_device,
721                                 ARRAY_SIZE(touch_spi_device));
722         }
723         if (board_info.board_id == BOARD_E1198) {
724                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
725                 platform_device_register(&tegra_spi_device2);
726                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
727                 platform_device_register(&tegra_spi_slave_device1);
728         }
729 }
730
731 static void __init cardhu_dtv_init(void)
732 {
733         struct board_info board_info;
734
735         tegra_get_board_info(&board_info);
736
737         if (board_info.board_id == BOARD_E1186)
738                 platform_device_register(&tegra_dtv_device);
739 }
740
741 static struct resource tegra_rtc_resources[] = {
742         [0] = {
743                 .start = TEGRA_RTC_BASE,
744                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
745                 .flags = IORESOURCE_MEM,
746         },
747         [1] = {
748                 .start = INT_RTC,
749                 .end = INT_RTC,
750                 .flags = IORESOURCE_IRQ,
751         },
752 };
753
754 static struct platform_device tegra_rtc_device = {
755         .name = "tegra_rtc",
756         .id   = -1,
757         .resource = tegra_rtc_resources,
758         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
759 };
760
761 static struct tegra_asoc_platform_data cardhu_audio_wm8903_pdata = {
762         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
763         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
764         .gpio_hp_mute           = -1,
765         .gpio_int_mic_en        = -1,
766         .gpio_ext_mic_en        = -1,
767         .i2s_param[HIFI_CODEC]  = {
768                 .audio_port_id  = 0,
769                 .is_i2s_master  = 1,
770                 .i2s_mode       = TEGRA_DAIFMT_I2S,
771         },
772         .i2s_param[BASEBAND]    = {
773                 .audio_port_id  = -1,
774         },
775         .i2s_param[BT_SCO]      = {
776                 .audio_port_id  = 3,
777                 .is_i2s_master  = 1,
778                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
779         },
780 };
781
782 static struct tegra_asoc_platform_data cardhu_audio_max98095_pdata = {
783         .gpio_spkr_en           = -1,
784         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
785         .gpio_hp_mute           = -1,
786         .gpio_int_mic_en        = -1,
787         .gpio_ext_mic_en        = -1,
788         .i2s_param[HIFI_CODEC]  = {
789                 .audio_port_id  = 0,
790                 .is_i2s_master  = 1,
791                 .i2s_mode       = TEGRA_DAIFMT_I2S,
792         },
793         .i2s_param[BASEBAND]    = {
794                 .audio_port_id  = -1,
795         },
796         .i2s_param[BT_SCO]      = {
797                 .audio_port_id  = 3,
798                 .is_i2s_master  = 1,
799                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
800         },
801 };
802
803 static struct platform_device cardhu_audio_wm8903_device = {
804         .name   = "tegra-snd-wm8903",
805         .id     = 0,
806         .dev    = {
807                 .platform_data = &cardhu_audio_wm8903_pdata,
808         },
809 };
810
811 static struct platform_device cardhu_audio_max98095_device = {
812         .name   = "tegra-snd-max98095",
813         .id     = 0,
814         .dev    = {
815                 .platform_data = &cardhu_audio_max98095_pdata,
816         },
817 };
818
819 static struct tegra_asoc_platform_data cardhu_audio_aic326x_pdata = {
820         .gpio_spkr_en           = -1,
821         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
822         .gpio_hp_mute           = -1,
823         .gpio_int_mic_en        = -1,
824         .gpio_ext_mic_en        = -1,
825         /*defaults for Verbier-Cardhu board with TI AIC326X codec*/
826         .i2s_param[HIFI_CODEC]  = {
827                 .audio_port_id  = 0,
828                 .is_i2s_master  = 1,
829                 .i2s_mode       = TEGRA_DAIFMT_I2S,
830                 .sample_size    = 16,
831         },
832         .i2s_param[BT_SCO]      = {
833                 .sample_size    = 16,
834                 .audio_port_id  = 3,
835                 .is_i2s_master  = 1,
836                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
837         },
838 };
839
840 static struct platform_device cardhu_audio_aic326x_device = {
841         .name   = "tegra-snd-aic326x",
842         .id     = 0,
843         .dev    = {
844                 .platform_data  = &cardhu_audio_aic326x_pdata,
845         },
846 };
847
848 static struct platform_device *cardhu_devices[] __initdata = {
849         &tegra_pmu_device,
850         &tegra_rtc_device,
851         &tegra_udc_device,
852         &tegra_wdt0_device,
853         &tegra_wdt1_device,
854         &tegra_wdt2_device,
855 #if defined(CONFIG_TEGRA_AVP)
856         &tegra_avp_device,
857 #endif
858         &tegra_camera,
859 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
860         &tegra_se_device,
861 #endif
862         &tegra_ahub_device,
863         &tegra_dam_device0,
864         &tegra_dam_device1,
865         &tegra_dam_device2,
866         &tegra_i2s_device0,
867         &tegra_i2s_device1,
868         &tegra_i2s_device3,
869         &tegra_spdif_device,
870         &spdif_dit_device,
871         &bluetooth_dit_device,
872         &baseband_dit_device,
873         &cardhu_bt_rfkill_device,
874         &tegra_pcm_device,
875         &cardhu_audio_wm8903_device,
876         &cardhu_audio_max98095_device,
877         &cardhu_audio_aic326x_device,
878         &tegra_hda_device,
879         &tegra_cec_device,
880 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
881         &tegra_aes_device,
882 #endif
883 };
884
885 #define E1506_MXT_CONFIG_CRC 0x62F903
886 static const u8 e1506_config[] = {
887         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
888         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x05, 0x01, 0x00,
889         0x00, 0x1E, 0x0A, 0x8B, 0x00, 0x00, 0x13, 0x0B,
890         0x00, 0x10, 0x32, 0x03, 0x03, 0x00, 0x03, 0x01,
891         0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xBF, 0x03, 0x1B,
892         0x02, 0x00, 0x00, 0x37, 0x37, 0x00, 0x00, 0x00,
893         0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
894         0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
895         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
896         0x00, 0x00, 0x00, 0xA9, 0x7F, 0x9A, 0x0E, 0x00,
897         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
898         0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00,
899         0x00, 0x00, 0x03, 0x23, 0x00, 0x00, 0x00, 0x0A,
900         0x0F, 0x14, 0x19, 0x03, 0x00, 0x00, 0x00, 0x00,
901         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
902         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
903         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
904         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
905         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
906         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
907         0x00, 0x00, 0x00, 0x01, 0x00, 0x03, 0x08, 0x10,
908         0x00
909 };
910
911 #define MXT_CONFIG_CRC  0xD62DE8
912 static const u8 config[] = {
913         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
914         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
915         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
916         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
917         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
918         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
919         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
920         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
921         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
922         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
923         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
924         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
925         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
926         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
927         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
928         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
929         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
930         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
931         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
932         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
933 };
934
935 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
936 static const u8 config_sku2000[] = {
937         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
938         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
939         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
940         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
941         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
942         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
943         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
944         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
945         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
946         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
947         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
948         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
949         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
950         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
951         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
952         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
953         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
954         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
955         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
956         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
957 };
958
959 static struct mxt_platform_data atmel_mxt_info = {
960         .x_line         = 27,
961         .y_line         = 42,
962         .x_size         = 768,
963         .y_size         = 1366,
964         .blen           = 0x20,
965         .threshold      = 0x3C,
966         .voltage        = 3300000,              /* 3.3V */
967         .orient         = 5,
968         .config         = config,
969         .config_length  = 157,
970         .config_crc     = MXT_CONFIG_CRC,
971         .irqflags       = IRQF_TRIGGER_FALLING,
972 /*      .read_chg       = &read_chg, */
973         .read_chg       = NULL,
974 };
975
976 static struct mxt_platform_data e1506_atmel_mxt_info = {
977         .x_line         = 19,
978         .y_line         = 11,
979         .x_size         = 960,
980         .y_size         = 540,
981         .blen           = 0x10,
982         .threshold      = 0x32,
983         .voltage        = 3300000,              /* 3.3V */
984         .orient         = 3,
985         .config         = e1506_config,
986         .config_length  = 168,
987         .config_crc     = E1506_MXT_CONFIG_CRC,
988         .irqflags       = IRQF_TRIGGER_FALLING,
989 /*      .read_chg       = &read_chg, */
990         .read_chg       = NULL,
991 };
992
993 static struct i2c_board_info __initdata atmel_i2c_info[] = {
994         {
995                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
996                 .platform_data = &atmel_mxt_info,
997         }
998 };
999
1000 static struct i2c_board_info __initdata e1506_atmel_i2c_info[] = {
1001         {
1002                 I2C_BOARD_INFO("atmel_mxt_ts", 0x4A),
1003                 .platform_data = &e1506_atmel_mxt_info,
1004         }
1005 };
1006
1007 static __initdata struct tegra_clk_init_table spi_clk_init_table[] = {
1008         /* name         parent          rate            enabled */
1009         { "sbc1",       "pll_p",        52000000,       true},
1010         { NULL,         NULL,           0,              0},
1011 };
1012
1013 static int __init cardhu_touch_init(void)
1014 {
1015         struct board_info BoardInfo, DisplayBoardInfo;
1016
1017         tegra_get_board_info(&BoardInfo);
1018         tegra_get_display_board_info(&DisplayBoardInfo);
1019         if (DisplayBoardInfo.board_id == BOARD_DISPLAY_PM313) {
1020                 tegra_clk_init_from_table(spi_clk_init_table);
1021
1022                 touch_init_raydium(TEGRA_GPIO_PH4, TEGRA_GPIO_PH6, 2);
1023         } else {
1024                 gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
1025                 gpio_direction_input(TEGRA_GPIO_PH4);
1026
1027                 gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
1028                 gpio_direction_output(TEGRA_GPIO_PH6, 0);
1029                 msleep(1);
1030                 gpio_set_value(TEGRA_GPIO_PH6, 1);
1031                 msleep(100);
1032
1033                 if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
1034                         atmel_mxt_info.config = config_sku2000;
1035                         atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
1036                 }
1037
1038                 if (DisplayBoardInfo.board_id == BOARD_DISPLAY_E1506) {
1039                         e1506_atmel_i2c_info[0].irq = gpio_to_irq(TEGRA_GPIO_PH4);
1040                         i2c_register_board_info(1, e1506_atmel_i2c_info, 1);
1041                 } else {
1042                         atmel_i2c_info[0].irq = gpio_to_irq(TEGRA_GPIO_PH4);
1043                         i2c_register_board_info(1, atmel_i2c_info, 1);
1044                 }
1045         }
1046
1047         return 0;
1048 }
1049
1050 #if defined(CONFIG_USB_SUPPORT)
1051
1052 static void cardu_usb_hsic_postsupend(void)
1053 {
1054 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1055         baseband_xmm_set_power_status(BBXMM_PS_L2);
1056 #endif
1057 }
1058
1059 static void cardu_usb_hsic_preresume(void)
1060 {
1061 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1062         baseband_xmm_set_power_status(BBXMM_PS_L2TOL0);
1063 #endif
1064 }
1065
1066 static void cardu_usb_hsic_phy_ready(void)
1067 {
1068 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1069         baseband_xmm_set_power_status(BBXMM_PS_L0);
1070 #endif
1071 }
1072
1073 static void cardu_usb_hsic_phy_off(void)
1074 {
1075 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1076         baseband_xmm_set_power_status(BBXMM_PS_L3);
1077 #endif
1078 }
1079
1080 static struct tegra_usb_phy_platform_ops hsic_xmm_plat_ops = {
1081         .post_suspend = cardu_usb_hsic_postsupend,
1082         .pre_resume = cardu_usb_hsic_preresume,
1083         .port_power = cardu_usb_hsic_phy_ready,
1084         .post_phy_off = cardu_usb_hsic_phy_off,
1085 };
1086
1087 static struct tegra_usb_platform_data tegra_ehci2_hsic_xmm_pdata = {
1088         .port_otg = false,
1089         .has_hostpc = true,
1090         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1091         .op_mode        = TEGRA_USB_OPMODE_HOST,
1092         .u_data.host = {
1093                 .vbus_gpio = -1,
1094                 .hot_plug = false,
1095                 .remote_wakeup_supported = false,
1096                 .power_off_on_suspend = false,
1097         },
1098         .ops = &hsic_xmm_plat_ops,
1099 };
1100 #endif
1101
1102 static int hsic_enable_gpio = -1;
1103 static int hsic_reset_gpio = -1;
1104
1105 void hsic_platform_open(void)
1106 {
1107         int reset_gpio = 0, enable_gpio = 0;
1108
1109         if (hsic_enable_gpio != -1)
1110                 enable_gpio = gpio_request(hsic_enable_gpio, "uhsic_enable");
1111         if (hsic_reset_gpio != -1)
1112                 reset_gpio = gpio_request(hsic_reset_gpio, "uhsic_reset");
1113         /* hsic enable signal deasserted, hsic reset asserted */
1114         if (!enable_gpio)
1115                 gpio_direction_output(hsic_enable_gpio, 0 /* deasserted */);
1116         if (!reset_gpio)
1117                 gpio_direction_output(hsic_reset_gpio, 0 /* asserted */);
1118         /* keep hsic reset asserted for 1 ms */
1119         udelay(1000);
1120         /* enable (power on) hsic */
1121         if (!enable_gpio)
1122                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
1123         udelay(1000);
1124         /* deassert reset */
1125         if (!reset_gpio)
1126                 gpio_set_value_cansleep(hsic_reset_gpio, 1);
1127
1128 }
1129
1130 void hsic_platform_close(void)
1131 {
1132         if (hsic_enable_gpio != -1) {
1133                 gpio_set_value(hsic_enable_gpio, 0);
1134                 gpio_free(hsic_enable_gpio);
1135         }
1136         if (hsic_reset_gpio != -1) {
1137                 gpio_set_value(hsic_reset_gpio, 0);
1138                 gpio_free(hsic_reset_gpio);
1139         }
1140 }
1141
1142 void hsic_power_on(void)
1143 {
1144         if (hsic_enable_gpio != -1) {
1145                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
1146                 udelay(1000);
1147         }
1148 }
1149
1150 void hsic_power_off(void)
1151 {
1152         if (hsic_enable_gpio != -1) {
1153                 gpio_set_value_cansleep(hsic_enable_gpio, 0);
1154                 udelay(1000);
1155         }
1156 }
1157
1158 #if defined(CONFIG_USB_SUPPORT)
1159 static struct tegra_usb_phy_platform_ops hsic_plat_ops = {
1160         .open = hsic_platform_open,
1161         .close = hsic_platform_close,
1162         .pre_phy_on = hsic_power_on,
1163         .post_phy_off = hsic_power_off,
1164 };
1165
1166 static struct tegra_usb_platform_data tegra_ehci2_hsic_pdata = {
1167         .port_otg = false,
1168         .has_hostpc = true,
1169         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1170         .op_mode        = TEGRA_USB_OPMODE_HOST,
1171         .u_data.host = {
1172                 .vbus_gpio = -1,
1173                 .hot_plug = false,
1174                 .remote_wakeup_supported = false,
1175                 .power_off_on_suspend = false,
1176         },
1177         .ops = &hsic_plat_ops,
1178 };
1179
1180 static struct tegra_usb_platform_data tegra_udc_pdata = {
1181         .port_otg = true,
1182         .has_hostpc = true,
1183         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1184         .op_mode = TEGRA_USB_OPMODE_DEVICE,
1185         .u_data.dev = {
1186                 .vbus_pmu_irq = 0,
1187                 .vbus_gpio = -1,
1188                 .charging_supported = false,
1189                 .remote_wakeup_supported = false,
1190         },
1191         .u_cfg.utmi = {
1192                 .hssync_start_delay = 0,
1193                 .elastic_limit = 16,
1194                 .idle_wait_delay = 17,
1195                 .term_range_adj = 6,
1196                 .xcvr_setup = 8,
1197                 .xcvr_lsfslew = 2,
1198                 .xcvr_lsrslew = 2,
1199                 .xcvr_setup_offset = 0,
1200                 .xcvr_use_fuses = 1,
1201         },
1202 };
1203
1204 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
1205         .port_otg = false,
1206         .has_hostpc = true,
1207         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1208         .op_mode        = TEGRA_USB_OPMODE_HOST,
1209         .u_data.host = {
1210                 .vbus_gpio = -1,
1211                 .hot_plug = false,
1212                 .remote_wakeup_supported = true,
1213                 .power_off_on_suspend = true,
1214         },
1215         .u_cfg.utmi = {
1216                 .hssync_start_delay = 0,
1217                 .elastic_limit = 16,
1218                 .idle_wait_delay = 17,
1219                 .term_range_adj = 6,
1220                 .xcvr_setup = 15,
1221                 .xcvr_lsfslew = 2,
1222                 .xcvr_lsrslew = 2,
1223                 .xcvr_setup_offset = 0,
1224                 .xcvr_use_fuses = 1,
1225         },
1226 };
1227
1228 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
1229         .port_otg = false,
1230         .has_hostpc = true,
1231         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1232         .op_mode = TEGRA_USB_OPMODE_HOST,
1233         .u_data.host = {
1234                 .vbus_gpio = -1,
1235                 .vbus_reg = "vdd_vbus_typea_usb",
1236                 .hot_plug = true,
1237                 .remote_wakeup_supported = true,
1238                 .power_off_on_suspend = true,
1239         },
1240         .u_cfg.utmi = {
1241                 .hssync_start_delay = 0,
1242                 .elastic_limit = 16,
1243                 .idle_wait_delay = 17,
1244                 .term_range_adj = 6,
1245                 .xcvr_setup = 8,
1246                 .xcvr_lsfslew = 2,
1247                 .xcvr_lsrslew = 2,
1248                 .xcvr_setup_offset = 0,
1249                 .xcvr_use_fuses = 1,
1250         },
1251 };
1252
1253 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
1254         .port_otg = true,
1255         .has_hostpc = true,
1256         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1257         .op_mode = TEGRA_USB_OPMODE_HOST,
1258         .u_data.host = {
1259                 .vbus_gpio = -1,
1260                 .vbus_reg = "vdd_vbus_micro_usb",
1261                 .hot_plug = true,
1262                 .remote_wakeup_supported = true,
1263                 .power_off_on_suspend = true,
1264         },
1265         .u_cfg.utmi = {
1266                 .hssync_start_delay = 0,
1267                 .elastic_limit = 16,
1268                 .idle_wait_delay = 17,
1269                 .term_range_adj = 6,
1270                 .xcvr_setup = 15,
1271                 .xcvr_lsfslew = 2,
1272                 .xcvr_lsrslew = 2,
1273                 .xcvr_setup_offset = 0,
1274                 .xcvr_use_fuses = 1,
1275         },
1276 };
1277
1278 static struct tegra_usb_otg_data tegra_otg_pdata = {
1279         .ehci_device = &tegra_ehci1_device,
1280         .ehci_pdata = &tegra_ehci1_utmi_pdata,
1281 };
1282 #endif
1283
1284 #if defined(CONFIG_USB_SUPPORT)
1285 static void cardhu_usb_init(void)
1286 {
1287         struct board_info bi;
1288
1289         tegra_get_board_info(&bi);
1290
1291         /* OTG should be the first to be registered */
1292         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
1293         platform_device_register(&tegra_otg_device);
1294
1295         /* setup the udc platform data */
1296         tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
1297
1298         if (bi.board_id == BOARD_PM267) {
1299                 hsic_enable_gpio = EN_HSIC_GPIO;
1300                 hsic_reset_gpio = PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
1301                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1302                 platform_device_register(&tegra_ehci2_device);
1303         } else if (bi.board_id == BOARD_E1256) {
1304                 hsic_enable_gpio = EN_HSIC_GPIO;
1305                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1306                 platform_device_register(&tegra_ehci2_device);
1307         } else if (bi.board_id == BOARD_E1186) {
1308                 tegra_ehci2_device.dev.platform_data =
1309                                                 &tegra_ehci2_hsic_xmm_pdata;
1310                 /* ehci2 registration happens in baseband-xmm-power  */
1311         } else {
1312                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata;
1313                 platform_device_register(&tegra_ehci2_device);
1314         }
1315
1316         tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
1317         platform_device_register(&tegra_ehci3_device);
1318
1319 }
1320 #else
1321 static void cardhu_usb_init(void) { }
1322 #endif
1323
1324 static struct baseband_power_platform_data tegra_baseband_power_data = {
1325         .baseband_type = BASEBAND_XMM,
1326         .modem = {
1327         .xmm = {
1328                         .bb_rst = XMM_GPIO_BB_RST,
1329                         .bb_on = XMM_GPIO_BB_ON,
1330                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
1331                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
1332                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
1333                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
1334                         .hsic_device = &tegra_ehci2_device,
1335                 },
1336         },
1337 };
1338
1339 static struct platform_device tegra_baseband_power_device = {
1340         .name = "baseband_xmm_power",
1341         .id = -1,
1342         .dev = {
1343                 .platform_data = &tegra_baseband_power_data,
1344         },
1345 };
1346
1347 static struct platform_device tegra_baseband_power2_device = {
1348         .name = "baseband_xmm_power2",
1349         .id = -1,
1350         .dev = {
1351                 .platform_data = &tegra_baseband_power_data,
1352         },
1353 };
1354
1355
1356 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
1357         .port_status[0] = 1,
1358         .port_status[1] = 1,
1359         .port_status[2] = 1,
1360         .use_dock_detect        = 0,
1361         .gpio           = 0,
1362 };
1363
1364 static void cardhu_pci_init(void)
1365 {
1366         struct board_info board_info;
1367
1368         tegra_get_board_info(&board_info);
1369         if (board_info.board_id == BOARD_E1291) {
1370                 cardhu_pci_platform_data.port_status[0] = 0;
1371                 cardhu_pci_platform_data.port_status[1] = 0;
1372                 cardhu_pci_platform_data.port_status[2] = 1;
1373                 cardhu_pci_platform_data.use_dock_detect = 1;
1374                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
1375         }
1376         if ((board_info.board_id == BOARD_E1186) ||
1377                 (board_info.board_id == BOARD_E1187) ||
1378                 (board_info.board_id == BOARD_E1291)) {
1379                 tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
1380                 platform_device_register(&tegra_pci_device);
1381         }
1382 }
1383
1384 static void cardhu_modem_init(void)
1385 {
1386         struct board_info board_info;
1387         int w_disable_gpio, ret;
1388
1389         tegra_get_board_info(&board_info);
1390         switch (board_info.board_id) {
1391         case BOARD_E1291:
1392         case BOARD_E1198:
1393                 if (((board_info.board_id == BOARD_E1291) &&
1394                                 (board_info.fab < BOARD_FAB_A03)) ||
1395                         ((board_info.board_id == BOARD_E1198) &&
1396                                         (board_info.fab < BOARD_FAB_A02))) {
1397                         w_disable_gpio = TEGRA_GPIO_PH5;
1398                 } else {
1399                         w_disable_gpio = TEGRA_GPIO_PDD5;
1400                 }
1401
1402                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
1403                 if (ret < 0)
1404                         pr_err("%s: gpio_request failed for gpio %d\n",
1405                                 __func__, w_disable_gpio);
1406                 else
1407                         gpio_direction_input(w_disable_gpio);
1408
1409                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
1410                 if (((board_info.board_id == BOARD_E1291) &&
1411                                 (board_info.fab >= BOARD_FAB_A04)) ||
1412                         ((board_info.board_id == BOARD_E1198) &&
1413                                         (board_info.fab >= BOARD_FAB_A02))) {
1414                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
1415                         if (ret < 0) {
1416                                 pr_err("%s(): Error in allocating gpio "
1417                                         "TEGRA_GPIO_PH7\n", __func__);
1418                                 break;
1419                         }
1420                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
1421                 }
1422                 break;
1423         case BOARD_E1186:
1424                 platform_device_register(&tegra_baseband_power_device);
1425                 platform_device_register(&tegra_baseband_power2_device);
1426                 break;
1427         default:
1428                 break;
1429         }
1430
1431 }
1432
1433 #ifdef CONFIG_SATA_AHCI_TEGRA
1434 static void cardhu_sata_init(void)
1435 {
1436         platform_device_register(&tegra_sata_device);
1437 }
1438 #else
1439 static void cardhu_sata_init(void) { }
1440 #endif
1441
1442 static void __init tegra_cardhu_init(void)
1443 {
1444         tegra_thermal_init(&thermal_data,
1445                                 &skin_data,
1446                                 throttle_list,
1447                                 ARRAY_SIZE(throttle_list));
1448         tegra_clk_init_from_table(cardhu_clk_init_table);
1449         tegra_enable_pinmux();
1450         tegra_smmu_init();
1451         cardhu_pinmux_init();
1452         cardhu_i2c_init();
1453         cardhu_spi_init();
1454         cardhu_usb_init();
1455 #ifdef CONFIG_TEGRA_EDP_LIMITS
1456         cardhu_edp_init();
1457 #endif
1458         cardhu_uart_init();
1459         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
1460         tegra_ram_console_debug_init();
1461         tegra_io_dpd_init();
1462         cardhu_sdhci_init();
1463         cardhu_regulator_init();
1464         cardhu_dtv_init();
1465         cardhu_suspend_init();
1466         cardhu_touch_init();
1467         cardhu_modem_init();
1468         cardhu_kbc_init();
1469         cardhu_scroll_init();
1470         cardhu_keys_init();
1471         cardhu_panel_init();
1472         cardhu_pmon_init();
1473         cardhu_sensors_init();
1474         cardhu_setup_bluesleep();
1475         cardhu_sata_init();
1476         //audio_wired_jack_init();
1477         cardhu_pins_state_init();
1478         cardhu_emc_init();
1479         tegra_release_bootloader_fb();
1480         cardhu_pci_init();
1481 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1482         tegra_wdt_recovery_init();
1483 #endif
1484         tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
1485 }
1486
1487 static void __init tegra_cardhu_reserve(void)
1488 {
1489 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
1490         /* support 1920X1200 with 24bpp */
1491         tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M);
1492 #else
1493         tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
1494 #endif
1495         tegra_ram_console_debug_reserve(SZ_1M);
1496 }
1497
1498 static const char *cardhu_dt_board_compat[] = {
1499         "nvidia,cardhu",
1500         NULL
1501 };
1502
1503 MACHINE_START(CARDHU, "cardhu")
1504         .atag_offset    = 0x100,
1505         .soc            = &tegra_soc_desc,
1506         .map_io         = tegra_map_common_io,
1507         .reserve        = tegra_cardhu_reserve,
1508         .init_early     = tegra30_init_early,
1509         .init_irq       = tegra_init_irq,
1510         .handle_irq     = gic_handle_irq,
1511         .timer          = &tegra_timer,
1512         .init_machine   = tegra_cardhu_init,
1513         .restart        = tegra_assert_system_reset,
1514         .dt_compat      = cardhu_dt_board_compat,
1515 MACHINE_END