arm: tegra: soc device registration
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/ctype.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/serial_8250.h>
28 #include <linux/i2c.h>
29 #include <linux/i2c/panjit_ts.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/i2c-tegra.h>
33 #include <linux/gpio.h>
34 #include <linux/input.h>
35 #include <linux/platform_data/tegra_usb.h>
36 #include <linux/spi/spi.h>
37 #include <linux/i2c/atmel_mxt_ts.h>
38 #include <linux/tegra_uart.h>
39 #include <linux/memblock.h>
40 #include <linux/spi-tegra.h>
41 #include <linux/nfc/pn544.h>
42 #include <linux/rfkill-gpio.h>
43 #include <linux/of_platform.h>
44
45 #include <sound/wm8903.h>
46 #include <sound/max98095.h>
47 #include <media/tegra_dtv.h>
48
49 #include <asm/hardware/gic.h>
50
51 #include <mach/edp.h>
52 #include <mach/clk.h>
53 #include <mach/iomap.h>
54 #include <mach/irqs.h>
55 #include <mach/pinmux.h>
56 #include <mach/iomap.h>
57 #include <mach/io_dpd.h>
58 #include <mach/io.h>
59 #include <mach/i2s.h>
60 #include <mach/tegra_asoc_pdata.h>
61 #include <mach/tegra_wm8903_pdata.h>
62 #include <mach/usb_phy.h>
63 #include <mach/thermal.h>
64 #include <mach/pci.h>
65 #include <mach/gpio-tegra.h>
66 #include <mach/tegra_fiq_debugger.h>
67 #include <linux/thermal.h>
68
69 #include <asm/hardware/gic.h>
70 #include <asm/mach-types.h>
71 #include <asm/mach/arch.h>
72
73 #include "board.h"
74 #include "clock.h"
75 #include "board-cardhu.h"
76 #include "board-touch.h"
77 #include "devices.h"
78 #include "gpio-names.h"
79 #include "fuse.h"
80 #include "pm.h"
81 #include "baseband-xmm-power.h"
82 #include "wdt-recovery.h"
83 #include "common.h"
84
85 static struct balanced_throttle throttle_list[] = {
86         {
87                 .tegra_cdev = {
88                         .id = CDEV_BTHROT_ID_TJ,
89                 },
90                 .throt_tab_size = 10,
91                 .throt_tab = {
92                         {      0, 1000 },
93                         { 640000, 1000 },
94                         { 640000, 1000 },
95                         { 640000, 1000 },
96                         { 640000, 1000 },
97                         { 640000, 1000 },
98                         { 760000, 1000 },
99                         { 760000, 1050 },
100                         {1000000, 1050 },
101                         {1000000, 1100 },
102                 },
103         },
104 };
105
106 static struct tegra_thermal_bind thermal_binds[] = {
107         /* Thermal Throttling */
108         {
109                 .tdev_id = THERMAL_DEVICE_ID_NCT_EXT,
110                 .cdev_id = CDEV_BTHROT_ID_TJ,
111                 .type = THERMAL_TRIP_PASSIVE,
112                 .passive = {
113                         .trip_temp = 85000,
114                         .tc1 = 0,
115                         .tc2 = 1,
116                         .passive_delay = 2000,
117                 }
118         },
119         /* EDP Capping */
120         {
121                 .tdev_id = THERMAL_DEVICE_ID_NCT_EXT,
122                 .cdev_id = CDEV_EDPTABLE_ID_EDP,
123                 .type = THERMAL_TRIP_ACTIVE,
124                 .get_trip_temp = tegra_edp_get_trip_temp,
125                 .get_trip_size = tegra_edp_get_trip_size,
126         },
127         {
128                 .tdev_id = THERMAL_DEVICE_ID_NULL,
129         },
130 };
131
132 static struct rfkill_gpio_platform_data cardhu_bt_rfkill_pdata[] = {
133         {
134                 .name           = "bt_rfkill",
135                 .shutdown_gpio  = TEGRA_GPIO_PU0,
136                 .reset_gpio     = TEGRA_GPIO_INVALID,
137                 .type           = RFKILL_TYPE_BLUETOOTH,
138         },
139 };
140
141 static struct platform_device cardhu_bt_rfkill_device = {
142         .name = "rfkill_gpio",
143         .id             = -1,
144         .dev = {
145                 .platform_data = &cardhu_bt_rfkill_pdata,
146         },
147 };
148
149 static struct resource cardhu_bluesleep_resources[] = {
150         [0] = {
151                 .name = "gpio_host_wake",
152                         .start  = TEGRA_GPIO_PU6,
153                         .end    = TEGRA_GPIO_PU6,
154                         .flags  = IORESOURCE_IO,
155         },
156         [1] = {
157                 .name = "gpio_ext_wake",
158                         .start  = TEGRA_GPIO_PU1,
159                         .end    = TEGRA_GPIO_PU1,
160                         .flags  = IORESOURCE_IO,
161         },
162         [2] = {
163                 .name = "host_wake",
164                         .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
165         },
166 };
167
168 static struct platform_device cardhu_bluesleep_device = {
169         .name           = "bluesleep",
170         .id             = -1,
171         .num_resources  = ARRAY_SIZE(cardhu_bluesleep_resources),
172         .resource       = cardhu_bluesleep_resources,
173 };
174
175 static noinline void __init cardhu_setup_bluesleep(void)
176 {
177         cardhu_bluesleep_resources[2].start =
178                 cardhu_bluesleep_resources[2].end =
179                         gpio_to_irq(TEGRA_GPIO_PU6);
180         platform_device_register(&cardhu_bluesleep_device);
181         return;
182 }
183
184 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
185         /* name         parent          rate            enabled */
186         { "pll_m",      NULL,           0,              false},
187         { "hda",        "pll_p",        108000000,      false},
188         { "hda2codec_2x","pll_p",       48000000,       false},
189         { "pwm",        "pll_p",        3187500,        false},
190         { "blink",      "clk_32k",      32768,          true},
191         { "i2s0",       "pll_a_out0",   0,              false},
192         { "i2s1",       "pll_a_out0",   0,              false},
193         { "i2s3",       "pll_a_out0",   0,              false},
194         { "spdif_out",  "pll_a_out0",   0,              false},
195         { "d_audio",    "clk_m",        12000000,       false},
196         { "dam0",       "clk_m",        12000000,       false},
197         { "dam1",       "clk_m",        12000000,       false},
198         { "dam2",       "clk_m",        12000000,       false},
199         { "audio1",     "i2s1_sync",    0,              false},
200         { "audio3",     "i2s3_sync",    0,              false},
201         { "vi_sensor",  "pll_p",        150000000,      false},
202         { "i2c1",       "pll_p",        3200000,        false},
203         { "i2c2",       "pll_p",        3200000,        false},
204         { "i2c3",       "pll_p",        3200000,        false},
205         { "i2c4",       "pll_p",        3200000,        false},
206         { "i2c5",       "pll_p",        3200000,        false},
207         { "vi",         "pll_p",        0,              false},
208         { NULL,         NULL,           0,              0},
209 };
210
211 static struct pn544_i2c_platform_data nfc_pdata = {
212         .irq_gpio = TEGRA_GPIO_PX0,
213         .ven_gpio = TEGRA_GPIO_PP3,
214         .firm_gpio = TEGRA_GPIO_PO7,
215         };
216
217 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
218         {
219                 I2C_BOARD_INFO("pn544", 0x28),
220                 .platform_data = &nfc_pdata,
221         },
222 };
223 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
224         .adapter_nr     = 0,
225         .bus_count      = 1,
226         .bus_clk_rate   = { 100000, 0 },
227         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
228         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
229         .arb_recovery = arb_lost_recovery,
230 };
231
232 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
233         .adapter_nr     = 1,
234         .bus_count      = 1,
235         .bus_clk_rate   = { 400000, 0 },
236         .is_clkon_always = true,
237         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
238         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
239         .arb_recovery = arb_lost_recovery,
240 };
241
242 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
243         .adapter_nr     = 2,
244         .bus_count      = 1,
245         .bus_clk_rate   = { 100000, 0 },
246         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
247         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
248         .arb_recovery = arb_lost_recovery,
249 };
250
251 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
252         .adapter_nr     = 3,
253         .bus_count      = 1,
254         .bus_clk_rate   = { 10000, 0 },
255         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
256         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
257         .arb_recovery = arb_lost_recovery,
258 };
259
260 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
261         .adapter_nr     = 4,
262         .bus_count      = 1,
263         .bus_clk_rate   = { 400000, 0 },
264         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
265         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
266         .arb_recovery = arb_lost_recovery,
267 };
268
269
270 #if 0
271 struct tegra_wired_jack_conf audio_wr_jack_conf = {
272         .hp_det_n = TEGRA_GPIO_PW2,
273         .en_mic_ext = TEGRA_GPIO_PX1,
274         .en_mic_int = TEGRA_GPIO_PX0,
275 };
276 #endif
277
278 static struct wm8903_platform_data cardhu_wm8903_pdata = {
279         .irq_active_low = 0,
280         .micdet_cfg = 0,
281         .micdet_delay = 100,
282         .gpio_base = CARDHU_GPIO_WM8903(0),
283         .gpio_cfg = {
284                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
285                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
286                         WM8903_GP2_DIR,
287                 WM8903_GPIO_CONFIG_ZERO,
288                 0,
289                 0,
290         },
291 };
292
293 /* Equalizer filter coefs generated from the MAXIM MAX98095
294  * evkit software tool */
295 static struct max98095_eq_cfg max98095_eq_cfg[] = {
296         {
297                 .name = "FLAT",
298                 .rate = 44100,
299                 .band1 = {0x2000, 0xC002, 0x4000, 0x00E9, 0x0000},
300                 .band2 = {0x2000, 0xC00F, 0x4000, 0x02BC, 0x0000},
301                 .band3 = {0x2000, 0xC0A7, 0x4000, 0x0916, 0x0000},
302                 .band4 = {0x2000, 0xC5C2, 0x4000, 0x1A87, 0x0000},
303                 .band5 = {0x2000, 0xF6B0, 0x4000, 0x3F51, 0x0000},
304         },
305         {
306                 .name = "LOWPASS1K",
307                 .rate = 44100,
308                 .band1 = {0x205D, 0xC001, 0x3FEF, 0x002E, 0x02E0},
309                 .band2 = {0x5B9A, 0xC093, 0x3AB2, 0x088B, 0x1981},
310                 .band3 = {0x0D22, 0xC170, 0x26EA, 0x0D79, 0x32CF},
311                 .band4 = {0x0894, 0xC612, 0x01B3, 0x1B34, 0x3FFA},
312                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
313         },
314         { /* BASS=-12dB, TREBLE=+9dB, Fc=5KHz */
315                 .name = "HIBOOST",
316                 .rate = 44100,
317                 .band1 = {0x0815, 0xC001, 0x3AA4, 0x0003, 0x19A2},
318                 .band2 = {0x0815, 0xC103, 0x092F, 0x0B55, 0x3F56},
319                 .band3 = {0x0E0A, 0xC306, 0x1E5C, 0x136E, 0x3856},
320                 .band4 = {0x2459, 0xF665, 0x0CAA, 0x3F46, 0x3EBB},
321                 .band5 = {0x5BBB, 0x3FFF, 0xCEB0, 0x0000, 0x28CA},
322         },
323         { /* BASS=12dB, TREBLE=+12dB */
324                 .name = "LOUD12DB",
325                 .rate = 44100,
326                 .band1 = {0x7FC1, 0xC001, 0x3EE8, 0x0020, 0x0BC7},
327                 .band2 = {0x51E9, 0xC016, 0x3C7C, 0x033F, 0x14E9},
328                 .band3 = {0x1745, 0xC12C, 0x1680, 0x0C2F, 0x3BE9},
329                 .band4 = {0x4536, 0xD7E2, 0x0ED4, 0x31DD, 0x3E42},
330                 .band5 = {0x7FEF, 0x3FFF, 0x0BAB, 0x0000, 0x3EED},
331         },
332         {
333                 .name = "FLAT",
334                 .rate = 16000,
335                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
336                 .band2 = {0x2000, 0xC033, 0x4000, 0x0505, 0x0000},
337                 .band3 = {0x2000, 0xC268, 0x4000, 0x115F, 0x0000},
338                 .band4 = {0x2000, 0xDA62, 0x4000, 0x33C6, 0x0000},
339                 .band5 = {0x2000, 0x4000, 0x4000, 0x0000, 0x0000},
340         },
341         {
342                 .name = "LOWPASS1K",
343                 .rate = 16000,
344                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
345                 .band2 = {0x5BE8, 0xC3E0, 0x3307, 0x15ED, 0x26A0},
346                 .band3 = {0x0F71, 0xD15A, 0x08B3, 0x2BD0, 0x3F67},
347                 .band4 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
348                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
349         },
350         { /* BASS=-12dB, TREBLE=+9dB, Fc=2KHz */
351                 .name = "HIBOOST",
352                 .rate = 16000,
353                 .band1 = {0x0815, 0xC001, 0x3BD2, 0x0009, 0x16BF},
354                 .band2 = {0x080E, 0xC17E, 0xF653, 0x0DBD, 0x3F43},
355                 .band3 = {0x0F80, 0xDF45, 0xEE33, 0x36FE, 0x3D79},
356                 .band4 = {0x590B, 0x3FF0, 0xE882, 0x02BD, 0x3B87},
357                 .band5 = {0x4C87, 0xF3D0, 0x063F, 0x3ED4, 0x3FB1},
358         },
359         { /* BASS=12dB, TREBLE=+12dB */
360                 .name = "LOUD12DB",
361                 .rate = 16000,
362                 .band1 = {0x7FC1, 0xC001, 0x3D07, 0x0058, 0x1344},
363                 .band2 = {0x2DA6, 0xC013, 0x3CF1, 0x02FF, 0x138B},
364                 .band3 = {0x18F1, 0xC08E, 0x244D, 0x0863, 0x34B5},
365                 .band4 = {0x2BE0, 0xF385, 0x04FD, 0x3EC5, 0x3FCE},
366                 .band5 = {0x7FEF, 0x4000, 0x0BAB, 0x0000, 0x3EED},
367         },
368 };
369
370 static struct max98095_pdata cardhu_max98095_pdata = {
371         /* equalizer configuration */
372         .eq_cfg = max98095_eq_cfg,
373         .eq_cfgcnt = ARRAY_SIZE(max98095_eq_cfg),
374
375         /* Biquad filter response configuration */
376         .bq_cfg = NULL,
377         .bq_cfgcnt = 0,
378
379         /* microphone configuration */
380         .digmic_left_mode = 1,
381         .digmic_right_mode = 1,
382 };
383
384 static struct i2c_board_info __initdata cardhu_codec_wm8903_info = {
385         I2C_BOARD_INFO("wm8903", 0x1a),
386         .platform_data = &cardhu_wm8903_pdata,
387 };
388
389 static struct i2c_board_info __initdata cardhu_codec_aic326x_info = {
390         I2C_BOARD_INFO("aic3262-codec", 0x18),
391 };
392
393 static struct i2c_board_info __initdata cardhu_codec_max98095_info = {
394         I2C_BOARD_INFO("max98095", 0x10),
395         .platform_data = &cardhu_max98095_pdata,
396 };
397
398 static void cardhu_i2c_init(void)
399 {
400         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
401         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
402         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
403         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
404         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
405
406         platform_device_register(&tegra_i2c_device5);
407         platform_device_register(&tegra_i2c_device4);
408         platform_device_register(&tegra_i2c_device3);
409         platform_device_register(&tegra_i2c_device2);
410         platform_device_register(&tegra_i2c_device1);
411
412         cardhu_codec_wm8903_info.irq = cardhu_codec_max98095_info.irq =
413                 cardhu_codec_aic326x_info.irq = gpio_to_irq(TEGRA_GPIO_CDC_IRQ);
414         i2c_register_board_info(4, &cardhu_codec_wm8903_info, 1);
415         i2c_register_board_info(4, &cardhu_codec_max98095_info, 1);
416         i2c_register_board_info(4, &cardhu_codec_aic326x_info, 1);
417
418         cardhu_i2c_bus3_board_info[0].irq = gpio_to_irq(TEGRA_GPIO_PX0);
419         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
420 }
421
422 static struct platform_device *cardhu_uart_devices[] __initdata = {
423         &tegra_uarta_device,
424         &tegra_uartb_device,
425         &tegra_uartc_device,
426         &tegra_uartd_device,
427         &tegra_uarte_device,
428 };
429 static struct uart_clk_parent uart_parent_clk[] = {
430         [0] = {.name = "clk_m"},
431         [1] = {.name = "pll_p"},
432 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
433         [2] = {.name = "pll_m"},
434 #endif
435 };
436
437 static struct tegra_uart_platform_data cardhu_uart_pdata;
438 static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
439
440 static void __init uart_debug_init(void)
441 {
442         struct board_info board_info;
443         int debug_port_id;
444
445         tegra_get_board_info(&board_info);
446
447         debug_port_id = get_tegra_uart_debug_port_id();
448         if (debug_port_id < 0) {
449                 debug_port_id = 0;
450                         /* UARTB is debug port
451                          *       for SLT - E1186/E1187/PM269
452                          *       for E1256/E1257
453                          */
454                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
455                         ((board_info.board_id == BOARD_E1186) ||
456                         (board_info.board_id == BOARD_E1187) ||
457                         (board_info.board_id == BOARD_PM269))) ||
458                         (board_info.board_id == BOARD_E1256) ||
459                         (board_info.board_id == BOARD_E1257))
460                                 debug_port_id = 1;
461         }
462
463 #ifdef CONFIG_TEGRA_IRDA
464         if ((board_info.board_id == BOARD_E1186) ||
465                 (board_info.board_id == BOARD_E1198)) {
466                 if (debug_port_id == 1) {
467                         cardhu_irda_pdata.is_irda = false;
468                         pr_err("UARTB is not available for IrDA\n");
469                 }
470         }
471 #endif
472
473         switch (debug_port_id) {
474         case 0:
475                 /* UARTA is the debug port. */
476                 pr_info("Selecting UARTA as the debug console\n");
477                 cardhu_uart_devices[0] = &debug_uarta_device;
478                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
479                 debug_uart_port_base = ((struct plat_serial8250_port *)(
480                         debug_uarta_device.dev.platform_data))->mapbase;
481                 break;
482
483         case 1:
484                 /* UARTB is the debug port. */
485                 pr_info("Selecting UARTB as the debug console\n");
486                 cardhu_uart_devices[1] = &debug_uartb_device;
487                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
488                 debug_uart_port_base = ((struct plat_serial8250_port *)(
489                         debug_uartb_device.dev.platform_data))->mapbase;
490                 break;
491
492         case 2:
493                 /* UARTC is the debug port. */
494                 pr_info("Selecting UARTC as the debug console\n");
495                 cardhu_uart_devices[2] = &debug_uartc_device;
496                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
497                 debug_uart_port_base = ((struct plat_serial8250_port *)(
498                         debug_uartc_device.dev.platform_data))->mapbase;
499                 break;
500
501         case 3:
502                 /* UARTD is the debug port. */
503                 pr_info("Selecting UARTD as the debug console\n");
504                 cardhu_uart_devices[3] = &debug_uartd_device;
505                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
506                 debug_uart_port_base = ((struct plat_serial8250_port *)(
507                         debug_uartd_device.dev.platform_data))->mapbase;
508                 break;
509
510         case 4:
511                 /* UARTE is the debug port. */
512                 pr_info("Selecting UARTE as the debug console\n");
513                 cardhu_uart_devices[4] = &debug_uarte_device;
514                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
515                 debug_uart_port_base = ((struct plat_serial8250_port *)(
516                         debug_uarte_device.dev.platform_data))->mapbase;
517                 break;
518
519         default:
520                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
521                 cardhu_uart_devices[0] = &debug_uarta_device;
522                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
523                 debug_uart_port_base = ((struct plat_serial8250_port *)(
524                         debug_uarta_device.dev.platform_data))->mapbase;
525                 break;
526         }
527         return;
528 }
529
530 static void __init cardhu_uart_init(void)
531 {
532         struct clk *c;
533         int i;
534         struct board_info board_info;
535
536         tegra_get_board_info(&board_info);
537
538         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
539                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
540                 if (IS_ERR_OR_NULL(c)) {
541                         pr_err("Not able to get the clock for %s\n",
542                                                 uart_parent_clk[i].name);
543                         continue;
544                 }
545                 uart_parent_clk[i].parent_clk = c;
546                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
547         }
548         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
549         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
550         cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
551         cardhu_loopback_uart_pdata.parent_clk_count =
552                                                 ARRAY_SIZE(uart_parent_clk);
553         cardhu_loopback_uart_pdata.is_loopback = true;
554         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
555         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
556         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
557         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
558         /* UARTE is used for loopback test purpose */
559         tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
560
561         /* Register low speed only if it is selected */
562         if (!is_tegra_debug_uartport_hs()) {
563                 uart_debug_init();
564                 /* Clock enable for the debug channel */
565                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
566                         pr_info("The debug console clock name is %s\n",
567                                                 debug_uart_clk->name);
568                         c = tegra_get_clock_by_name("pll_p");
569                         if (IS_ERR_OR_NULL(c))
570                                 pr_err("Not getting the parent clock pll_p\n");
571                         else
572                                 clk_set_parent(debug_uart_clk, c);
573
574                         clk_enable(debug_uart_clk);
575                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
576                 } else {
577                         pr_err("Not getting the clock %s for debug console\n",
578                                         debug_uart_clk->name);
579                 }
580         }
581
582 #ifdef CONFIG_TEGRA_IRDA
583         if (((board_info.board_id == BOARD_E1186) ||
584                 (board_info.board_id == BOARD_E1198)) &&
585                         cardhu_irda_pdata.is_irda) {
586                 cardhu_irda_pdata.parent_clk_list = uart_parent_clk;
587                 cardhu_irda_pdata.parent_clk_count =
588                                         ARRAY_SIZE(uart_parent_clk);
589
590                 tegra_uartb_device.dev.platform_data = &cardhu_irda_pdata;
591         }
592 #endif
593
594         platform_add_devices(cardhu_uart_devices,
595                                 ARRAY_SIZE(cardhu_uart_devices));
596 }
597
598 static struct platform_device tegra_camera = {
599         .name = "tegra_camera",
600         .id = -1,
601 };
602
603 static struct platform_device *cardhu_spi_devices[] __initdata = {
604         &tegra_spi_device4,
605 };
606
607 static struct platform_device *touch_spi_device[] __initdata = {
608         &tegra_spi_device1,
609 };
610
611 struct spi_clk_parent spi_parent_clk[] = {
612         [0] = {.name = "pll_p"},
613 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
614         [1] = {.name = "pll_m"},
615         [2] = {.name = "clk_m"},
616 #else
617         [1] = {.name = "clk_m"},
618 #endif
619 };
620
621 static struct tegra_spi_platform_data cardhu_spi_pdata = {
622         .is_dma_based           = true,
623         .max_dma_buffer         = (16 * 1024),
624         .is_clkon_always        = false,
625         .max_rate               = 100000000,
626 };
627
628 static void __init cardhu_spi_init(void)
629 {
630         int i;
631         struct clk *c;
632         struct board_info board_info, display_board_info;
633
634         tegra_get_board_info(&board_info);
635         tegra_get_display_board_info(&display_board_info);
636
637         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
638                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
639                 if (IS_ERR_OR_NULL(c)) {
640                         pr_err("Not able to get the clock for %s\n",
641                                                 spi_parent_clk[i].name);
642                         continue;
643                 }
644                 spi_parent_clk[i].parent_clk = c;
645                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
646         }
647         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
648         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
649         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
650         platform_add_devices(cardhu_spi_devices,
651                                 ARRAY_SIZE(cardhu_spi_devices));
652
653         if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
654                 platform_add_devices(touch_spi_device,
655                                 ARRAY_SIZE(touch_spi_device));
656         }
657         if (board_info.board_id == BOARD_E1198) {
658                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
659                 platform_device_register(&tegra_spi_device2);
660                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
661                 platform_device_register(&tegra_spi_slave_device1);
662         }
663 }
664
665 static void __init cardhu_dtv_init(void)
666 {
667         struct board_info board_info;
668
669         tegra_get_board_info(&board_info);
670
671         if (board_info.board_id == BOARD_E1186)
672                 platform_device_register(&tegra_dtv_device);
673 }
674
675 static struct resource tegra_rtc_resources[] = {
676         [0] = {
677                 .start = TEGRA_RTC_BASE,
678                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
679                 .flags = IORESOURCE_MEM,
680         },
681         [1] = {
682                 .start = INT_RTC,
683                 .end = INT_RTC,
684                 .flags = IORESOURCE_IRQ,
685         },
686 };
687
688 static struct platform_device tegra_rtc_device = {
689         .name = "tegra_rtc",
690         .id   = -1,
691         .resource = tegra_rtc_resources,
692         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
693 };
694
695 static struct tegra_asoc_platform_data cardhu_audio_wm8903_pdata = {
696         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
697         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
698         .gpio_hp_mute           = -1,
699         .gpio_int_mic_en        = -1,
700         .gpio_ext_mic_en        = -1,
701         .i2s_param[HIFI_CODEC]  = {
702                 .audio_port_id  = 0,
703                 .is_i2s_master  = 1,
704                 .i2s_mode       = TEGRA_DAIFMT_I2S,
705         },
706         .i2s_param[BASEBAND]    = {
707                 .audio_port_id  = -1,
708         },
709         .i2s_param[BT_SCO]      = {
710                 .audio_port_id  = 3,
711                 .is_i2s_master  = 1,
712                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
713         },
714 };
715
716 static struct tegra_asoc_platform_data cardhu_audio_max98095_pdata = {
717         .gpio_spkr_en           = -1,
718         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
719         .gpio_hp_mute           = -1,
720         .gpio_int_mic_en        = -1,
721         .gpio_ext_mic_en        = -1,
722         .i2s_param[HIFI_CODEC]  = {
723                 .audio_port_id  = 0,
724                 .is_i2s_master  = 1,
725                 .i2s_mode       = TEGRA_DAIFMT_I2S,
726         },
727         .i2s_param[BASEBAND]    = {
728                 .audio_port_id  = -1,
729         },
730         .i2s_param[BT_SCO]      = {
731                 .audio_port_id  = 3,
732                 .is_i2s_master  = 1,
733                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
734         },
735 };
736
737 static struct platform_device cardhu_audio_wm8903_device = {
738         .name   = "tegra-snd-wm8903",
739         .id     = 0,
740         .dev    = {
741                 .platform_data = &cardhu_audio_wm8903_pdata,
742         },
743 };
744
745 static struct platform_device cardhu_audio_max98095_device = {
746         .name   = "tegra-snd-max98095",
747         .id     = 0,
748         .dev    = {
749                 .platform_data = &cardhu_audio_max98095_pdata,
750         },
751 };
752
753 static struct tegra_asoc_platform_data cardhu_audio_aic326x_pdata = {
754         .gpio_spkr_en           = -1,
755         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
756         .gpio_hp_mute           = -1,
757         .gpio_int_mic_en        = -1,
758         .gpio_ext_mic_en        = -1,
759         /*defaults for Verbier-Cardhu board with TI AIC326X codec*/
760         .i2s_param[HIFI_CODEC]  = {
761                 .audio_port_id  = 0,
762                 .is_i2s_master  = 1,
763                 .i2s_mode       = TEGRA_DAIFMT_I2S,
764                 .sample_size    = 16,
765         },
766         .i2s_param[BT_SCO]      = {
767                 .sample_size    = 16,
768                 .audio_port_id  = 3,
769                 .is_i2s_master  = 1,
770                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
771         },
772 };
773
774 static struct platform_device cardhu_audio_aic326x_device = {
775         .name   = "tegra-snd-aic326x",
776         .id     = 0,
777         .dev    = {
778                 .platform_data  = &cardhu_audio_aic326x_pdata,
779         },
780 };
781
782 static struct platform_device *cardhu_devices[] __initdata = {
783         &tegra_pmu_device,
784         &tegra_rtc_device,
785         &tegra_udc_device,
786         &tegra_wdt0_device,
787         &tegra_wdt1_device,
788         &tegra_wdt2_device,
789 #if defined(CONFIG_TEGRA_AVP)
790         &tegra_avp_device,
791 #endif
792         &tegra_camera,
793 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
794         &tegra_se_device,
795 #endif
796         &tegra_ahub_device,
797         &tegra_dam_device0,
798         &tegra_dam_device1,
799         &tegra_dam_device2,
800         &tegra_i2s_device0,
801         &tegra_i2s_device1,
802         &tegra_i2s_device3,
803         &tegra_spdif_device,
804         &spdif_dit_device,
805         &bluetooth_dit_device,
806         &baseband_dit_device,
807         &cardhu_bt_rfkill_device,
808         &tegra_pcm_device,
809         &cardhu_audio_wm8903_device,
810         &cardhu_audio_max98095_device,
811         &cardhu_audio_aic326x_device,
812         &tegra_hda_device,
813         &tegra_cec_device,
814 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
815         &tegra_aes_device,
816 #endif
817 };
818
819 #define E1506_MXT_CONFIG_CRC 0x62F903
820 static const u8 e1506_config[] = {
821         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
822         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x05, 0x01, 0x00,
823         0x00, 0x1E, 0x0A, 0x8B, 0x00, 0x00, 0x13, 0x0B,
824         0x00, 0x10, 0x32, 0x03, 0x03, 0x00, 0x03, 0x01,
825         0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xBF, 0x03, 0x1B,
826         0x02, 0x00, 0x00, 0x37, 0x37, 0x00, 0x00, 0x00,
827         0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
828         0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
829         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
830         0x00, 0x00, 0x00, 0xA9, 0x7F, 0x9A, 0x0E, 0x00,
831         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
832         0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00,
833         0x00, 0x00, 0x03, 0x23, 0x00, 0x00, 0x00, 0x0A,
834         0x0F, 0x14, 0x19, 0x03, 0x00, 0x00, 0x00, 0x00,
835         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
836         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
837         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
838         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
839         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
840         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
841         0x00, 0x00, 0x00, 0x01, 0x00, 0x03, 0x08, 0x10,
842         0x00
843 };
844
845 #define MXT_CONFIG_CRC  0xD62DE8
846 static const u8 config[] = {
847         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
848         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
849         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
850         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
851         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
852         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
853         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
854         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
855         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
856         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
857         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
858         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
859         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
860         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
861         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
862         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
863         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
864         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
865         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
866         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
867 };
868
869 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
870 static const u8 config_sku2000[] = {
871         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
872         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
873         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
874         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
875         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
876         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
877         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
878         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
879         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
880         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
881         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
882         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
883         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
884         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
885         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
886         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
887         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
888         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
889         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
890         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
891 };
892
893 static struct mxt_platform_data atmel_mxt_info = {
894         .x_line         = 27,
895         .y_line         = 42,
896         .x_size         = 768,
897         .y_size         = 1366,
898         .blen           = 0x20,
899         .threshold      = 0x3C,
900         .voltage        = 3300000,              /* 3.3V */
901         .orient         = 5,
902         .config         = config,
903         .config_length  = 157,
904         .config_crc     = MXT_CONFIG_CRC,
905         .irqflags       = IRQF_TRIGGER_FALLING,
906 /*      .read_chg       = &read_chg, */
907         .read_chg       = NULL,
908 };
909
910 static struct mxt_platform_data e1506_atmel_mxt_info = {
911         .x_line         = 19,
912         .y_line         = 11,
913         .x_size         = 960,
914         .y_size         = 540,
915         .blen           = 0x10,
916         .threshold      = 0x32,
917         .voltage        = 3300000,              /* 3.3V */
918         .orient         = 3,
919         .config         = e1506_config,
920         .config_length  = 168,
921         .config_crc     = E1506_MXT_CONFIG_CRC,
922         .irqflags       = IRQF_TRIGGER_FALLING,
923 /*      .read_chg       = &read_chg, */
924         .read_chg       = NULL,
925 };
926
927 static struct i2c_board_info __initdata atmel_i2c_info[] = {
928         {
929                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
930                 .platform_data = &atmel_mxt_info,
931         }
932 };
933
934 static struct i2c_board_info __initdata e1506_atmel_i2c_info[] = {
935         {
936                 I2C_BOARD_INFO("atmel_mxt_ts", 0x4A),
937                 .platform_data = &e1506_atmel_mxt_info,
938         }
939 };
940
941 static __initdata struct tegra_clk_init_table spi_clk_init_table[] = {
942         /* name         parent          rate            enabled */
943         { "sbc1",       "pll_p",        52000000,       true},
944         { NULL,         NULL,           0,              0},
945 };
946
947 static int __init cardhu_touch_init(void)
948 {
949         struct board_info BoardInfo, DisplayBoardInfo;
950
951         tegra_get_board_info(&BoardInfo);
952         tegra_get_display_board_info(&DisplayBoardInfo);
953         if (DisplayBoardInfo.board_id == BOARD_DISPLAY_PM313) {
954                 tegra_clk_init_from_table(spi_clk_init_table);
955
956                 touch_init_raydium(TEGRA_GPIO_PH4, TEGRA_GPIO_PH6, 2);
957         } else {
958                 gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
959                 gpio_direction_input(TEGRA_GPIO_PH4);
960
961                 gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
962                 gpio_direction_output(TEGRA_GPIO_PH6, 0);
963                 msleep(1);
964                 gpio_set_value(TEGRA_GPIO_PH6, 1);
965                 msleep(100);
966
967                 if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
968                         atmel_mxt_info.config = config_sku2000;
969                         atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
970                 }
971
972                 if (DisplayBoardInfo.board_id == BOARD_DISPLAY_E1506) {
973                         e1506_atmel_i2c_info[0].irq = gpio_to_irq(TEGRA_GPIO_PH4);
974                         i2c_register_board_info(1, e1506_atmel_i2c_info, 1);
975                 } else {
976                         atmel_i2c_info[0].irq = gpio_to_irq(TEGRA_GPIO_PH4);
977                         i2c_register_board_info(1, atmel_i2c_info, 1);
978                 }
979         }
980
981         return 0;
982 }
983
984 #if defined(CONFIG_USB_SUPPORT)
985
986 static void cardu_usb_hsic_postsupend(void)
987 {
988 #ifdef CONFIG_TEGRA_BB_XMM_POWER
989         baseband_xmm_set_power_status(BBXMM_PS_L2);
990 #endif
991 }
992
993 static void cardu_usb_hsic_preresume(void)
994 {
995 #ifdef CONFIG_TEGRA_BB_XMM_POWER
996         baseband_xmm_set_power_status(BBXMM_PS_L2TOL0);
997 #endif
998 }
999
1000 static void cardu_usb_hsic_phy_ready(void)
1001 {
1002 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1003         baseband_xmm_set_power_status(BBXMM_PS_L0);
1004 #endif
1005 }
1006
1007 static void cardu_usb_hsic_phy_off(void)
1008 {
1009 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1010         baseband_xmm_set_power_status(BBXMM_PS_L3);
1011 #endif
1012 }
1013
1014 static struct tegra_usb_phy_platform_ops hsic_xmm_plat_ops = {
1015         .post_suspend = cardu_usb_hsic_postsupend,
1016         .pre_resume = cardu_usb_hsic_preresume,
1017         .port_power = cardu_usb_hsic_phy_ready,
1018         .post_phy_off = cardu_usb_hsic_phy_off,
1019 };
1020
1021 static struct tegra_usb_platform_data tegra_ehci2_hsic_xmm_pdata = {
1022         .port_otg = false,
1023         .has_hostpc = true,
1024         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1025         .op_mode        = TEGRA_USB_OPMODE_HOST,
1026         .u_data.host = {
1027                 .vbus_gpio = -1,
1028                 .hot_plug = false,
1029                 .remote_wakeup_supported = false,
1030                 .power_off_on_suspend = false,
1031         },
1032         .ops = &hsic_xmm_plat_ops,
1033 };
1034 #endif
1035
1036 static int hsic_enable_gpio = -1;
1037 static int hsic_reset_gpio = -1;
1038
1039 void hsic_platform_open(void)
1040 {
1041         int reset_gpio = -1, enable_gpio = -1;
1042
1043         if (hsic_enable_gpio != -1)
1044                 enable_gpio = gpio_request(hsic_enable_gpio, "uhsic_enable");
1045         if (hsic_reset_gpio != -1)
1046                 reset_gpio = gpio_request(hsic_reset_gpio, "uhsic_reset");
1047         /* hsic enable signal deasserted, hsic reset asserted */
1048         if (!enable_gpio)
1049                 gpio_direction_output(hsic_enable_gpio, 0 /* deasserted */);
1050         if (!reset_gpio)
1051                 gpio_direction_output(hsic_reset_gpio, 0 /* asserted */);
1052         /* keep hsic reset asserted for 1 ms */
1053         udelay(1000);
1054         /* enable (power on) hsic */
1055         if (!enable_gpio)
1056                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
1057         udelay(1000);
1058         /* deassert reset */
1059         if (!reset_gpio)
1060                 gpio_set_value_cansleep(hsic_reset_gpio, 1);
1061
1062 }
1063
1064 void hsic_platform_close(void)
1065 {
1066         if (hsic_enable_gpio != -1) {
1067                 gpio_set_value(hsic_enable_gpio, 0);
1068                 gpio_free(hsic_enable_gpio);
1069         }
1070         if (hsic_reset_gpio != -1) {
1071                 gpio_set_value(hsic_reset_gpio, 0);
1072                 gpio_free(hsic_reset_gpio);
1073         }
1074 }
1075
1076 void hsic_power_on(void)
1077 {
1078         if (hsic_enable_gpio != -1) {
1079                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
1080                 udelay(1000);
1081         }
1082 }
1083
1084 void hsic_power_off(void)
1085 {
1086         if (hsic_enable_gpio != -1) {
1087                 gpio_set_value_cansleep(hsic_enable_gpio, 0);
1088                 udelay(1000);
1089         }
1090 }
1091
1092 #if defined(CONFIG_USB_SUPPORT)
1093 static struct tegra_usb_phy_platform_ops hsic_plat_ops = {
1094         .open = hsic_platform_open,
1095         .close = hsic_platform_close,
1096         .pre_phy_on = hsic_power_on,
1097         .post_phy_off = hsic_power_off,
1098 };
1099
1100 static struct tegra_usb_platform_data tegra_ehci2_hsic_pdata = {
1101         .port_otg = false,
1102         .has_hostpc = true,
1103         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1104         .op_mode        = TEGRA_USB_OPMODE_HOST,
1105         .u_data.host = {
1106                 .vbus_gpio = -1,
1107                 .hot_plug = false,
1108                 .remote_wakeup_supported = false,
1109                 .power_off_on_suspend = false,
1110         },
1111         .ops = &hsic_plat_ops,
1112 };
1113
1114 static struct tegra_usb_platform_data tegra_udc_pdata = {
1115         .port_otg = true,
1116         .has_hostpc = true,
1117         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1118         .op_mode = TEGRA_USB_OPMODE_DEVICE,
1119         .u_data.dev = {
1120                 .vbus_pmu_irq = 0,
1121                 .vbus_gpio = -1,
1122                 .charging_supported = false,
1123                 .remote_wakeup_supported = false,
1124         },
1125         .u_cfg.utmi = {
1126                 .hssync_start_delay = 0,
1127                 .elastic_limit = 16,
1128                 .idle_wait_delay = 17,
1129                 .term_range_adj = 6,
1130                 .xcvr_setup = 8,
1131                 .xcvr_lsfslew = 2,
1132                 .xcvr_lsrslew = 2,
1133                 .xcvr_setup_offset = 0,
1134                 .xcvr_use_fuses = 1,
1135         },
1136 };
1137
1138 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
1139         .port_otg = false,
1140         .has_hostpc = true,
1141         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1142         .op_mode        = TEGRA_USB_OPMODE_HOST,
1143         .u_data.host = {
1144                 .vbus_gpio = -1,
1145                 .hot_plug = false,
1146                 .remote_wakeup_supported = true,
1147                 .power_off_on_suspend = true,
1148         },
1149         .u_cfg.utmi = {
1150                 .hssync_start_delay = 0,
1151                 .elastic_limit = 16,
1152                 .idle_wait_delay = 17,
1153                 .term_range_adj = 6,
1154                 .xcvr_setup = 15,
1155                 .xcvr_lsfslew = 2,
1156                 .xcvr_lsrslew = 2,
1157                 .xcvr_setup_offset = 0,
1158                 .xcvr_use_fuses = 1,
1159         },
1160 };
1161
1162 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
1163         .port_otg = false,
1164         .has_hostpc = true,
1165         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1166         .op_mode = TEGRA_USB_OPMODE_HOST,
1167         .u_data.host = {
1168                 .vbus_gpio = -1,
1169                 .hot_plug = true,
1170                 .remote_wakeup_supported = true,
1171                 .power_off_on_suspend = true,
1172         },
1173         .u_cfg.utmi = {
1174                 .hssync_start_delay = 0,
1175                 .elastic_limit = 16,
1176                 .idle_wait_delay = 17,
1177                 .term_range_adj = 6,
1178                 .xcvr_setup = 8,
1179                 .xcvr_lsfslew = 2,
1180                 .xcvr_lsrslew = 2,
1181                 .xcvr_setup_offset = 0,
1182                 .xcvr_use_fuses = 1,
1183         },
1184 };
1185
1186 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
1187         .port_otg = true,
1188         .has_hostpc = true,
1189         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1190         .op_mode = TEGRA_USB_OPMODE_HOST,
1191         .u_data.host = {
1192                 .vbus_gpio = -1,
1193                 .hot_plug = true,
1194                 .remote_wakeup_supported = true,
1195                 .power_off_on_suspend = true,
1196         },
1197         .u_cfg.utmi = {
1198                 .hssync_start_delay = 0,
1199                 .elastic_limit = 16,
1200                 .idle_wait_delay = 17,
1201                 .term_range_adj = 6,
1202                 .xcvr_setup = 15,
1203                 .xcvr_lsfslew = 2,
1204                 .xcvr_lsrslew = 2,
1205                 .xcvr_setup_offset = 0,
1206                 .xcvr_use_fuses = 1,
1207         },
1208 };
1209
1210 static struct tegra_usb_otg_data tegra_otg_pdata = {
1211         .ehci_device = &tegra_ehci1_device,
1212         .ehci_pdata = &tegra_ehci1_utmi_pdata,
1213 };
1214 #endif
1215
1216 #if defined(CONFIG_USB_SUPPORT)
1217 static void cardhu_usb_init(void)
1218 {
1219         struct board_info bi;
1220
1221         tegra_get_board_info(&bi);
1222
1223         /* OTG should be the first to be registered */
1224         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
1225         platform_device_register(&tegra_otg_device);
1226
1227         /* setup the udc platform data */
1228         tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
1229
1230         if (bi.board_id == BOARD_PM267) {
1231                 hsic_enable_gpio = EN_HSIC_GPIO;
1232                 hsic_reset_gpio = PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
1233                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1234                 platform_device_register(&tegra_ehci2_device);
1235         } else if (bi.board_id == BOARD_E1256) {
1236                 hsic_enable_gpio = EN_HSIC_GPIO;
1237                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1238                 platform_device_register(&tegra_ehci2_device);
1239         } else if (bi.board_id == BOARD_E1186) {
1240                 tegra_ehci2_device.dev.platform_data =
1241                                                 &tegra_ehci2_hsic_xmm_pdata;
1242                 /* ehci2 registration happens in baseband-xmm-power  */
1243         } else {
1244                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata;
1245                 platform_device_register(&tegra_ehci2_device);
1246         }
1247
1248         tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
1249         platform_device_register(&tegra_ehci3_device);
1250
1251 }
1252 #else
1253 static void cardhu_usb_init(void) { }
1254 #endif
1255
1256 static struct baseband_power_platform_data tegra_baseband_power_data = {
1257         .baseband_type = BASEBAND_XMM,
1258         .modem = {
1259         .xmm = {
1260                         .bb_rst = XMM_GPIO_BB_RST,
1261                         .bb_on = XMM_GPIO_BB_ON,
1262                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
1263                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
1264                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
1265                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
1266                         .hsic_device = &tegra_ehci2_device,
1267                 },
1268         },
1269 };
1270
1271 static struct platform_device tegra_baseband_power_device = {
1272         .name = "baseband_xmm_power",
1273         .id = -1,
1274         .dev = {
1275                 .platform_data = &tegra_baseband_power_data,
1276         },
1277 };
1278
1279 static struct platform_device tegra_baseband_power2_device = {
1280         .name = "baseband_xmm_power2",
1281         .id = -1,
1282         .dev = {
1283                 .platform_data = &tegra_baseband_power_data,
1284         },
1285 };
1286
1287
1288 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
1289         .port_status[0] = 1,
1290         .port_status[1] = 1,
1291         .port_status[2] = 1,
1292         .use_dock_detect        = 0,
1293         .gpio           = 0,
1294 };
1295
1296 static void cardhu_pci_init(void)
1297 {
1298         struct board_info board_info;
1299
1300         tegra_get_board_info(&board_info);
1301         if (board_info.board_id == BOARD_E1291) {
1302                 cardhu_pci_platform_data.port_status[0] = 0;
1303                 cardhu_pci_platform_data.port_status[1] = 0;
1304                 cardhu_pci_platform_data.port_status[2] = 1;
1305                 cardhu_pci_platform_data.use_dock_detect = 1;
1306                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
1307         }
1308         if ((board_info.board_id == BOARD_E1186) ||
1309                 (board_info.board_id == BOARD_E1187) ||
1310                 (board_info.board_id == BOARD_E1291)) {
1311                 tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
1312                 platform_device_register(&tegra_pci_device);
1313         }
1314 }
1315
1316 static void cardhu_modem_init(void)
1317 {
1318         struct board_info board_info;
1319         int w_disable_gpio, ret;
1320
1321         tegra_get_board_info(&board_info);
1322         switch (board_info.board_id) {
1323         case BOARD_E1291:
1324         case BOARD_E1198:
1325                 if (((board_info.board_id == BOARD_E1291) &&
1326                                 (board_info.fab < BOARD_FAB_A03)) ||
1327                         ((board_info.board_id == BOARD_E1198) &&
1328                                         (board_info.fab < BOARD_FAB_A02))) {
1329                         w_disable_gpio = TEGRA_GPIO_PH5;
1330                 } else {
1331                         w_disable_gpio = TEGRA_GPIO_PDD5;
1332                 }
1333
1334                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
1335                 if (ret < 0)
1336                         pr_err("%s: gpio_request failed for gpio %d\n",
1337                                 __func__, w_disable_gpio);
1338                 else
1339                         gpio_direction_input(w_disable_gpio);
1340
1341                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
1342                 if (((board_info.board_id == BOARD_E1291) &&
1343                                 (board_info.fab >= BOARD_FAB_A04)) ||
1344                         ((board_info.board_id == BOARD_E1198) &&
1345                                         (board_info.fab >= BOARD_FAB_A02))) {
1346                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
1347                         if (ret < 0) {
1348                                 pr_err("%s(): Error in allocating gpio "
1349                                         "TEGRA_GPIO_PH7\n", __func__);
1350                                 break;
1351                         }
1352                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
1353                 }
1354                 break;
1355         case BOARD_E1186:
1356                 platform_device_register(&tegra_baseband_power_device);
1357                 platform_device_register(&tegra_baseband_power2_device);
1358                 break;
1359         default:
1360                 break;
1361         }
1362
1363 }
1364
1365 #ifdef CONFIG_SATA_AHCI_TEGRA
1366 static void cardhu_sata_init(void)
1367 {
1368         platform_device_register(&tegra_sata_device);
1369 }
1370 #else
1371 static void cardhu_sata_init(void) { }
1372 #endif
1373
1374 /* This needs to be inialized later hand */
1375 static int __init cardhu_throttle_list_init(void)
1376 {
1377         int i;
1378         for (i = 0; i < ARRAY_SIZE(throttle_list); i++)
1379                 if (balanced_throttle_register(&throttle_list[i]))
1380                         return -ENODEV;
1381
1382         return 0;
1383 }
1384 late_initcall(cardhu_throttle_list_init);
1385
1386 static void __init tegra_cardhu_init(void)
1387 {
1388         tegra_thermal_init(thermal_binds);
1389         tegra_clk_init_from_table(cardhu_clk_init_table);
1390         tegra_enable_pinmux();
1391         tegra_smmu_init();
1392         tegra_soc_device_init("cardhu");
1393         cardhu_pinmux_init();
1394         cardhu_i2c_init();
1395         cardhu_spi_init();
1396         cardhu_usb_init();
1397 #ifdef CONFIG_TEGRA_EDP_LIMITS
1398         cardhu_edp_init();
1399 #endif
1400         cardhu_uart_init();
1401         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
1402         tegra_ram_console_debug_init();
1403         tegra_io_dpd_init();
1404         cardhu_sdhci_init();
1405         cardhu_regulator_init();
1406         cardhu_dtv_init();
1407         cardhu_suspend_init();
1408         cardhu_touch_init();
1409         cardhu_modem_init();
1410         cardhu_kbc_init();
1411         cardhu_scroll_init();
1412         cardhu_keys_init();
1413         cardhu_panel_init();
1414         cardhu_pmon_init();
1415         cardhu_sensors_init();
1416         cardhu_setup_bluesleep();
1417         cardhu_sata_init();
1418         cardhu_pins_state_init();
1419         cardhu_emc_init();
1420         tegra_release_bootloader_fb();
1421         cardhu_pci_init();
1422 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1423         tegra_wdt_recovery_init();
1424 #endif
1425         tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
1426 }
1427
1428 static void __init tegra_cardhu_dt_init(void)
1429 {
1430         tegra_cardhu_init();
1431
1432         of_platform_populate(NULL,
1433                 of_default_bus_match_table, NULL, NULL);
1434 }
1435
1436 static void __init tegra_cardhu_reserve(void)
1437 {
1438 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
1439         /* support 1920X1200 with 24bpp */
1440         tegra_reserve(0, SZ_8M + SZ_1M, SZ_16M);
1441 #else
1442         tegra_reserve(SZ_128M, SZ_8M, SZ_16M);
1443 #endif
1444 }
1445
1446 static const char *cardhu_dt_board_compat[] = {
1447         "nvidia,cardhu",
1448         NULL
1449 };
1450
1451 MACHINE_START(CARDHU, "cardhu")
1452         .atag_offset    = 0x100,
1453         .soc            = &tegra_soc_desc,
1454         .map_io         = tegra_map_common_io,
1455         .reserve        = tegra_cardhu_reserve,
1456         .init_early     = tegra30_init_early,
1457         .init_irq       = tegra_init_irq,
1458         .handle_irq     = gic_handle_irq,
1459         .timer          = &tegra_timer,
1460         .init_machine   = tegra_cardhu_dt_init,
1461         .restart        = tegra_assert_system_reset,
1462         .dt_compat      = cardhu_dt_board_compat,
1463 MACHINE_END