arm: tegra: cardhu: disable hotplug for usb instance 1
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/ctype.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/serial_8250.h>
28 #include <linux/i2c.h>
29 #include <linux/i2c/panjit_ts.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/i2c-tegra.h>
33 #include <linux/gpio.h>
34 #include <linux/input.h>
35 #include <linux/platform_data/tegra_usb.h>
36 #include <linux/spi/spi.h>
37 #include <linux/i2c/atmel_mxt_ts.h>
38 #include <linux/tegra_uart.h>
39 #include <linux/memblock.h>
40 #include <linux/spi-tegra.h>
41 #include <linux/nfc/pn544.h>
42
43 #include <sound/wm8903.h>
44 #include <sound/max98095.h>
45 #include <media/tegra_dtv.h>
46
47 #include <asm/hardware/gic.h>
48
49 #include <mach/clk.h>
50 #include <mach/iomap.h>
51 #include <mach/irqs.h>
52 #include <mach/pinmux.h>
53 #include <mach/iomap.h>
54 #include <mach/io.h>
55 #include <mach/i2s.h>
56 #include <mach/tegra_asoc_pdata.h>
57 #include <mach/tegra_wm8903_pdata.h>
58 #include <asm/mach-types.h>
59 #include <asm/mach/arch.h>
60 #include <mach/usb_phy.h>
61 #include <mach/thermal.h>
62 #include <mach/pci.h>
63 #include <mach/gpio-tegra.h>
64
65 #include "board.h"
66 #include "clock.h"
67 #include "board-cardhu.h"
68 #include "board-touch.h"
69 #include "devices.h"
70 #include "gpio-names.h"
71 #include "fuse.h"
72 #include "pm.h"
73 #include "baseband-xmm-power.h"
74 #include "wdt-recovery.h"
75
76 /* All units are in millicelsius */
77 static struct tegra_thermal_data thermal_data = {
78         .temp_shutdown = 90000,
79         .temp_offset = TDIODE_OFFSET, /* temps based on tdiode */
80 #ifdef CONFIG_TEGRA_EDP_LIMITS
81         .edp_offset = TDIODE_OFFSET,  /* edp based on tdiode */
82         .hysteresis_edp = 3000,
83 #endif
84 #ifdef CONFIG_TEGRA_THERMAL_THROTTLE
85         .temp_throttle = 85000,
86         .tc1 = 0,
87         .tc2 = 1,
88         .passive_delay = 2000,
89 #endif
90 };
91
92 static struct resource cardhu_bcm4329_rfkill_resources[] = {
93         {
94                 .name   = "bcm4329_nshutdown_gpio",
95                 .start  = TEGRA_GPIO_PU0,
96                 .end    = TEGRA_GPIO_PU0,
97                 .flags  = IORESOURCE_IO,
98         },
99 };
100
101 static struct platform_device cardhu_bcm4329_rfkill_device = {
102         .name = "bcm4329_rfkill",
103         .id             = -1,
104         .num_resources  = ARRAY_SIZE(cardhu_bcm4329_rfkill_resources),
105         .resource       = cardhu_bcm4329_rfkill_resources,
106 };
107
108 static struct resource cardhu_bluesleep_resources[] = {
109         [0] = {
110                 .name = "gpio_host_wake",
111                         .start  = TEGRA_GPIO_PU6,
112                         .end    = TEGRA_GPIO_PU6,
113                         .flags  = IORESOURCE_IO,
114         },
115         [1] = {
116                 .name = "gpio_ext_wake",
117                         .start  = TEGRA_GPIO_PU1,
118                         .end    = TEGRA_GPIO_PU1,
119                         .flags  = IORESOURCE_IO,
120         },
121         [2] = {
122                 .name = "host_wake",
123                         .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
124         },
125 };
126
127 static struct platform_device cardhu_bluesleep_device = {
128         .name           = "bluesleep",
129         .id             = -1,
130         .num_resources  = ARRAY_SIZE(cardhu_bluesleep_resources),
131         .resource       = cardhu_bluesleep_resources,
132 };
133
134 static noinline void __init cardhu_setup_bluesleep(void)
135 {
136         cardhu_bluesleep_resources[2].start =
137                 cardhu_bluesleep_resources[2].end =
138                         gpio_to_irq(TEGRA_GPIO_PU6);
139         platform_device_register(&cardhu_bluesleep_device);
140         return;
141 }
142
143 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
144         /* name         parent          rate            enabled */
145         { "pll_m",      NULL,           0,              false},
146         { "hda",        "pll_p",        108000000,      false},
147         { "hda2codec_2x","pll_p",       48000000,       false},
148         { "pwm",        "pll_p",        3187500,        false},
149         { "blink",      "clk_32k",      32768,          true},
150         { "i2s0",       "pll_a_out0",   0,              false},
151         { "i2s1",       "pll_a_out0",   0,              false},
152         { "i2s3",       "pll_a_out0",   0,              false},
153         { "spdif_out",  "pll_a_out0",   0,              false},
154         { "d_audio",    "clk_m",        12000000,       false},
155         { "dam0",       "clk_m",        12000000,       false},
156         { "dam1",       "clk_m",        12000000,       false},
157         { "dam2",       "clk_m",        12000000,       false},
158         { "audio1",     "i2s1_sync",    0,              false},
159         { "audio3",     "i2s3_sync",    0,              false},
160         { "vi_sensor",  "pll_p",        150000000,      false},
161         { "i2c1",       "pll_p",        3200000,        false},
162         { "i2c2",       "pll_p",        3200000,        false},
163         { "i2c3",       "pll_p",        3200000,        false},
164         { "i2c4",       "pll_p",        3200000,        false},
165         { "i2c5",       "pll_p",        3200000,        false},
166         { NULL,         NULL,           0,              0},
167 };
168
169 static struct pn544_i2c_platform_data nfc_pdata = {
170         .irq_gpio = TEGRA_GPIO_PX0,
171         .ven_gpio = TEGRA_GPIO_PP3,
172         .firm_gpio = TEGRA_GPIO_PO7,
173         };
174
175 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
176         {
177                 I2C_BOARD_INFO("pn544", 0x28),
178                 .platform_data = &nfc_pdata,
179         },
180 };
181 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
182         .adapter_nr     = 0,
183         .bus_count      = 1,
184         .bus_clk_rate   = { 100000, 0 },
185         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
186         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
187         .arb_recovery = arb_lost_recovery,
188 };
189
190 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
191         .adapter_nr     = 1,
192         .bus_count      = 1,
193         .bus_clk_rate   = { 400000, 0 },
194         .is_clkon_always = true,
195         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
196         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
197         .arb_recovery = arb_lost_recovery,
198 };
199
200 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
201         .adapter_nr     = 2,
202         .bus_count      = 1,
203         .bus_clk_rate   = { 100000, 0 },
204         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
205         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
206         .arb_recovery = arb_lost_recovery,
207 };
208
209 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
210         .adapter_nr     = 3,
211         .bus_count      = 1,
212         .bus_clk_rate   = { 10000, 0 },
213         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
214         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
215         .arb_recovery = arb_lost_recovery,
216 };
217
218 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
219         .adapter_nr     = 4,
220         .bus_count      = 1,
221         .bus_clk_rate   = { 400000, 0 },
222         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
223         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
224         .arb_recovery = arb_lost_recovery,
225 };
226
227
228 #if 0
229 struct tegra_wired_jack_conf audio_wr_jack_conf = {
230         .hp_det_n = TEGRA_GPIO_PW2,
231         .en_mic_ext = TEGRA_GPIO_PX1,
232         .en_mic_int = TEGRA_GPIO_PX0,
233 };
234 #endif
235
236 static struct wm8903_platform_data cardhu_wm8903_pdata = {
237         .irq_active_low = 0,
238         .micdet_cfg = 0,
239         .micdet_delay = 100,
240         .gpio_base = CARDHU_GPIO_WM8903(0),
241         .gpio_cfg = {
242                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
243                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
244                         WM8903_GP2_DIR,
245                 WM8903_GPIO_CONFIG_ZERO,
246                 0,
247                 0,
248         },
249 };
250
251 /* Equalizer filter coefs generated from the MAXIM MAX98095
252  * evkit software tool */
253 static struct max98095_eq_cfg max98095_eq_cfg[] = {
254         {
255                 .name = "FLAT",
256                 .rate = 44100,
257                 .band1 = {0x2000, 0xC002, 0x4000, 0x00E9, 0x0000},
258                 .band2 = {0x2000, 0xC00F, 0x4000, 0x02BC, 0x0000},
259                 .band3 = {0x2000, 0xC0A7, 0x4000, 0x0916, 0x0000},
260                 .band4 = {0x2000, 0xC5C2, 0x4000, 0x1A87, 0x0000},
261                 .band5 = {0x2000, 0xF6B0, 0x4000, 0x3F51, 0x0000},
262         },
263         {
264                 .name = "LOWPASS1K",
265                 .rate = 44100,
266                 .band1 = {0x205D, 0xC001, 0x3FEF, 0x002E, 0x02E0},
267                 .band2 = {0x5B9A, 0xC093, 0x3AB2, 0x088B, 0x1981},
268                 .band3 = {0x0D22, 0xC170, 0x26EA, 0x0D79, 0x32CF},
269                 .band4 = {0x0894, 0xC612, 0x01B3, 0x1B34, 0x3FFA},
270                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
271         },
272         { /* BASS=-12dB, TREBLE=+9dB, Fc=5KHz */
273                 .name = "HIBOOST",
274                 .rate = 44100,
275                 .band1 = {0x0815, 0xC001, 0x3AA4, 0x0003, 0x19A2},
276                 .band2 = {0x0815, 0xC103, 0x092F, 0x0B55, 0x3F56},
277                 .band3 = {0x0E0A, 0xC306, 0x1E5C, 0x136E, 0x3856},
278                 .band4 = {0x2459, 0xF665, 0x0CAA, 0x3F46, 0x3EBB},
279                 .band5 = {0x5BBB, 0x3FFF, 0xCEB0, 0x0000, 0x28CA},
280         },
281         { /* BASS=12dB, TREBLE=+12dB */
282                 .name = "LOUD12DB",
283                 .rate = 44100,
284                 .band1 = {0x7FC1, 0xC001, 0x3EE8, 0x0020, 0x0BC7},
285                 .band2 = {0x51E9, 0xC016, 0x3C7C, 0x033F, 0x14E9},
286                 .band3 = {0x1745, 0xC12C, 0x1680, 0x0C2F, 0x3BE9},
287                 .band4 = {0x4536, 0xD7E2, 0x0ED4, 0x31DD, 0x3E42},
288                 .band5 = {0x7FEF, 0x3FFF, 0x0BAB, 0x0000, 0x3EED},
289         },
290         {
291                 .name = "FLAT",
292                 .rate = 16000,
293                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
294                 .band2 = {0x2000, 0xC033, 0x4000, 0x0505, 0x0000},
295                 .band3 = {0x2000, 0xC268, 0x4000, 0x115F, 0x0000},
296                 .band4 = {0x2000, 0xDA62, 0x4000, 0x33C6, 0x0000},
297                 .band5 = {0x2000, 0x4000, 0x4000, 0x0000, 0x0000},
298         },
299         {
300                 .name = "LOWPASS1K",
301                 .rate = 16000,
302                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
303                 .band2 = {0x5BE8, 0xC3E0, 0x3307, 0x15ED, 0x26A0},
304                 .band3 = {0x0F71, 0xD15A, 0x08B3, 0x2BD0, 0x3F67},
305                 .band4 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
306                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
307         },
308         { /* BASS=-12dB, TREBLE=+9dB, Fc=2KHz */
309                 .name = "HIBOOST",
310                 .rate = 16000,
311                 .band1 = {0x0815, 0xC001, 0x3BD2, 0x0009, 0x16BF},
312                 .band2 = {0x080E, 0xC17E, 0xF653, 0x0DBD, 0x3F43},
313                 .band3 = {0x0F80, 0xDF45, 0xEE33, 0x36FE, 0x3D79},
314                 .band4 = {0x590B, 0x3FF0, 0xE882, 0x02BD, 0x3B87},
315                 .band5 = {0x4C87, 0xF3D0, 0x063F, 0x3ED4, 0x3FB1},
316         },
317         { /* BASS=12dB, TREBLE=+12dB */
318                 .name = "LOUD12DB",
319                 .rate = 16000,
320                 .band1 = {0x7FC1, 0xC001, 0x3D07, 0x0058, 0x1344},
321                 .band2 = {0x2DA6, 0xC013, 0x3CF1, 0x02FF, 0x138B},
322                 .band3 = {0x18F1, 0xC08E, 0x244D, 0x0863, 0x34B5},
323                 .band4 = {0x2BE0, 0xF385, 0x04FD, 0x3EC5, 0x3FCE},
324                 .band5 = {0x7FEF, 0x4000, 0x0BAB, 0x0000, 0x3EED},
325         },
326 };
327
328 static struct max98095_pdata cardhu_max98095_pdata = {
329         /* equalizer configuration */
330         .eq_cfg = max98095_eq_cfg,
331         .eq_cfgcnt = ARRAY_SIZE(max98095_eq_cfg),
332
333         /* Biquad filter response configuration */
334         .bq_cfg = NULL,
335         .bq_cfgcnt = 0,
336
337         /* microphone configuration */
338         .digmic_left_mode = 1,
339         .digmic_right_mode = 1,
340 };
341
342 static struct i2c_board_info __initdata cardhu_codec_wm8903_info = {
343         I2C_BOARD_INFO("wm8903", 0x1a),
344         .platform_data = &cardhu_wm8903_pdata,
345 };
346
347 static struct i2c_board_info __initdata cardhu_codec_aic326x_info = {
348         I2C_BOARD_INFO("aic3262-codec", 0x18),
349 };
350
351 static struct i2c_board_info __initdata cardhu_codec_max98095_info = {
352         I2C_BOARD_INFO("max98095", 0x10),
353         .platform_data = &cardhu_max98095_pdata,
354 };
355
356 static void cardhu_i2c_init(void)
357 {
358         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
359         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
360         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
361         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
362         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
363
364         platform_device_register(&tegra_i2c_device5);
365         platform_device_register(&tegra_i2c_device4);
366         platform_device_register(&tegra_i2c_device3);
367         platform_device_register(&tegra_i2c_device2);
368         platform_device_register(&tegra_i2c_device1);
369
370         cardhu_codec_wm8903_info.irq = cardhu_codec_max98095_info.irq =
371                 cardhu_codec_aic326x_info.irq = gpio_to_irq(TEGRA_GPIO_CDC_IRQ);
372         i2c_register_board_info(4, &cardhu_codec_wm8903_info, 1);
373         i2c_register_board_info(4, &cardhu_codec_max98095_info, 1);
374         i2c_register_board_info(4, &cardhu_codec_aic326x_info, 1);
375
376         cardhu_i2c_bus3_board_info[0].irq = gpio_to_irq(TEGRA_GPIO_PX0);
377         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
378 }
379
380 static struct platform_device *cardhu_uart_devices[] __initdata = {
381         &tegra_uarta_device,
382         &tegra_uartb_device,
383         &tegra_uartc_device,
384         &tegra_uartd_device,
385         &tegra_uarte_device,
386 };
387 static struct uart_clk_parent uart_parent_clk[] = {
388         [0] = {.name = "clk_m"},
389         [1] = {.name = "pll_p"},
390 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
391         [2] = {.name = "pll_m"},
392 #endif
393 };
394
395 static struct tegra_uart_platform_data cardhu_uart_pdata;
396 static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
397
398 static void __init uart_debug_init(void)
399 {
400         struct board_info board_info;
401         int debug_port_id;
402
403         tegra_get_board_info(&board_info);
404
405         debug_port_id = get_tegra_uart_debug_port_id();
406         if (debug_port_id < 0) {
407                 debug_port_id = 0;
408                         /* UARTB is debug port
409                          *       for SLT - E1186/E1187/PM269
410                          *       for E1256/E1257
411                          */
412                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
413                         ((board_info.board_id == BOARD_E1186) ||
414                         (board_info.board_id == BOARD_E1187) ||
415                         (board_info.board_id == BOARD_PM269))) ||
416                         (board_info.board_id == BOARD_E1256) ||
417                         (board_info.board_id == BOARD_E1257))
418                                 debug_port_id = 1;
419         }
420
421         switch (debug_port_id) {
422         case 0:
423                 /* UARTA is the debug port. */
424                 pr_info("Selecting UARTA as the debug console\n");
425                 cardhu_uart_devices[0] = &debug_uarta_device;
426                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
427                 debug_uart_port_base = ((struct plat_serial8250_port *)(
428                         debug_uarta_device.dev.platform_data))->mapbase;
429                 break;
430
431         case 1:
432                 /* UARTB is the debug port. */
433                 pr_info("Selecting UARTB as the debug console\n");
434                 cardhu_uart_devices[1] = &debug_uartb_device;
435                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
436                 debug_uart_port_base = ((struct plat_serial8250_port *)(
437                         debug_uartb_device.dev.platform_data))->mapbase;
438                 break;
439
440         case 2:
441                 /* UARTC is the debug port. */
442                 pr_info("Selecting UARTC as the debug console\n");
443                 cardhu_uart_devices[2] = &debug_uartc_device;
444                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
445                 debug_uart_port_base = ((struct plat_serial8250_port *)(
446                         debug_uartc_device.dev.platform_data))->mapbase;
447                 break;
448
449         case 3:
450                 /* UARTD is the debug port. */
451                 pr_info("Selecting UARTD as the debug console\n");
452                 cardhu_uart_devices[3] = &debug_uartd_device;
453                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
454                 debug_uart_port_base = ((struct plat_serial8250_port *)(
455                         debug_uartd_device.dev.platform_data))->mapbase;
456                 break;
457
458         case 4:
459                 /* UARTE is the debug port. */
460                 pr_info("Selecting UARTE as the debug console\n");
461                 cardhu_uart_devices[4] = &debug_uarte_device;
462                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
463                 debug_uart_port_base = ((struct plat_serial8250_port *)(
464                         debug_uarte_device.dev.platform_data))->mapbase;
465                 break;
466
467         default:
468                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
469                 cardhu_uart_devices[0] = &debug_uarta_device;
470                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
471                 debug_uart_port_base = ((struct plat_serial8250_port *)(
472                         debug_uarta_device.dev.platform_data))->mapbase;
473                 break;
474         }
475         return;
476 }
477
478 static void __init cardhu_uart_init(void)
479 {
480         struct clk *c;
481         int i;
482
483         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
484                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
485                 if (IS_ERR_OR_NULL(c)) {
486                         pr_err("Not able to get the clock for %s\n",
487                                                 uart_parent_clk[i].name);
488                         continue;
489                 }
490                 uart_parent_clk[i].parent_clk = c;
491                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
492         }
493         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
494         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
495         cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
496         cardhu_loopback_uart_pdata.parent_clk_count =
497                                                 ARRAY_SIZE(uart_parent_clk);
498         cardhu_loopback_uart_pdata.is_loopback = true;
499         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
500         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
501         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
502         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
503         /* UARTE is used for loopback test purpose */
504         tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
505
506         /* Register low speed only if it is selected */
507         if (!is_tegra_debug_uartport_hs()) {
508                 uart_debug_init();
509                 /* Clock enable for the debug channel */
510                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
511                         pr_info("The debug console clock name is %s\n",
512                                                 debug_uart_clk->name);
513                         c = tegra_get_clock_by_name("pll_p");
514                         if (IS_ERR_OR_NULL(c))
515                                 pr_err("Not getting the parent clock pll_p\n");
516                         else
517                                 clk_set_parent(debug_uart_clk, c);
518
519                         clk_enable(debug_uart_clk);
520                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
521                 } else {
522                         pr_err("Not getting the clock %s for debug console\n",
523                                         debug_uart_clk->name);
524                 }
525         }
526
527         platform_add_devices(cardhu_uart_devices,
528                                 ARRAY_SIZE(cardhu_uart_devices));
529 }
530
531 static struct platform_device tegra_camera = {
532         .name = "tegra_camera",
533         .id = -1,
534 };
535
536 static struct platform_device *cardhu_spi_devices[] __initdata = {
537         &tegra_spi_device4,
538 };
539
540 static struct platform_device *touch_spi_device[] __initdata = {
541         &tegra_spi_device1,
542 };
543
544 struct spi_clk_parent spi_parent_clk[] = {
545         [0] = {.name = "pll_p"},
546 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
547         [1] = {.name = "pll_m"},
548         [2] = {.name = "clk_m"},
549 #else
550         [1] = {.name = "clk_m"},
551 #endif
552 };
553
554 static struct tegra_spi_platform_data cardhu_spi_pdata = {
555         .is_dma_based           = true,
556         .max_dma_buffer         = (16 * 1024),
557         .is_clkon_always        = false,
558         .max_rate               = 100000000,
559 };
560
561 static void __init cardhu_spi_init(void)
562 {
563         int i;
564         struct clk *c;
565         struct board_info board_info, display_board_info;
566
567         tegra_get_board_info(&board_info);
568         tegra_get_display_board_info(&display_board_info);
569
570         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
571                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
572                 if (IS_ERR_OR_NULL(c)) {
573                         pr_err("Not able to get the clock for %s\n",
574                                                 spi_parent_clk[i].name);
575                         continue;
576                 }
577                 spi_parent_clk[i].parent_clk = c;
578                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
579         }
580         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
581         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
582         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
583         platform_add_devices(cardhu_spi_devices,
584                                 ARRAY_SIZE(cardhu_spi_devices));
585
586         if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
587                 platform_add_devices(touch_spi_device,
588                                 ARRAY_SIZE(touch_spi_device));
589         }
590         if (board_info.board_id == BOARD_E1198) {
591                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
592                 platform_device_register(&tegra_spi_device2);
593                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
594                 platform_device_register(&tegra_spi_slave_device1);
595         }
596 }
597
598 static void __init cardhu_dtv_init(void)
599 {
600         struct board_info board_info;
601
602         tegra_get_board_info(&board_info);
603
604         if (board_info.board_id == BOARD_E1186)
605                 platform_device_register(&tegra_dtv_device);
606 }
607
608 static struct resource tegra_rtc_resources[] = {
609         [0] = {
610                 .start = TEGRA_RTC_BASE,
611                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
612                 .flags = IORESOURCE_MEM,
613         },
614         [1] = {
615                 .start = INT_RTC,
616                 .end = INT_RTC,
617                 .flags = IORESOURCE_IRQ,
618         },
619 };
620
621 static struct platform_device tegra_rtc_device = {
622         .name = "tegra_rtc",
623         .id   = -1,
624         .resource = tegra_rtc_resources,
625         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
626 };
627
628 static struct tegra_wm8903_platform_data cardhu_audio_wm8903_pdata = {
629         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
630         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
631         .gpio_hp_mute           = -1,
632         .gpio_int_mic_en        = -1,
633         .gpio_ext_mic_en        = -1,
634 };
635
636 static struct tegra_asoc_platform_data cardhu_audio_max98095_pdata = {
637         .gpio_spkr_en           = -1,
638         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
639         .gpio_hp_mute           = -1,
640         .gpio_int_mic_en        = -1,
641         .gpio_ext_mic_en        = -1,
642 };
643
644 static struct platform_device cardhu_audio_wm8903_device = {
645         .name   = "tegra-snd-wm8903",
646         .id     = 0,
647         .dev    = {
648                 .platform_data = &cardhu_audio_wm8903_pdata,
649         },
650 };
651
652 static struct platform_device cardhu_audio_max98095_device = {
653         .name   = "tegra-snd-max98095",
654         .id     = 0,
655         .dev    = {
656                 .platform_data = &cardhu_audio_max98095_pdata,
657         },
658 };
659
660 static struct tegra_asoc_platform_data cardhu_audio_aic326x_pdata = {
661         .gpio_spkr_en           = -1,
662         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
663         .gpio_hp_mute           = -1,
664         .gpio_int_mic_en        = -1,
665         .gpio_ext_mic_en        = -1,
666         /*defaults for Verbier-Cardhu board with TI AIC326X codec*/
667         .audio_port_id          = {
668                 [HIFI_CODEC] = 0,
669                 [BASEBAND] = -1,
670                 [BT_SCO] = 3,
671         },
672         .baseband_param         = {
673                 .rate = -1,
674                 .channels = -1,
675         },
676 };
677
678 static struct platform_device cardhu_audio_aic326x_device = {
679         .name   = "tegra-snd-aic326x",
680         .id     = 0,
681         .dev    = {
682                 .platform_data  = &cardhu_audio_aic326x_pdata,
683         },
684 };
685
686 static struct platform_device *cardhu_devices[] __initdata = {
687         &tegra_pmu_device,
688         &tegra_rtc_device,
689         &tegra_udc_device,
690 #if defined(CONFIG_TEGRA_IOVMM_SMMU) ||  defined(CONFIG_TEGRA_IOMMU_SMMU)
691         &tegra_smmu_device,
692 #endif
693         &tegra_wdt_device,
694 #if defined(CONFIG_TEGRA_AVP)
695         &tegra_avp_device,
696 #endif
697         &tegra_camera,
698 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
699         &tegra_se_device,
700 #endif
701         &tegra_ahub_device,
702         &tegra_dam_device0,
703         &tegra_dam_device1,
704         &tegra_dam_device2,
705         &tegra_i2s_device0,
706         &tegra_i2s_device1,
707         &tegra_i2s_device3,
708         &tegra_spdif_device,
709         &spdif_dit_device,
710         &bluetooth_dit_device,
711         &baseband_dit_device,
712         &cardhu_bcm4329_rfkill_device,
713         &tegra_pcm_device,
714         &cardhu_audio_wm8903_device,
715         &cardhu_audio_max98095_device,
716         &cardhu_audio_aic326x_device,
717         &tegra_hda_device,
718 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
719         &tegra_aes_device,
720 #endif
721 };
722
723 #define MXT_CONFIG_CRC  0xD62DE8
724 static const u8 config[] = {
725         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
726         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
727         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
728         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
729         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
730         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
731         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
732         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
733         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
734         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
735         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
736         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
737         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
738         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
739         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
740         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
741         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
742         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
743         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
744         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
745 };
746
747 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
748 static const u8 config_sku2000[] = {
749         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
750         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
751         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
752         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
753         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
754         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
755         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
756         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
757         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
758         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
759         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
760         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
761         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
762         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
763         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
764         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
765         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
766         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
767         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
768         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
769 };
770
771 static struct mxt_platform_data atmel_mxt_info = {
772         .x_line         = 27,
773         .y_line         = 42,
774         .x_size         = 768,
775         .y_size         = 1366,
776         .blen           = 0x20,
777         .threshold      = 0x3C,
778         .voltage        = 3300000,              /* 3.3V */
779         .orient         = 5,
780         .config         = config,
781         .config_length  = 157,
782         .config_crc     = MXT_CONFIG_CRC,
783         .irqflags       = IRQF_TRIGGER_FALLING,
784 /*      .read_chg       = &read_chg, */
785         .read_chg       = NULL,
786 };
787
788 static struct i2c_board_info __initdata atmel_i2c_info[] = {
789         {
790                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
791                 .platform_data = &atmel_mxt_info,
792         }
793 };
794
795 static __initdata struct tegra_clk_init_table spi_clk_init_table[] = {
796         /* name         parent          rate            enabled */
797         { "sbc1",       "pll_p",        52000000,       true},
798         { NULL,         NULL,           0,              0},
799 };
800
801 static int __init cardhu_touch_init(void)
802 {
803         struct board_info BoardInfo;
804
805         tegra_get_display_board_info(&BoardInfo);
806         if (BoardInfo.board_id == BOARD_DISPLAY_PM313) {
807                 tegra_clk_init_from_table(spi_clk_init_table);
808
809                 touch_init_raydium(TEGRA_GPIO_PH4, TEGRA_GPIO_PH6, 2);
810         } else {
811                 gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
812                 gpio_direction_input(TEGRA_GPIO_PH4);
813
814                 gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
815                 gpio_direction_output(TEGRA_GPIO_PH6, 0);
816                 msleep(1);
817                 gpio_set_value(TEGRA_GPIO_PH6, 1);
818                 msleep(100);
819
820                 tegra_get_board_info(&BoardInfo);
821                 if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
822                         atmel_mxt_info.config = config_sku2000;
823                         atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
824                 }
825
826                 atmel_i2c_info[0].irq = gpio_to_irq(TEGRA_GPIO_PH4);
827                 i2c_register_board_info(1, atmel_i2c_info, 1);
828         }
829
830         return 0;
831 }
832
833 static void cardu_usb_hsic_postsupend(void)
834 {
835 #ifdef CONFIG_TEGRA_BB_XMM_POWER
836         baseband_xmm_set_power_status(BBXMM_PS_L2);
837 #endif
838 }
839
840 static void cardu_usb_hsic_preresume(void)
841 {
842 #ifdef CONFIG_TEGRA_BB_XMM_POWER
843         baseband_xmm_set_power_status(BBXMM_PS_L2TOL0);
844 #endif
845 }
846
847 static void cardu_usb_hsic_phy_ready(void)
848 {
849 #ifdef CONFIG_TEGRA_BB_XMM_POWER
850         baseband_xmm_set_power_status(BBXMM_PS_L0);
851 #endif
852 }
853
854 static void cardu_usb_hsic_phy_off(void)
855 {
856 #ifdef CONFIG_TEGRA_BB_XMM_POWER
857         baseband_xmm_set_power_status(BBXMM_PS_L3);
858 #endif
859 }
860
861 static struct tegra_usb_phy_platform_ops hsic_xmm_plat_ops = {
862         .post_suspend = cardu_usb_hsic_postsupend,
863         .pre_resume = cardu_usb_hsic_preresume,
864         .port_power = cardu_usb_hsic_phy_ready,
865         .post_phy_off = cardu_usb_hsic_phy_off,
866 };
867
868 static struct tegra_usb_platform_data tegra_ehci2_hsic_xmm_pdata = {
869         .port_otg = false,
870         .has_hostpc = true,
871         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
872         .op_mode        = TEGRA_USB_OPMODE_HOST,
873         .u_data.host = {
874                 .vbus_gpio = -1,
875                 .hot_plug = false,
876                 .remote_wakeup_supported = false,
877                 .power_off_on_suspend = false,
878         },
879         .u_cfg.hsic = {
880                 .sync_start_delay = 9,
881                 .idle_wait_delay = 17,
882                 .term_range_adj = 0,
883                 .elastic_underrun_limit = 16,
884                 .elastic_overrun_limit = 16,
885         },
886         .ops = &hsic_xmm_plat_ops,
887 };
888
889
890 static int hsic_enable_gpio = -1;
891 static int hsic_reset_gpio = -1;
892
893 void hsic_platform_open(void)
894 {
895         int reset_gpio = 0, enable_gpio = 0;
896
897         if (hsic_enable_gpio != -1)
898                 enable_gpio = gpio_request(hsic_enable_gpio, "uhsic_enable");
899         if (hsic_reset_gpio != -1)
900                 reset_gpio = gpio_request(hsic_reset_gpio, "uhsic_reset");
901         /* hsic enable signal deasserted, hsic reset asserted */
902         if (!enable_gpio)
903                 gpio_direction_output(hsic_enable_gpio, 0 /* deasserted */);
904         if (!reset_gpio)
905                 gpio_direction_output(hsic_reset_gpio, 0 /* asserted */);
906         if (!enable_gpio)
907                 tegra_gpio_enable(hsic_enable_gpio);
908         if (!reset_gpio)
909                 tegra_gpio_enable(hsic_reset_gpio);
910         /* keep hsic reset asserted for 1 ms */
911         udelay(1000);
912         /* enable (power on) hsic */
913         if (!enable_gpio)
914                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
915         udelay(1000);
916         /* deassert reset */
917         if (!reset_gpio)
918                 gpio_set_value_cansleep(hsic_reset_gpio, 1);
919
920 }
921
922 void hsic_platform_close(void)
923 {
924         if (hsic_enable_gpio != -1) {
925                 gpio_set_value(hsic_enable_gpio, 0);
926                 gpio_free(hsic_enable_gpio);
927         }
928         if (hsic_reset_gpio != -1) {
929                 gpio_set_value(hsic_reset_gpio, 0);
930                 gpio_free(hsic_reset_gpio);
931         }
932 }
933
934 void hsic_power_on(void)
935 {
936         if (hsic_enable_gpio != -1) {
937                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
938                 udelay(1000);
939         }
940 }
941
942 void hsic_power_off(void)
943 {
944         if (hsic_enable_gpio != -1) {
945                 gpio_set_value_cansleep(hsic_enable_gpio, 0);
946                 udelay(1000);
947         }
948 }
949
950 static struct tegra_usb_phy_platform_ops hsic_plat_ops = {
951         .open = hsic_platform_open,
952         .close = hsic_platform_close,
953         .pre_phy_on = hsic_power_on,
954         .post_phy_off = hsic_power_off,
955 };
956
957 static struct tegra_usb_platform_data tegra_ehci2_hsic_pdata = {
958         .port_otg = false,
959         .has_hostpc = true,
960         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
961         .op_mode        = TEGRA_USB_OPMODE_HOST,
962         .u_data.host = {
963                 .vbus_gpio = -1,
964                 .hot_plug = false,
965                 .remote_wakeup_supported = false,
966                 .power_off_on_suspend = false,
967         },
968         .u_cfg.hsic = {
969                 .sync_start_delay = 9,
970                 .idle_wait_delay = 17,
971                 .term_range_adj = 0,
972                 .elastic_underrun_limit = 16,
973                 .elastic_overrun_limit = 16,
974         },
975         .ops = &hsic_plat_ops,
976 };
977
978 static struct tegra_usb_platform_data tegra_udc_pdata = {
979         .port_otg = true,
980         .has_hostpc = true,
981         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
982         .op_mode = TEGRA_USB_OPMODE_DEVICE,
983         .u_data.dev = {
984                 .vbus_pmu_irq = 0,
985                 .vbus_gpio = -1,
986                 .charging_supported = false,
987                 .remote_wakeup_supported = false,
988         },
989         .u_cfg.utmi = {
990                 .hssync_start_delay = 0,
991                 .elastic_limit = 16,
992                 .idle_wait_delay = 17,
993                 .term_range_adj = 6,
994                 .xcvr_setup = 8,
995                 .xcvr_lsfslew = 2,
996                 .xcvr_lsrslew = 2,
997                 .xcvr_setup_offset = 0,
998                 .xcvr_use_fuses = 1,
999         },
1000 };
1001
1002 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
1003         .port_otg = true,
1004         .has_hostpc = true,
1005         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1006         .op_mode = TEGRA_USB_OPMODE_HOST,
1007         .u_data.host = {
1008                 .vbus_gpio = -1,
1009                 .vbus_reg = "vdd_vbus_micro_usb",
1010                 .hot_plug = true,
1011                 .remote_wakeup_supported = true,
1012                 .power_off_on_suspend = true,
1013         },
1014         .u_cfg.utmi = {
1015                 .hssync_start_delay = 0,
1016                 .elastic_limit = 16,
1017                 .idle_wait_delay = 17,
1018                 .term_range_adj = 6,
1019                 .xcvr_setup = 15,
1020                 .xcvr_lsfslew = 2,
1021                 .xcvr_lsrslew = 2,
1022                 .xcvr_setup_offset = 0,
1023                 .xcvr_use_fuses = 1,
1024         },
1025 };
1026
1027 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
1028         .port_otg = false,
1029         .has_hostpc = true,
1030         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1031         .op_mode        = TEGRA_USB_OPMODE_HOST,
1032         .u_data.host = {
1033                 .vbus_gpio = -1,
1034                 .hot_plug = false,
1035                 .remote_wakeup_supported = true,
1036                 .power_off_on_suspend = true,
1037         },
1038         .u_cfg.utmi = {
1039                 .hssync_start_delay = 0,
1040                 .elastic_limit = 16,
1041                 .idle_wait_delay = 17,
1042                 .term_range_adj = 6,
1043                 .xcvr_setup = 15,
1044                 .xcvr_lsfslew = 2,
1045                 .xcvr_lsrslew = 2,
1046                 .xcvr_setup_offset = 0,
1047                 .xcvr_use_fuses = 1,
1048         },
1049 };
1050
1051 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
1052         .port_otg = false,
1053         .has_hostpc = true,
1054         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1055         .op_mode        = TEGRA_USB_OPMODE_HOST,
1056         .u_data.host = {
1057                 .vbus_gpio = -1,
1058                 .vbus_reg = "vdd_vbus_typea_usb",
1059                 .hot_plug = true,
1060                 .remote_wakeup_supported = true,
1061                 .power_off_on_suspend = true,
1062         },
1063         .u_cfg.utmi = {
1064                 .hssync_start_delay = 0,
1065                 .elastic_limit = 16,
1066                 .idle_wait_delay = 17,
1067                 .term_range_adj = 6,
1068                 .xcvr_setup = 8,
1069                 .xcvr_lsfslew = 2,
1070                 .xcvr_lsrslew = 2,
1071                 .xcvr_setup_offset = 0,
1072                 .xcvr_use_fuses = 1,
1073         },
1074 };
1075
1076 static struct tegra_usb_otg_data tegra_otg_pdata = {
1077         .ehci_device = &tegra_ehci1_device,
1078         .ehci_pdata = &tegra_ehci1_utmi_pdata,
1079 };
1080
1081 #if CONFIG_USB_SUPPORT
1082 static void cardhu_usb_init(void)
1083 {
1084         struct board_info bi;
1085
1086         tegra_get_board_info(&bi);
1087
1088         /* OTG should be the first to be registered */
1089         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
1090         platform_device_register(&tegra_otg_device);
1091
1092         /* setup the udc platform data */
1093         tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
1094
1095         if (bi.board_id == BOARD_PM267) {
1096                 hsic_enable_gpio = EN_HSIC_GPIO;
1097                 hsic_reset_gpio = PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
1098                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1099                 platform_device_register(&tegra_ehci2_device);
1100         } else if (bi.board_id == BOARD_E1256) {
1101                 hsic_enable_gpio = EN_HSIC_GPIO;
1102                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1103                 platform_device_register(&tegra_ehci2_device);
1104         } else if (bi.board_id == BOARD_E1186) {
1105                 tegra_ehci2_device.dev.platform_data =
1106                                                 &tegra_ehci2_hsic_xmm_pdata;
1107                 /* ehci2 registration happens in baseband-xmm-power  */
1108         } else {
1109                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata;
1110                 platform_device_register(&tegra_ehci2_device);
1111         }
1112
1113         tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
1114         platform_device_register(&tegra_ehci3_device);
1115
1116 }
1117 #else
1118 static void cardhu_usb_init(void) { }
1119 #endif
1120
1121 static struct baseband_power_platform_data tegra_baseband_power_data = {
1122         .baseband_type = BASEBAND_XMM,
1123         .modem = {
1124         .xmm = {
1125                         .bb_rst = XMM_GPIO_BB_RST,
1126                         .bb_on = XMM_GPIO_BB_ON,
1127                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
1128                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
1129                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
1130                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
1131                         .hsic_device = &tegra_ehci2_device,
1132                 },
1133         },
1134 };
1135
1136 static struct platform_device tegra_baseband_power_device = {
1137         .name = "baseband_xmm_power",
1138         .id = -1,
1139         .dev = {
1140                 .platform_data = &tegra_baseband_power_data,
1141         },
1142 };
1143
1144 static struct platform_device tegra_baseband_power2_device = {
1145         .name = "baseband_xmm_power2",
1146         .id = -1,
1147         .dev = {
1148                 .platform_data = &tegra_baseband_power_data,
1149         },
1150 };
1151
1152
1153 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
1154         .port_status[0] = 1,
1155         .port_status[1] = 1,
1156         .port_status[2] = 1,
1157         .use_dock_detect        = 0,
1158         .gpio           = 0,
1159 };
1160
1161 static void cardhu_pci_init(void)
1162 {
1163         struct board_info board_info;
1164
1165         tegra_get_board_info(&board_info);
1166         if (board_info.board_id == BOARD_E1291) {
1167                 cardhu_pci_platform_data.port_status[0] = 0;
1168                 cardhu_pci_platform_data.port_status[1] = 0;
1169                 cardhu_pci_platform_data.port_status[2] = 1;
1170                 cardhu_pci_platform_data.use_dock_detect = 1;
1171                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
1172         }
1173         if ((board_info.board_id == BOARD_E1186) ||
1174                 (board_info.board_id == BOARD_E1187) ||
1175                 (board_info.board_id == BOARD_E1291)) {
1176                 tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
1177                 platform_device_register(&tegra_pci_device);
1178         }
1179 }
1180
1181 static void cardhu_modem_init(void)
1182 {
1183         struct board_info board_info;
1184         int w_disable_gpio, ret;
1185
1186         tegra_get_board_info(&board_info);
1187         switch (board_info.board_id) {
1188         case BOARD_E1291:
1189         case BOARD_E1198:
1190                 if (((board_info.board_id == BOARD_E1291) &&
1191                                 (board_info.fab < BOARD_FAB_A03)) ||
1192                         ((board_info.board_id == BOARD_E1198) &&
1193                                         (board_info.fab < BOARD_FAB_A02))) {
1194                         w_disable_gpio = TEGRA_GPIO_PH5;
1195                 } else {
1196                         w_disable_gpio = TEGRA_GPIO_PDD5;
1197                 }
1198
1199                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
1200                 if (ret < 0)
1201                         pr_err("%s: gpio_request failed for gpio %d\n",
1202                                 __func__, w_disable_gpio);
1203                 else
1204                         gpio_direction_input(w_disable_gpio);
1205
1206                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
1207                 if (((board_info.board_id == BOARD_E1291) &&
1208                                 (board_info.fab >= BOARD_FAB_A04)) ||
1209                         ((board_info.board_id == BOARD_E1198) &&
1210                                         (board_info.fab >= BOARD_FAB_A02))) {
1211                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
1212                         if (ret < 0) {
1213                                 pr_err("%s(): Error in allocating gpio "
1214                                         "TEGRA_GPIO_PH7\n", __func__);
1215                                 break;
1216                         }
1217                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
1218                 }
1219                 break;
1220         case BOARD_E1186:
1221                 platform_device_register(&tegra_baseband_power_device);
1222                 platform_device_register(&tegra_baseband_power2_device);
1223                 break;
1224         default:
1225                 break;
1226         }
1227
1228 }
1229
1230 #ifdef CONFIG_SATA_AHCI_TEGRA
1231 static void cardhu_sata_init(void)
1232 {
1233         platform_device_register(&tegra_sata_device);
1234 }
1235 #else
1236 static void cardhu_sata_init(void) { }
1237 #endif
1238
1239 static void __init tegra_cardhu_init(void)
1240 {
1241         tegra_thermal_init(&thermal_data);
1242         tegra_clk_init_from_table(cardhu_clk_init_table);
1243         tegra_enable_pinmux();
1244         cardhu_pinmux_init();
1245         cardhu_i2c_init();
1246         cardhu_spi_init();
1247         cardhu_usb_init();
1248 #ifdef CONFIG_TEGRA_EDP_LIMITS
1249         cardhu_edp_init();
1250 #endif
1251         cardhu_uart_init();
1252         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
1253         tegra_ram_console_debug_init();
1254         cardhu_sdhci_init();
1255         cardhu_regulator_init();
1256         cardhu_dtv_init();
1257         cardhu_suspend_init();
1258         cardhu_touch_init();
1259         cardhu_modem_init();
1260         cardhu_kbc_init();
1261         cardhu_scroll_init();
1262         cardhu_keys_init();
1263         cardhu_panel_init();
1264         cardhu_pmon_init();
1265         cardhu_sensors_init();
1266         cardhu_setup_bluesleep();
1267         cardhu_sata_init();
1268         //audio_wired_jack_init();
1269         cardhu_pins_state_init();
1270         cardhu_emc_init();
1271         tegra_release_bootloader_fb();
1272         cardhu_pci_init();
1273 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1274         tegra_wdt_recovery_init();
1275 #endif
1276 }
1277
1278 static void __init tegra_cardhu_reserve(void)
1279 {
1280 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
1281         /* support 1920X1200 with 24bpp */
1282         tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M);
1283 #else
1284         tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
1285 #endif
1286         tegra_ram_console_debug_reserve(SZ_1M);
1287 }
1288
1289 MACHINE_START(CARDHU, "cardhu")
1290         .atag_offset    = 0x100,
1291         .map_io         = tegra_map_common_io,
1292         .reserve        = tegra_cardhu_reserve,
1293         .init_early     = tegra30_init_early,
1294         .init_irq       = tegra_init_irq,
1295         .handle_irq     = gic_handle_irq,
1296         .timer          = &tegra_timer,
1297         .init_machine   = tegra_cardhu_init,
1298         .restart        = tegra_assert_system_reset,
1299 MACHINE_END